zink: set lower_uadd_carry in nir options

fixes a bunch of mulextended piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5685>

loader/dri3: Check for window destruction in dri3_wait_for_event_locked

If the underlying X11 window gets destroyed, the event we're waiting
for may never be delivered, in which case xcb_wait_for_special_event
would hang indefinitely.

Solution:

1. Use xcb_poll_for_special_event to check if an event has arrived yet.
2. If not, Wait up to ~1s for XCB's file descriptor to become readable;
   if it does, go back to step 1.
3. If the file descriptor didn't become readable, make a round-trip to
   the X server to check that the window still exists. Go back to step
   1 if it does, otherwise bail.

Also add an early bail-out when it's known that the window was
destroyed.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/116
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5368>

loader/dri3: Use dri3_wait_for_event_locked in loader_dri3_wait_for_msc

Before, if one thread ended up waiting in dri3_wait_for_event_locked
and another one in loader_dri3_wait_for_msc at the same time, one thread
could end up processing an event the other thread was waiting for, which
could result in the latter thread waiting longer than necessary
(possibly indefinitely).

Noticed by inspection.

v2:
* Drop xcb_flush call from loader_dri3_wait_for_msc in favour of the one
  in dri3_wait_for_event_locked (Kenneth Graunke)

Fixes: 7b0e8264dd21 "loader/dri3: Try to make sure we only process our
                     own NotifyMSC events"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5368>

loader/dri3: Add dri3_wait_for_event_locked full_sequence out parameter

Preparation for the next commit, no functional change intended.

Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5368>

v3d: Fix -Wmaybe-uninitialized compiler warning in the v33 code.

We weren't initializing the VCM bits in the !gs path, but v33 doesn't have
GS so we can just mark it unreachable.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2952>

v3d: Enable PIPE_CAP_TGSI_TEXCOORD.

Dave wants to drop the !TEXCOORD path from NIR, and it's easy enough to
do.  Untested.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2952>

vc4: Enable PIPE_CAP_TGSI_TEXCOORD.

Dave wants to drop the !TEXCOORD path from NIR, and it's easy enough to
do.  Untested.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2952>

gallium/util: Add a helper function for point sprite handling.

Many drivers will need to do the same thing here, so consolidate it.

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2952>

turnip: enable depthBiasClamp

Passes at least dEQP-VK.dynamic_state.rs_state.depth_bias_clamp

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>

turnip: enable largePoints

Passes dEQP-VK.rasterization.primitive_size.points.point_size_*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>

freedreno/regs: add extra bits for UBWC array pitch

This is not completely tested, but matches the max array pitch allowed by
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH.

Note this still doesn't allow all image sizes, but it allows 16384x16384
cpp=4 images to work.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5678>

frontends/va: Handle dynamic resolution/SVC for VP9

VP9 allows frame to use another resolution frame as reference
frames so updating the resolution for decoder when there is a
resolution change.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5646>

v3d/compiler: fix spill offset

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Fixes: 97566efe5cac0ff11b ("v3d: Rematerialize MOVs of uniforms instead of spilling them.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5664>

radv: add support for MRTs compaction to avoid holes

SPI_SHADER_COL_FORMAT allocates export memory and CB_SHADER_MASK
map them to higher MRTs if necessary. The hardware allows to remap
MRTs to avoid holes somehow.

For example, if we have a scenario where MRT0 is unused and only
MRT1 and MRT2 are used, SPI_SHADER_COL_FORMAT is 0x77 and
CB_SHADER_MASK/CB_TARGET_MASK are 0x770 (this assumes
SPI_SHADER_UINT16_ABGR is set).

This allows us to remove one workaround that was added for fixing
GPU hangs with DXVK. I think this is because SPI_SHADER_COL_FORMAT
expects contiguous MRTs to be allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5434>

radv: use SPI_SHADER_ZERO for non-written color attachments

When colorWriteMask is 0 we can assume that this color attachment
is unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5434>

radv: rework 8/16-bit color attachment formats detection

To prepare for MRTs compaction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5434>

radv: adjust CB_SHADER_MASK for dual-source blending in the shader info pass

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5434>

radv: enable VK_AMD_shader_ballot on GFX6-7 with both compiler backends

It gives +1-2 FPS with Doom Eternal on Pitcairn.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5659>

nir: Add new rules to optimize NOOP pack/unpack pairs

nir_load_store_vectorize_test.ssbo_load_adjacent_32_32_64_64 expectations
need to be fixed accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5589>

gallivm/nir: fix const loading on big endian systems

The code was expecting the lower 32-bits of the 64-bit to be
what it wanted, don't be implicit, pull the value from the union.

This should fix rendering on big endian systems since NIR was
introduced.

Fixes: 44a6b0107b37 ("gallivm: add nir->llvm translation (v2)")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5677>

freedreno/ir3: fix resinfo wrmask

resinfo always writes 3 components, which was not being taken into account

Fixes these tests:
dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_3
dEQP-VK.renderpass.suballocation.attachment_sparse_filling.input_attachment_7

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5674>

docs: use ref-links for internal references

Ref-link have two benefits over generic links:

1. They produce the right result for non-HTML outputs
2. They get validated at build-time

So let's use them for internal references instead.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5671>

docs: fix internal references

It seems last time I tried to fix these, I missed a few spots. So let's
try to get things right this time.

Fixes: 429ff054917 ("docs/relnotes: update internal references")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5671>

docs: restore accidentally dropped labels

These were accidentally dropped when cleaning up the TOC, making links to
them dead. Because we used plain links, sphinx didn't inform us that
these became dead. Let's restore them.

Fixes: 14f2a81b6f6 ("docs: drop open-coded toc for articles")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5671>

docs: remove non-existent reference

The section referenced here was removed a while ago, but it was always
empty anyway. Let's just remove it instead of trying to fix it up.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5671>

meson: Do not require shader cache for radv.

We fixed the compile error a while ago.

Fixes: cc10b34e9ed "util/disk_cache: Fix disk_cache_get_function_timestamp with disabled cache."
Reviewed-by: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5649>

rbug: Fix rbug_delete_vs_state lock acquisition.

Fix warning reported by Coverity Scan.

Double unlock (LOCK)
double_unlock: mtx_unlock unlocks rb_pipe->call_mutex while it is
unlocked.

Fixes: 07838ff990a7 ("rbug: Use the call mutex")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3023
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5196>

v3d: moving v3d simulator to src/broadcom

So it could be used by both the OpenGL and the Vulkan driver.

In addition to the move, some small changes were needed to be made on
the API. For example, the simulator was receiving v3d_screen on
initialization, and that code setted v3d_screen->sim_file. Now it
returns the new sim_file created.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5666>

turnip: Put VK_KHR_external_fence_fd stubs back

tu_ImportFenceFdKHR is used by tu_AcquireImageANDROID, which may or
may not work, but let's at least keep things compiling until somebody
has time to tie up the loose ends on the Android side.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5670>

iris: Implement pipe->texture_subdata directly

Chris Wilson noted that u_default_texture_subdata's transfer path
sometimes results in wasteful double copies.  This patch is based
on an earlier path he wrote, but updated now that we have staging
blits for busy or compressed textures.

Consider the case of idle, non-CCS-compressed, tiled images:

The transfer-based CPU path has to return a "linear" mapping, so upon
map, it mallocs a temporary buffer.  u_default_texture_subdata then
copies the client memory to this malloc'd buffer, and transfer unmap
performs a tiled_memcpy to copy it back into the texture.  By writing
a direct texture_subdata() implementation, we're able to directly do
a tiled_memcpy from the client memory into the destination texture,
resulting in only one copy.

For linear buffers, there is no advantage to doing things directly, so
we simply fall back to u_default_texture_subdata()'s transfer path to
avoid replicating those cases.

We still may want to use GPU staging buffers for busy destinations
(to avoid stalls) or CCS-compressed images (to compress the data),
at which point we also fall back to the existing path.  We thought
to try and use a tiled temporary, but this didn't appear to help.

Improves performance in x11perf -shmput500 by 1.96x on my Icelake.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2500
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3818>

turnip: Properly return VK_DEVICE_LOST on queuesubmit failures.

The device lost support closely matches the anv code for the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>

turnip: Fix error handling of DRM_MSM_GEM_INFO ioctls.

drmCommandWriteRead gives us a -errno, and we only checked for -1 (-EPERM,
incidentally).  All the callers wanted 0 for errors, which they were
getting by the fact that req.value was 0-initialized in our stack
allocation (though this only works as long as the kernel doesn't return an
error after setting req.value to something), and -EPERM not really being
an answer we would expect from an ioctl at this stage in the driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>

turnip: Do better TU_DEBUG=startup logging of drmGetDevices2() failure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>

turnip: semaphore support.

There is only one queue for now, so for non-shared semaphores, the
implementation is basically a no-op. For shared semaphores, this
always uses syncobjs. This depends on syncobj support in the msm
kernel driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>

ci/baremetal: Bump the kernel to a recent drm-msm-fixes for msm semaphores.

We need this to test the new VK feature we're about to land.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2769>

aco: fix partial copies on GFX6/7

While we don't allow partial subdword copies,
we still need to be able to split 64bit registers

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5663>

mapi: x86: Fix dynamic entries in x86 tsd stubs.

We need to update dynamic entries related code after updating
asm stubs.

Fixes: 45206d7673a ("mapi: Adapted libglvnd x86 tsd changes")
Signed-off-by: Lepton Wu <lepton@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5598>

ci/bare-metal: Fail early when we get stuck powering on a cheza.

I think I've seen about 3 of this error total so far, but waiting 60
minutes for the scripts to give up wastes marge time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5651>

freedreno/ir3: move nir finalization to after cache miss

In cases where every variant is a shader-cache-hit, we never need the
post-finalize round of nir opt/lowering passes.  So defer this until
the first shader-cache-miss to avoid doing pointless work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: disk-cache support

Adds a shader disk-cache for ir3 shader variants.  Note that builds with
`-Dshader-cache=false` have no-op stubs with `disk_cache_create()` that
returns NULL.

Binning pass variants are serialized together with their draw-pass
counterparts, due to shared const-state.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: build binning variant at same time as draw variant

For shader-cache, we are going to want to serialize them together.
Which is awkward if the two related variants are not compiled together.

This also decouples allocation and compile, which will simplify adding
shader-cache (which still needs to allocate, but can skip compile).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/a6xx+ir3: stop generating pointless binning shaders

Currently we always do sysmem if there is tess.  And for GS, the binning
pass VS ends up identical to the draw pass VS, so no point in compiling
it twice.  (For GS what we should do someday is generate a binning pass
GS, and possibly if we can do cross-stage linking opts, an optimized
binning pass VS, but the required outputs would somehow have to end up
in the shader variant key.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: shuffle some variant fields

Just to group together the parts that will get serialized when we have
shader disk-cache.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: add ir3_compiler_destroy()

Use ir3_compiler_destroy() rather than open-coding ralloc_free().  This
will give us a place to add more compiler related cleanup code in the
following patches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: move finalize_nir to pscreen hook

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

freedreno/ir3: add ir3_finalize_nir()

The next step is to hook this into pscreen->finalize_nir() so it can
come before the state tracker's shader-caching.

Unfortunately we still need to do lower_io after mesa/st, so that is
split out into a post-finalize pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5372>

zink: use OpFUnordNotEqual for nir_op_fne

we want to detect NaNs here, and OpFUnordNotEqual is the variant which does this

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: set lower_mul_high and lower_rotate in ntv compiler options

we don't implement these

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: handle isign alu in ntv

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: handle ixor in ntv

fixes spec@glsl-1.30@execution@built-in-functions@fs-op-assign-bitxor tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: lower byte/word extract ops in nir

we don't implement these, and pre-optimizing them breaks things in ntv->vtn

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: add bitfield_reverse handling to ntv

fixes several piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: add ult handling for ntv

fixes shaders@glsl-vs-absolutedifference-uint piglit test

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

zink: handle signed and unsigned min/max ops in ntv

fixes a number of piglit amd_shader_trinary_minmax tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5562>

radv: remove the load/store workaround for Monster Hunter World with LLVM

Now that ACO is default, this is pointless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>

radv: remove the shader ballot workaround for Youngblood with LLVM

Now that ACO is default, this is now pointless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>

docs: update favicon

I created a new and cleaner favicon for mesa3d.org, and it seems like a
good idea to use that one for the docs as well.

While we're at it, replace the original PNG with the original SVG asset
the ICO-file was generated from.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5643>

turnip: fix huge scissor min/max case

Now that tu_cs_emit_regs is used for the scissor, it hits an assert when
the scissor is too large. Fixes this dEQP test:

dEQP-VK.draw.scissor.static_scissor_max_int32

Fixes: 9c0ae5704d654108fd36b ("turnip: fix empty scissor case")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5655>

turnip: fix VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES

My attempt to be clever here backfired, it overwrites the pNext and stops
the loop (causing deqp to fail to query extension features after that).

Fixes: 62de79ac4492ac9e ("turnip: implement VK_KHR_shader_draw_parameters")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5654>

panfrost: Add PAN_MESA_DEBUG=gl3 flag

This flag allows forcing GL 3.3 without having to use
MESA_GL_VERSION_OVERRIDE etc.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5584>

freedreno/a6xx: use firstIndex field

Analogous to the turnip change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>

tu: Pass firstIndex directly to CP_DRAW_INDX_OFFSET

Saves some minor overhead, cleans things up a bit, and removes one more
unknown. We now program the internal registers in the same way between
direct/indirect draws.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>

freedreno/registers: Label firstIndex field in CP_DRAW_INDX_OFFSET

Based on comparing the implementations of CP_DRAW_INDX_OFFSET and
CP_DRAW_INDIRECT, this is what this field is for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>

freedreno: On a5xx+ INDX_SIZE is MAX_INDICES

This was already done correctly for the indirect variants, and turnip
was setting the correct value, but it seems freedreno missed the change
in the non-indirect variant. Also, fix a misspelling of "indices" and
add a type to INDX_SIZE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>

freedreno: Share constlen between different stages properly

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

freedreno: Refactor ir3_cache shader compilation

Use an array, which makes it more like turnip and makes implementing the
const limits easier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

tu: Share constlen between different stages properly

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

ir3: Add ir3_trim_constlen()

This provides the policy for how to handle reducing constlen for some
stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

ir3: Support variants with different constlen's

This provides the mechanism for compiling variants with a reduced
constlen. The next patch provides the policy for choosing which to
reduce.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

ir3: Include ir3_compiler from ir3_shader

I wanted to access the ir3_compiler from a small helper inside
ir3_shader.h, which currently isn't possible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

ir3, freedreno: Round up constlen earlier

Prevents problems when calculating whether we overflow the shared limit.
Note that on a6xx, the macros handle the assert for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>

v3d/compiler: don't rewrite unused temporaries to point to NOP register

This was assuming that unused temporaries are written but never read,
since the NOP register can only be used as a destination register,
but we can end up here also for temporaries that are read once but
never written.

This was found with a graphicsfuzz test that has a switch with
cases that have unreachable discards. In that test, NIR genrates
code like this:

decl_reg vec3 32 r19
...
r20 = mov r19.z
r21 = mov r19.y
r22 = mov r19.x

Where r19.xyz would generate 3 temporary registers that are read but
never written, so we would rewrite them to point to the NOP register
as QPU instruction sources, which is not allowed and would hit an
assert that expect magic reads to be from [r0,r5] only.

Fixes:
dEQP-VK.graphicsfuzz.unreachable-switch-case-with-discards

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5645>

v3d: Use stvpmd for non-uniform offsets in GS

The offset for the VPM write for storing outputs from the geometry
shader isn’t necessarily uniform across all the lanes. This can happen
if some of the lanes don’t emit some of the vertices. In that case the
offset for the subsequent vertices will be different in each lane. In
that case we need to use the stvpmd instruction instead of stvpmv
because it will scatter the values out.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3150
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>

v3d: Add missing macro for stvpmd instruction

stvpmd is like stvpmv but it scatters the output. It can be used with
non-dynamically uniform offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>

radeonsi: remove tabs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: clear per-context buffers at the end of si_create_context

We don't want any packets before CONTEXT_CONTROL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: make si_pm4_cmd_begin/end static and simplify all usages

There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state

The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: make wait_mem_scratch unmappable

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: don't add the tess ring buffers into the cs_preamble state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: rename init_config states to cs_preamble states

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

radeonsi: don't add the border color buffer into the init_config state

We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

ac,winsys/amdgpu: align IBs the same as the kernel

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

amd: add proper definitions for NOP packets

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

gitlab-ci: attach the Fossilize log file as artifact on failure

It might be help.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>

gitlab-ci: append Fossilize stdout/stderr to a file to reduce spam

Fossilize is really verbose and it's easy to reach the buffer
limit in GitLab CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>

gitlab-ci: set the number of Fossilize threads to 4

The shared runners are set up for concurrent jobs ~= CPUs / 4 (x86)
or 8 (ARM).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>

panfrost: Only copy resources when they are in a pending batch

Fixes a performance regression in alacritty, and rendering is still
fine in GLQuake ports.

Fixes: 361fb38662f ("panfrost: Copy resources when mapping to avoid waiting for readers")
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5642>

anv: Align "used" attribute to 64 bits.

This is a 64 bits value that might not be aligned on 32 bit plaforms.
Since it's used with atomics, let's make sure it gets properly aligned
to avoid any potential performance loss.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>

iris: Align last_seqnos to 64 bits.

last_seqnos is used in atomic operations. Specially on 32 bit platorms,
it tends to be slower if it's not aligned to 64 bits (see
cdc331c6f9f6b2ffc035018de4445dba9b67c1f7). This fixes a small regression
on Bioshock.

Fixes: aba3aed96e4 ("iris: fix export of GEM handles")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>

ci: Remove a stray "always" on the freedreno traces job.

This was making it so that the CI would error if the set of files modified
or the pipeline involvd meant the jobs we depend on weren't enabled.  It
was just some misplaced debug leftovers of mine.

Fixes: b88c46fa11ae ("ci: Add a freedreno a630 tracie run.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5653>

freedreno/a6xx: Add support for polygon fill mode (as long as front==back).

Unlike a4xx, we don't seem to have separate back vs front fields any more.
Still, this improves desktop GL conformance (and one of the traces in
traces-db).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>

turnip: Add support for polygon fill modes.

Passes the new tests in dEQP-VK.rasterization.culling.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>

freedreno/a6xx: Define the register fields for polygon fill mode.

Produced by comparing the traces of:
dEQP-VK.rasterization.culling.front_triangles
dEQP-VK.rasterization.culling.front_triangles_point
dEQP-VK.rasterization.culling.front_triangles_line

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>

ci: Add a freedreno a630 tracie run.

This job runs in about one minute on the current set of traces, and has
successfully revealed some bugs in our current rendering.  Takes about 7
minutes currently.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>

ci/tracie: Fix apitrace dump using "less" which isn't in the ARM rootfs.

You would get no output during the "find the last frame" step of the trace
replay.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>

ci/tracie: Print the path if the trace isn't found.

I hit this a few times while setting up CI.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>

ci: Include trace replay support in ARM rootfses.

Builds the renderdoc and apitrace programs so we can replay GL traces on
DUTs.

[Separated out from 5472's commit that also enabled the jobs in LAVA,
dropped unnecessary python packages from arm_build, fixed up arm64_test
build, traces-db in baremetal, new commit message by anholt]

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>

ci/bare-metal: Don't include dev packages in arm*test.

We just need these to build our rootfs, clean them out afterwards.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>

ci/bare-metal: Skip setting of unset variables at startup.

It's silly to be setting (and logging the setting of!) all the env vars we
*didn't* set in a job.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>