openpower-isa.git
2 years agoMissed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:24:38 +0000 (11:24 +0100)]
Missed another two form sub-headings

2 years agoMissed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:18:19 +0000 (11:18 +0100)]
Missed another two form sub-headings

2 years agoFixed missing space for form headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:15:49 +0000 (11:15 +0100)]
Fixed missing space for form headings

2 years agocompute 2nd svindex dimension using unsignee compare
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 00:45:09 +0000 (01:45 +0100)]
compute 2nd svindex dimension using unsignee compare

2 years agoadd yx svindex test, needed to compute size of 2nd dim
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 17:52:20 +0000 (18:52 +0100)]
add yx svindex test, needed to compute size of 2nd dim

2 years agoIndexed SVSHAPE add bypass mode when dim sizes are 1
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:50 +0000 (17:18 +0100)]
Indexed SVSHAPE add bypass mode when dim sizes are 1

2 years agoadd second svindex test, modulo 3
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:05 +0000 (17:18 +0100)]
add second svindex test, modulo 3

2 years agofix svindex pseudocode, set large 2nd dim on nonskip
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:17:09 +0000 (17:17 +0100)]
fix svindex pseudocode, set large 2nd dim on nonskip

2 years agofix svindex unit test, experiment setting dimensions
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 12:59:26 +0000 (13:59 +0100)]
fix svindex unit test, experiment setting dimensions
to 0b111111 in svindex pseudocode

2 years agofix SVSHAPE iterator for index case, stop deepcopy
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:26 +0000 (12:42 +0100)]
fix SVSHAPE iterator for index case, stop deepcopy
(was copying entire GPR)

2 years agoadd new svindex sv.add test with arbitrary index map
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:02 +0000 (12:42 +0100)]
add new svindex sv.add test with arbitrary index map

2 years agonon-persistence enabled on svindex as well as svremap
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:41:32 +0000 (12:41 +0100)]
non-persistence enabled on svindex as well as svremap

2 years agofix svindex pseudocode
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 10:53:56 +0000 (11:53 +0100)]
fix svindex pseudocode
rename RS to SVG in SVI-Form (svindex) to avoid a register name conflict
start checking things properly in test_caller_svindex.py

2 years agopass GPR to SVSHAPEs in ISACaller
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 21:12:06 +0000 (22:12 +0100)]
pass GPR to SVSHAPEs in ISACaller

2 years agoadd gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:45:12 +0000 (21:45 +0100)]
add gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)

2 years agorough unit test ahowing Index REMAP basically functional in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:26:28 +0000 (21:26 +0100)]
rough unit test ahowing Index REMAP basically functional in SVSHAPE

2 years agoadd support for Indexed mode in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 19:39:53 +0000 (20:39 +0100)]
add support for Indexed mode in SVSHAPE

2 years agoadd storing of shape in requested SVSHAPE in svindex pseudocode
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 12:58:21 +0000 (13:58 +0100)]
add storing of shape in requested SVSHAPE in svindex pseudocode

2 years agomove DX Form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 21:08:46 +0000 (22:08 +0100)]
move DX Form

2 years agoadd first stub of svindex pseudocode
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 17:54:07 +0000 (18:54 +0100)]
add first stub of svindex pseudocode
https://bugs.libre-soc.org/show_bug.cgi?id=885

2 years agoaudio/mp3: convert asm to the new notation
Dmitry Selyutin [Wed, 6 Jul 2022 17:33:43 +0000 (20:33 +0300)]
audio/mp3: convert asm to the new notation

https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agosvp64.py: allow macros as register names
Dmitry Selyutin [Wed, 6 Jul 2022 17:10:52 +0000 (17:10 +0000)]
svp64.py: allow macros as register names

This patch enables things like *fv0, where *fv0 is just a macro.
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agosvp64.py: generate registers
Dmitry Selyutin [Thu, 30 Jun 2022 13:11:25 +0000 (16:11 +0300)]
svp64.py: generate registers

2 years agoadd svindex to power_enums.py, minor_22.csv
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 16:55:36 +0000 (17:55 +0100)]
add svindex to power_enums.py, minor_22.csv
https://bugs.libre-soc.org/show_bug.cgi?id=867

2 years agoindentation on fields.txt to make it more markdown-like
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 15:55:28 +0000 (16:55 +0100)]
indentation on fields.txt to make it more markdown-like

2 years agoconvert Logical svp64_cases.py to new vector reg form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:37:17 +0000 (08:37 +0100)]
convert Logical svp64_cases.py to new vector reg form
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agoconvert ALU svp64_cases.py to new vector reg form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:23:28 +0000 (08:23 +0100)]
convert ALU svp64_cases.py to new vector reg form
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agoconverted test_caller_svstate.py to new reg format
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:12:06 +0000 (08:12 +0100)]
converted test_caller_svstate.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconvert test_caller_svp64.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 22:11:03 +0000 (22:11 +0000)]
convert test_caller_svp64.py to new vector numbering convention

2 years agoconvert test_caller_svp64_predication.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 22:04:00 +0000 (22:04 +0000)]
convert test_caller_svp64_predication.py to new vector numbering convention

2 years agoconvert test_caller_svp64_ldst.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 21:52:54 +0000 (21:52 +0000)]
convert test_caller_svp64_ldst.py to new vector numbering convention

2 years agoUpdated the nmigen.sim import
Andrey Miroshnikov [Tue, 5 Jul 2022 21:10:07 +0000 (21:10 +0000)]
Updated the nmigen.sim import

2 years agoconvert test_caller_svp64_fft.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 21:05:48 +0000 (21:05 +0000)]
convert test_caller_svp64_fft.py to new vector numbering convention

2 years agoconvert test_caller_svp64_bc.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 19:21:44 +0000 (19:21 +0000)]
convert test_caller_svp64_bc.py to new vector numbering convention

2 years agoconvert test_caller_svp64_dct.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 18:52:29 +0000 (18:52 +0000)]
convert test_caller_svp64_dct.py to new vector numbering convention

2 years agoconverted test_caller_svp64_matrix.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 18:01:30 +0000 (19:01 +0100)]
converted test_caller_svp64_matrix.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconverted test_caller_svp64_fp.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:57:07 +0000 (18:57 +0100)]
converted test_caller_svp64_fp.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconverted test_caller_svp64_mapreduce.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:51:41 +0000 (18:51 +0100)]
converted test_caller_svp64_mapreduce.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconvert test_caller_setvl.py to new vector numbering convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:34:08 +0000 (18:34 +0100)]
convert test_caller_setvl.py to new vector numbering convention
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoadd "*%" and "*" vector-numbering convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:21:55 +0000 (18:21 +0100)]
add "*%" and "*" vector-numbering convention
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoadd note about bug #884 new reg vector naming convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:19:29 +0000 (18:19 +0100)]
add note about bug #884 new reg vector naming convention

2 years agoadd regression test for completely borked value from mulhd
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 13:04:24 +0000 (14:04 +0100)]
add regression test for completely borked value from mulhd
https://bugs.libre-soc.org/show_bug.cgi?id=855

2 years agotake deepcopy of regs passed in to avoid accidental modification
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 13:02:29 +0000 (14:02 +0100)]
take deepcopy of regs passed in to avoid accidental modification

2 years agoadd setvl CTR tests, fix CTR mode
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 17:11:59 +0000 (18:11 +0100)]
add setvl CTR tests, fix CTR mode

2 years agofix setvl CTR mode
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 16:59:34 +0000 (17:59 +0100)]
fix setvl CTR mode

2 years agosetvl has new CTR mode, making room in encoding needed
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 16:37:47 +0000 (17:37 +0100)]
setvl has new CTR mode, making room in encoding needed
fixing unit tests

2 years agodo CSV isatables explicitly in sv_analysis.py
Luke Kenneth Casson Leighton [Thu, 30 Jun 2022 11:33:47 +0000 (12:33 +0100)]
do CSV isatables explicitly in sv_analysis.py
for pandoc to pick up

2 years agoexplicit output of opcode_regs_deduped in mdwn table format
Luke Kenneth Casson Leighton [Thu, 30 Jun 2022 11:04:27 +0000 (12:04 +0100)]
explicit output of opcode_regs_deduped in mdwn table format
so as to make it possible to convert to latex with pandoc

2 years agoadd recognition of "sv." to pysvp64asm
Luke Kenneth Casson Leighton [Tue, 28 Jun 2022 16:30:28 +0000 (17:30 +0100)]
add recognition of "sv." to pysvp64asm

2 years agoremove qemu co-simulation, dump output expected results
Luke Kenneth Casson Leighton [Tue, 28 Jun 2022 15:23:38 +0000 (16:23 +0100)]
remove qemu co-simulation, dump output expected results
test/basic_pypowersim

2 years agoadd predicate mask test svstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:33:06 +0000 (23:33 +0100)]
add predicate mask test svstep

2 years agowhoops svp64.py testing wrong variable on sv.svstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:13:27 +0000 (23:13 +0100)]
whoops svp64.py testing wrong variable on sv.svstep

2 years agoadd predicated srcstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:04:29 +0000 (23:04 +0100)]
add predicated srcstep

2 years agomake svstep output srcstep/dststep, basically viota
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 21:56:01 +0000 (22:56 +0100)]
make svstep output srcstep/dststep, basically viota

2 years agorename SVRM *field* to SVrm to avoid a name-clash with
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 17:23:35 +0000 (18:23 +0100)]
rename SVRM *field* to SVrm to avoid a name-clash with
SVRM-*Form*

2 years agosvp64.py: decrement SVd operand
Dmitry Selyutin [Sun, 26 Jun 2022 17:10:19 +0000 (20:10 +0300)]
svp64.py: decrement SVd operand

2 years agosvp64.py: fix ignored field range
Dmitry Selyutin [Sun, 26 Jun 2022 16:06:12 +0000 (19:06 +0300)]
svp64.py: fix ignored field range

2 years agosvp64.py: drop commented code
Dmitry Selyutin [Sun, 26 Jun 2022 15:59:20 +0000 (18:59 +0300)]
svp64.py: drop commented code

2 years agosvp64.py: fix fsins/fcoss X-FORM
Dmitry Selyutin [Sun, 26 Jun 2022 15:42:23 +0000 (18:42 +0300)]
svp64.py: fix fsins/fcoss X-FORM

2 years agoagain fix number of arguments to svremap,
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 09:27:04 +0000 (10:27 +0100)]
again fix number of arguments to svremap,
test_caller_svp64_ldst.py

2 years agowhitespace
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 09:23:49 +0000 (10:23 +0100)]
whitespace

2 years agotest_caller_svstate.py: end-of-loop condition sets CR.SO not CR.EQ
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:59:39 +0000 (09:59 +0100)]
test_caller_svstate.py: end-of-loop condition sets CR.SO not CR.EQ

2 years agosvp64_matrix.py svremap reduce to 7 args from 8 (again)
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:46:32 +0000 (09:46 +0100)]
svp64_matrix.py svremap reduce to 7 args from 8 (again)

2 years agosvremap only takes 7 args not 8, same as in svp64_fft.py
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:35:17 +0000 (09:35 +0100)]
svremap only takes 7 args not 8, same as in svp64_fft.py
fix in svp64_dct.py

2 years agoone too many arguments to svremap in svp64_fft.py test
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:24:46 +0000 (09:24 +0100)]
one too many arguments to svremap in svp64_fft.py test

2 years agowhoops hack-use of DOUBLE2SINGLE in test_caller_transcendentals.py
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:20:41 +0000 (09:20 +0100)]
whoops hack-use of DOUBLE2SINGLE in test_caller_transcendentals.py

2 years agosvp64.py: sync SVRM-Form used for svshape
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:15:12 +0000 (09:15 +0100)]
svp64.py: sync SVRM-Form used for svshape

2 years agosvp64.py: fix svshape and setvl plus couple of oddities
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:01:40 +0000 (09:01 +0100)]
svp64.py: fix svshape and setvl plus couple of oddities

* svstep RT,SVi,vf
but the Form is 8 fields
* setvl RT,RA,SVi,vf,vs,ms
the order of those is *different* from the "natural" order in the
SVL-Form

2 years agosvp64.py: add -FORM headers to more functions
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 07:39:23 +0000 (08:39 +0100)]
svp64.py: add -FORM headers to more functions

2 years agosvp64.py: fix bmask entry
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 07:33:42 +0000 (08:33 +0100)]
svp64.py: fix bmask entry

2 years agosvp64.py: group 32-bit instructions into the table
Dmitry Selyutin [Sat, 25 Jun 2022 20:51:29 +0000 (23:51 +0300)]
svp64.py: group 32-bit instructions into the table

The pysvp64asm code became really dirty with the addition of new
instructions, it's almost impossible to keep track of it. Some
instructions were not converted at all, due to incorrect check (all but
setvl/svshape). Some had wrong operand names (fsins, fcoss used RT, RA
operands, and this does not follow the spec). Some instructions had no
SV support, despite the fact they should (fsins).

This all became barely maintainable. From now on, instructions are
grouped into a special table. Ideally we should generate this table
from fields.txt, but there's no time for writing yet another parser.

2 years agosvp64.py: align indentation
Dmitry Selyutin [Sat, 25 Jun 2022 15:57:53 +0000 (18:57 +0300)]
svp64.py: align indentation

2 years agoadd test case for kaivb to jump to 0x2700
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 11:56:59 +0000 (12:56 +0100)]
add test case for kaivb to jump to 0x2700

2 years agoadd TrapTestCase for KAIVB
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 11:39:31 +0000 (12:39 +0100)]
add TrapTestCase for KAIVB
https://bugs.libre-soc.org/show_bug.cgi?id=859

2 years agohmm do expected state in rfid trap case
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 11:15:14 +0000 (12:15 +0100)]
hmm do expected state in rfid trap case

2 years agocorrect input example for SOF case_3_bmask
Luke Kenneth Casson Leighton [Sat, 25 Jun 2022 20:08:32 +0000 (21:08 +0100)]
correct input example for SOF case_3_bmask

2 years agoAdded sif/sof
Andrey Miroshnikov [Sat, 25 Jun 2022 19:37:02 +0000 (19:37 +0000)]
Added sif/sof

2 years agocorrections to test cases, it is not quite
Luke Kenneth Casson Leighton [Sat, 25 Jun 2022 19:25:43 +0000 (20:25 +0100)]
corrections to test cases, it is not quite
as "obvious" as it looks due to the masking

2 years agoupdate comments in av_cases.py test_1_bmask
Luke Kenneth Casson Leighton [Sat, 25 Jun 2022 19:07:13 +0000 (20:07 +0100)]
update comments in av_cases.py test_1_bmask

2 years agocorrect undefined in av.mdwn bmask
Luke Kenneth Casson Leighton [Sat, 25 Jun 2022 19:01:12 +0000 (20:01 +0100)]
correct undefined in av.mdwn bmask

2 years agoAdded second bmask test case, designed to be multi-test
Andrey Miroshnikov [Fri, 24 Jun 2022 22:14:38 +0000 (22:14 +0000)]
Added second bmask test case, designed to be multi-test

2 years agoadd svindex XO field 101001
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 21:20:47 +0000 (22:20 +0100)]
add svindex XO field 101001

2 years agorename mask to rmm in svindex
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 20:58:26 +0000 (21:58 +0100)]
rename mask to rmm in svindex

2 years agorename mask field to rmm to avoid using "mask" in binutils
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 20:57:35 +0000 (21:57 +0100)]
rename mask field to rmm to avoid using "mask" in binutils
https://libre-soc.org/irclog/%23libre-soc.2022-06-24.log.html#t2022-06-24T20:27:25

2 years agosvp64.py: support svindex instruction
Dmitry Selyutin [Fri, 24 Jun 2022 18:49:23 +0000 (21:49 +0300)]
svp64.py: support svindex instruction

2 years agoadd SVd to fields.txt (SVI-Form)
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 18:29:43 +0000 (19:29 +0100)]
add SVd to fields.txt (SVI-Form)
missed out description

2 years agoadd first bmask unit test
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:51:30 +0000 (15:51 +0100)]
add first bmask unit test

2 years agoinvert mode-bits in bmask bm field
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:51:02 +0000 (15:51 +0100)]
invert mode-bits in bmask bm field

2 years agobmask does not have Rc=1 variant
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:50:40 +0000 (15:50 +0100)]
bmask does not have Rc=1 variant

2 years agosigh, bm not mode argument to bmask
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:17:27 +0000 (15:17 +0100)]
sigh, bm not mode argument to bmask
plus the offsets (sub-fields) of bm were completely wrong

2 years agocorrect bmask conversion to binary (wrong instruction used
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:12:33 +0000 (15:12 +0100)]
correct bmask conversion to binary (wrong instruction used
as a beginning template)

2 years agoadd bmask to instruction list
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 14:11:42 +0000 (15:11 +0100)]
add bmask to instruction list

2 years agoadd to fields.txt for the svstep instruction
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 11:05:26 +0000 (12:05 +0100)]
add to fields.txt for the svstep instruction
which misses out some fields

2 years agoadd svindex SVI-Form to fields.txt
Luke Kenneth Casson Leighton [Fri, 24 Jun 2022 10:54:25 +0000 (11:54 +0100)]
add svindex SVI-Form to fields.txt

2 years agoadd missed generated csv changes
Jacob Lifshay [Fri, 24 Jun 2022 05:01:36 +0000 (22:01 -0700)]
add missed generated csv changes

2 years agoadd BM2-Form to power_enums.py
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:13:47 +0000 (17:13 +0100)]
add BM2-Form to power_enums.py

2 years agoelse must be on separate line in pseudocode av.mdwn
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:11:59 +0000 (17:11 +0100)]
else must be on separate line in pseudocode av.mdwn

2 years agomissing "Special Registers Altered" on av.mdwn
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:10:10 +0000 (17:10 +0100)]
missing "Special Registers Altered" on av.mdwn

2 years agoAdded bmask, pywriter failing
Andrey Miroshnikov [Thu, 23 Jun 2022 14:55:01 +0000 (14:55 +0000)]
Added bmask, pywriter failing

2 years agoadd SPDX-License-Headers to CSV files
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 09:53:40 +0000 (10:53 +0100)]
add SPDX-License-Headers to CSV files
(now that comments are possible)
mention provenance from microwatt decode1.vhdl