Danylo Piliaiev [Fri, 13 Mar 2020 14:06:07 +0000 (16:06 +0200)]
nir: Fix breakage of foreach_list_typed_safe assumptions in loop unrolling
foreach_list_typed_safe works with assumption that even if current node
becomes invalid, the next will be still valid.
However process_loops broke this assumption, because during iteration
when immediate child is unrolled - not only current node could be removed
but also the one after it.
This doesn't cause issues now but it will cause issues when undefined
behaviour in foreach* macros is fixed.
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4189>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4189>
Pierre-Eric Pelloux-Prayer [Fri, 27 Mar 2020 19:42:29 +0000 (20:42 +0100)]
radeon: switch to 3-spaces style
For clang-format config see the previous commit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Pierre-Eric Pelloux-Prayer [Fri, 27 Mar 2020 18:32:38 +0000 (19:32 +0100)]
radeonsi: switch to 3-spaces style
Generated automatically using clang-format and the following config:
AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
AlwaysBreakAfterReturnType: None
BasedOnStyle: LLVM
BraceWrapping:
AfterControlStatement: false
AfterEnum: true
AfterFunction: true
AfterStruct: false
BeforeElse: false
SplitEmptyFunction: true
BinPackArguments: true
BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
ForEachMacros:
- LIST_FOR_EACH_ENTRY
- LIST_FOR_EACH_ENTRY_SAFE
- util_dynarray_foreach
- nir_foreach_variable
- nir_foreach_variable_safe
- nir_foreach_register
- nir_foreach_register_safe
- nir_foreach_use
- nir_foreach_use_safe
- nir_foreach_if_use
- nir_foreach_if_use_safe
- nir_foreach_def
- nir_foreach_def_safe
- nir_foreach_phi_src
- nir_foreach_phi_src_safe
- nir_foreach_parallel_copy_entry
- nir_foreach_instr
- nir_foreach_instr_reverse
- nir_foreach_instr_safe
- nir_foreach_instr_reverse_safe
- nir_foreach_function
- nir_foreach_block
- nir_foreach_block_safe
- nir_foreach_block_reverse
- nir_foreach_block_reverse_safe
- nir_foreach_block_in_cf_node
IncludeBlocks: Regroup
IncludeCategories:
- Regex: '<[[:alnum:].]+>'
Priority: 2
- Regex: '.*'
Priority: 1
IndentWidth: 3
PenaltyBreakBeforeFirstCallParameter: 1
PenaltyExcessCharacter: 100
SpaceAfterCStyleCast: false
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: false
SpacesInContainerLiterals: false
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Pierre-Eric Pelloux-Prayer [Fri, 27 Mar 2020 19:33:13 +0000 (20:33 +0100)]
radeon: fix includes
And add required forward declarations.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Pierre-Eric Pelloux-Prayer [Fri, 27 Mar 2020 19:34:09 +0000 (20:34 +0100)]
ddebug: add missing forward declaration
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319>
Daniel Stone [Tue, 28 Jan 2020 12:47:20 +0000 (12:47 +0000)]
meson: Add VS 4624 warning exclusion to remove piles of LLVM warnings
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
Erik Faye-Lund [Tue, 14 Jan 2020 10:56:13 +0000 (11:56 +0100)]
meson: disable some more warnings on msvc
These warnings triggers for me, and they are harmless as-is. Let's
disable them to avoid hiding actually scary warnings.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4343>
Daniel Stone [Mon, 30 Mar 2020 09:16:18 +0000 (10:16 +0100)]
CI: Avoid htz4 runner for VS2019
The htz4 runner needs to be updated in order for our support binaries
like Chocolatey to work. Temporarily restrict jobs to the EC2 runner
until this has happened.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4371>
Eric Engestrom [Fri, 27 Mar 2020 23:28:33 +0000 (00:28 +0100)]
intel: drop unused include directories
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Eric Engestrom [Tue, 5 Mar 2019 16:55:02 +0000 (16:55 +0000)]
vulkan: drop unused include directories
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Eric Engestrom [Tue, 5 Mar 2019 16:21:47 +0000 (16:21 +0000)]
meson: inline `inc_common`
Let's make it clear what includes are being added everywhere, so that
they can be cleaned up.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Eric Engestrom [Tue, 5 Mar 2019 10:40:51 +0000 (10:40 +0000)]
meson: use existing variables in inc_common
Stepping stone to make review of the next commits easier.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4360>
Vinson Lee [Sat, 28 Mar 2020 02:56:10 +0000 (19:56 -0700)]
mesa: Change _mesa_exec_malloc argument type.
Fix build error.
In file included from ../src/mesa/x86/rtasm/x86sse.c:7:0:
../src/mesa/main/execmem.h:31:19: error: unknown type name ‘GLuint’; did you mean ‘uint’?
_mesa_exec_malloc(GLuint size);
^~~~~~
uint
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Fixes: e5339fe4a47c ("Move compiler.h and imports.h/c from src/mesa/main into src/util")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4361>
Michel Dänzer [Mon, 23 Mar 2020 17:16:07 +0000 (18:16 +0100)]
gitlab-ci: Update to current templates
The .fdo.container-ifnot-exists template has been replaced by
.fdo.container-build.
We need to include "debian/" in FDO_REPO_SUFFIX for now, we can drop it
for individual images when their tags are bumped if we want.
Miscellaneous other goodies this gets us:
* The templates now add some labels to images which may be useful for
garbage collecting unused tags in the future.
* The templates now copy the current tag from the main project
registry to the forked project's if it already exists in the latter
but points to a different image hash. This will avoid false failures
(or passes) due to using the wrong image.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4286>
Tomeu Vizoso [Fri, 27 Mar 2020 14:31:45 +0000 (15:31 +0100)]
Revert "gitlab-ci: Disable jobs for Collabora's LAVA lab"
Lab is online again.
This reverts commit
1351ee03352b12690233a73e160f92da2edecf16.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4347>
Marek Olšák [Fri, 20 Mar 2020 21:34:15 +0000 (17:34 -0400)]
radeonsi/gfx10: fix descriptors and compute registers for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:35:56 +0000 (17:35 -0400)]
radeonsi/gfx10: fix the wave size for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:34:59 +0000 (17:34 -0400)]
radeonsi/gfx10: user correct ACQUIRE_MEM packet for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:30:33 +0000 (17:30 -0400)]
radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:45:17 +0000 (17:45 -0400)]
radeonsi/gfx10: don't use NGG culling if compute-based culling is used
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Sat, 21 Mar 2020 01:12:38 +0000 (21:12 -0400)]
radeonsi: add num_vbos_in_user_sgprs into the shader cache key
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 22:20:52 +0000 (18:20 -0400)]
radeonsi: always create wait_mem_scratch for compute-based culling
used by the primitive restart emulation
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 22:02:20 +0000 (18:02 -0400)]
radeonsi: set amdgpu-gds-size for mode == 2 of compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:32:11 +0000 (17:32 -0400)]
radeonsi: fix incorrect ordered_wave_id initilization for compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Marek Olšák [Fri, 20 Mar 2020 21:30:10 +0000 (17:30 -0400)]
radeonsi: remove obsolete TODO comment related to compute-based culling
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>
Vasily Khoruzhick [Mon, 23 Mar 2020 06:12:06 +0000 (23:12 -0700)]
lima: Implement lima_texture_subdata
We can avoid intermediate copy if we implement it ourselves.
Improves x11perf -shmput500 from 199.0/s to 283.0/s
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4281>
Rob Clark [Fri, 27 Mar 2020 23:34:27 +0000 (16:34 -0700)]
gitlab-ci: disable vs2019 build
Seems to be broken atm and blocking merging anything.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Thu, 26 Mar 2020 17:45:54 +0000 (10:45 -0700)]
freedreno/ir3/ra: re-work a6xx merged register file conflicts
In particular setup the full/half conflicts first. This avoids spurious
conflicts that where causing RA to place vecN half-regs poorly.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Thu, 26 Mar 2020 17:25:04 +0000 (10:25 -0700)]
freedreno/ir3/ra: split building regs/classes and conflicts
Split out the construction of registers and classes (which is the same
on all gens) from setting up conflicts. Prep to re-work how we setup
conflicts on a6xx+ which merged half/full register file.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Mon, 23 Mar 2020 17:25:38 +0000 (10:25 -0700)]
freedreno/ir3/ra: pick higher numbered scalars in first pass
Since we are re-assigning the scalars anyways in the second pass, assign
them to the highest free reg in the first pass (rather than lowest) to
allow packing vecN regs as low as possible.
Note this required some changes specifically for tex instructions with a
single component writemask that is not necessarily .x, as previously
these would get assigned in the first RA pass, and since they are still
scalar, we'd end up w/ some r47.* and other similarly way-to-high
assignments after the 2nd pass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Fri, 20 Mar 2020 16:14:36 +0000 (09:14 -0700)]
freedreno/ir3/ra: compute register target from liveranges
Using the output of the first pass isn't ideal, as it can bake in the
losses from fragmentation which the scalar pass is intended to fill in.
This gets worse when we start using "vectorish" instructions, due to
higher use of vecN values.
Instead, we can just use the outputs of the liveness analysis to get a
more accurate # of maximum live values at any point.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sun, 22 Mar 2020 19:37:12 +0000 (12:37 -0700)]
freedreno/ir3/ra: fix array liveranges
Fixes: 1b658533e11 ("freedreno/ir3: extend liverange of arrays")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 21:44:44 +0000 (14:44 -0700)]
freedreno/ir3/ra: add def/use iterators
Decouple the messy logic of figuring out vreg names defined/used by an
instruction from the logic of what to do about it by introducing
iterators. There is still *some* array vs ssa special casing in
ra_block_compute_live_ranges(), but less than before. And this will
avoid introducing a second copy of the def/use logic in a following
patch which uses the liveranges to calculate the maximum # of live
values (which is the optimal target for max physical register window
to round-robin within).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 20:29:37 +0000 (13:29 -0700)]
freedreno/ir3/ra: drop extending output live-ranges
This is no longer needed as we create meta:collect instructions in the
end block, which achieves the same result.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 18:25:36 +0000 (11:25 -0700)]
freedreno/ir3/ra: add helper to map name to array
For vreg names that refer to arrays rather than SSA values, this is the
counterpart to name_to_instr().
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 18:07:35 +0000 (11:07 -0700)]
freedreno/ir3/ra: fix target register calculation
Account for the # of regs an instruction writes, and fix an off-by-one.
(We are about to replace this with calculating the register target using
the live-ranges, but in debugging that it was useful to assert() if it
chose a higher target.)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Thu, 19 Mar 2020 23:29:57 +0000 (16:29 -0700)]
freedreno/ir3/ra: add helper to map name to instruction
Extract out a helper from the select_reg callback. And include all the
instructions in the hashtable, not just SFU. This will be useful in the
following commits.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 17:33:48 +0000 (10:33 -0700)]
freedreno/ir3/ra: split-up
Split out regset and shared header, since the RA pass is already getting
large-ish.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Mon, 23 Mar 2020 15:58:07 +0000 (08:58 -0700)]
freedreno/ir3/ra: add debug option for RA debug msgs
Similar to the debug switch for sched debug msgs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Fri, 6 Mar 2020 16:46:43 +0000 (08:46 -0800)]
freedreno/ir3: convert debug bitfield to BITFIELD_BIT()
(Little more verbose than the kernel's BIT())
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Fri, 6 Mar 2020 16:43:35 +0000 (08:43 -0800)]
freedreno/ir3: reformat disasm output
In particular, make sure we see all the shader-db stats. The format
(order) is the sameish, except split across multiple lines to make it
easier to read.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 20:13:34 +0000 (13:13 -0700)]
freedreno/ir3: fix bogus register footprint with tess/gs
When we have a tess or gs stage, VS outputs aren't normal varyings, so
regid is r63.x.. we shouldn't extend our registerfootprint to 64!
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Thu, 12 Mar 2020 21:16:38 +0000 (14:16 -0700)]
freedreno/ir3: remove unused helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Fri, 20 Mar 2020 18:50:46 +0000 (11:50 -0700)]
freedreno/ir3: add bary_ij as src for meta:tex_prefetch
This way RA doesn't have to special case it in use/def accounting..
This gets rid of an extra level of split/collect, which shouldn't be
needed. And interferes with scheduler trying to put tex-prefetches
after inputs but before other instructions. (Otherwise it would have
to figure out which split/collects need to go before the tex-prefetch)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 18:06:59 +0000 (11:06 -0700)]
freedreno/ir3: small cleanup and comments
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Rob Clark [Sat, 21 Mar 2020 16:49:27 +0000 (09:49 -0700)]
freedreno/a6xx: register update
No functional change, and this register isn't used in userspace. Just
syncing from envytools tree to eliminate the delta.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4272>
Daniel Stone [Fri, 27 Mar 2020 21:20:11 +0000 (21:20 +0000)]
CI: Disable Panfrost Mali-T820 jobs
The BayLibre T820 runners appear to be unhealthy.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4359>
Marek Olšák [Thu, 26 Mar 2020 03:47:36 +0000 (23:47 -0400)]
util: remove duplicated MALLOC_STRUCT and CALLOC_STRUCT
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Marek Olšák [Thu, 26 Mar 2020 03:44:59 +0000 (23:44 -0400)]
util: don't include p_defines.h and u_pointer.h from gallium
It's a mess, but this is what I arrived at.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Marek Olšák [Thu, 26 Mar 2020 01:30:55 +0000 (21:30 -0400)]
radv: stop including files from mesa/main
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Marek Olšák [Thu, 26 Mar 2020 01:26:24 +0000 (21:26 -0400)]
util: stop including files from mesa/main
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Marek Olšák [Thu, 26 Mar 2020 01:13:48 +0000 (21:13 -0400)]
mesa: don't use <> for including internal headers
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Marek Olšák [Thu, 26 Mar 2020 01:11:44 +0000 (21:11 -0400)]
Move compiler.h and imports.h/c from src/mesa/main into src/util
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4324>
Jesse Natalie [Tue, 17 Mar 2020 17:53:33 +0000 (10:53 -0700)]
wgl: use gldrv.h instead of stw_icd.h
Now that we have the official header, let's use that instead of
stw_icd.h.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
Jesse Natalie [Tue, 17 Mar 2020 17:53:33 +0000 (10:53 -0700)]
wgl: add official gldrv.h header-file
This is the official, Microsoft-provided gldrv.h that describes the
driver-interface for OpenGL drivers on Windows.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4305>
Karol Herbst [Fri, 20 Sep 2019 18:27:20 +0000 (20:27 +0200)]
nv50, nvc0: fix must_check warning of util_dynarray_resize_bytes
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
Erik Faye-Lund [Thu, 26 Mar 2020 10:50:10 +0000 (11:50 +0100)]
nv50: remove unused variable
This isn't used anymore, so let's get rid of it to silence a warning.
Fixes: c574cda3c6a ("util: Make helper functions for pack/unpacking pixel rows.")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4330>
Lionel Landwerlin [Mon, 2 Mar 2020 12:00:55 +0000 (14:00 +0200)]
intel/perf: store the probed i915-perf version
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Lionel Landwerlin [Mon, 2 Mar 2020 11:52:49 +0000 (13:52 +0200)]
intel/perf: document meaning of query field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Lionel Landwerlin [Wed, 4 Sep 2019 11:10:22 +0000 (14:10 +0300)]
intel/perf: move mdapi query definitions to their own file
Where they belong.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Lionel Landwerlin [Wed, 4 Sep 2019 10:52:13 +0000 (13:52 +0300)]
intel/perf: break GL query stuff away
This stuff is somewhat specific to the GL extension & drivers. On
Vulkan we won't use this, it also made a rather large file.
v2: Fix Android build (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Lionel Landwerlin [Wed, 13 Nov 2019 13:21:00 +0000 (15:21 +0200)]
intel/perf: move register definition to special file
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4344>
Andres Gomez [Sun, 8 Mar 2020 00:05:08 +0000 (02:05 +0200)]
gitlab-ci/traces: Add D3D11 sample entry for POLARIS10
v2:
- Updated traces-db commit.
- Changed the reference DXVK trace.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Andres Gomez [Fri, 20 Mar 2020 18:26:48 +0000 (20:26 +0200)]
gitlab-ci: add Wine and DXVK env variables to Vulkan's tracie runner
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Andres Gomez [Wed, 18 Mar 2020 14:39:49 +0000 (16:39 +0200)]
gitlab-ci: replay apitrace traces in headless mode
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Andres Gomez [Sun, 8 Mar 2020 21:40:04 +0000 (23:40 +0200)]
gitlab-ci: add apitrace's DXGI traces support
v2:
- Pass the whole retrace command for apitrace traces (Alexandros).
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Andres Gomez [Sun, 8 Mar 2020 21:37:23 +0000 (23:37 +0200)]
gitlab-ci: add Wine, win64's apitrace and DXVK to the Vulkan testing container
In preparation for having automated testing with DXGI traces.
v2:
- Updated DXVK version.
- Merged the new Wine container into the existing Vulkan
one (Michel).
v3:
- Updated commit log.
- Use a particular known-good apitrace version (Alexandros).
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Andres Gomez [Thu, 26 Mar 2020 21:00:15 +0000 (23:00 +0200)]
gitlab-ci: Don't use buster-backports packages by default for x86_test-vk
The backports repository can be temporarily inconsistent between
architectures, which can break the docker image build.
Suggested-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4238>
Daniel Stone [Fri, 27 Mar 2020 13:22:37 +0000 (13:22 +0000)]
CI: Windows: Fix Docker tag argument inversion
docker tag takes its arguments as source and dest, not dest and source.
Went unnoticed as the host already had a tag for my image when I was
testing.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4346>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4346>
Daniel Stone [Tue, 24 Mar 2020 11:11:36 +0000 (11:11 +0000)]
CI: Add native Windows VS2019 build
Adds a native build of Mesa using Meson with the Visual Studio 2019
toolchain on a Windows host.
Though Docker is supported on Windows, Docker-in-Docker is not possible,
nor are podman and skopeo available. We handle this by creating the
container from a shell-executor Windows machine, which gives us a native
PowerShell that we can execute Docker from. This attempts to do the same
copy-from-upstream-or-create-if-not-exists optimisation as the
ci-templates do for our Linux builds, albeit open-coded in PowerShell.
The Mesa build itself is executed inside a container, using Meson and
Ninja.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Brian Paul <brianp@vmware.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
Daniel Stone [Thu, 26 Mar 2020 13:01:58 +0000 (13:01 +0000)]
util/test: Use MAX_PATH on Windows
Windows provides MAX_PATH rather than PATH_MAX for the maximum allowable
path length. This is not a limit on the length of filename which can
exist on the filesystem, but a length on the length of path which can be
passed to Win32 API calls.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070a ("util/u_process: add util_get_process_exec_path")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
Pierre-Eric Pelloux-Prayer [Thu, 26 Mar 2020 13:07:39 +0000 (14:07 +0100)]
util: fix process_test path
Make sure we only use winepath when needed.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: f8f1413070a ("util/u_process: add util_get_process_exec_path")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2690
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4304>
Tomeu Vizoso [Fri, 27 Mar 2020 08:25:17 +0000 (09:25 +0100)]
gitlab-ci: Disable jobs for Collabora's LAVA lab
The lab is going down for a few hours to upgrade the LAVA installation
to the latest stable release.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4342>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4342>
Timothy Arceri [Thu, 26 Mar 2020 01:23:23 +0000 (12:23 +1100)]
nir: fix packing of TCS varyings not read by the TES
Unlike other stages TCS outputs not read by the TES cannot always
be demoted to globals e.g. when they are read by other TCS
invocations.
We were not taking these outputs into account when packing which
could result in other outputs being assigned to the same location.
Here we make sure to gather information on these outputs and group
them together when packing.
This fixes rendering issues in QUBE 2 via Proton.
Closes: #2653
Fixes: 26aa460940f6 ("nir: rewrite varying component packing")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Timothy Arceri [Thu, 26 Mar 2020 08:03:51 +0000 (19:03 +1100)]
glsl: fix varying packing for 64bit integers
Without this we can incorrectly end up marking things as making
use of ARB_enhanced_layouts style packing.
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4328>
Samuel Pitoiset [Thu, 26 Mar 2020 10:40:35 +0000 (11:40 +0100)]
ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv()
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
No pipeline-db changes with VEGA10/LLVM 9.
pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 6672 -> 6672 (0.00 %)
VGPRS: 6652 -> 6652 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 561780 -> 561692 (-0.02 %) bytes
Max Waves: 1043 -> 1043 (0.00 %)
pipeline-db (VEGA10/LLVM 11 -
92744f62478):
Totals from affected shaders:
SGPRS: 84608 -> 83768 (-0.99 %)
VGPRS: 106768 -> 106636 (-0.12 %)
Spilled SGPRs: 1625 -> 1713 (5.42 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size:
10850936 ->
10726712 (-1.14 %) bytes
Max Waves: 3152 -> 3180 (0.89 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Samuel Pitoiset [Wed, 25 Mar 2020 17:17:38 +0000 (18:17 +0100)]
ac/nir: use llvm.amdgcn.rsq for nir_op_frsq
Instead of emitting 1.0 / sqrt(x) which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
pipeline-db (VEGA10/LLVM 9):
Totals from affected shaders:
SGPRS: 16872 -> 16864 (-0.05 %)
VGPRS: 15320 -> 15464 (0.94 %)
Spilled SGPRs: 2021 -> 2133 (5.54 %)
Code Size:
1915464 ->
1917476 (0.11 %) bytes
Max Waves: 641 -> 639 (-0.31 %)
pipeline-db (VEGA10/LLVM 10):
Totals from affected shaders:
SGPRS: 43936 -> 44120 (0.42 %)
VGPRS: 41776 -> 41972 (0.47 %)
Spilled SGPRs: 875 -> 875 (0.00 %)
Code Size:
4468164 ->
4468120 (-0.00 %) bytes
Max Waves: 2412 -> 2414 (0.08 %)
pipeline-db (VEGA10/LLVM 11 -
92744f62478):
Totals from affected shaders:
SGPRS: 60096 -> 60096 (0.00 %)
VGPRS: 63552 -> 63648 (0.15 %)
Spilled SGPRs: 6135 -> 6117 (-0.29 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size:
6252996 ->
6249772 (-0.05 %) bytes
Max Waves: 2324 -> 2337 (0.56 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
Samuel Pitoiset [Wed, 25 Mar 2020 17:17:06 +0000 (18:17 +0100)]
ac/nir: use llvm.amdgcn.rcp for nir_op_frcp
Instead of emitting 1.0 / x which includes a slow division that
LLVM doesn't always optimize even if the metadata is correctly set.
pipeline-db (VEG10/LLVM 9):
Totals from affected shaders:
SGPRS: 50384 -> 50312 (-0.14 %)
VGPRS: 42572 -> 42696 (0.29 %)
Spilled SGPRs: 1372 -> 1372 (0.00 %)
Code Size:
5692040 ->
5691428 (-0.01 %) bytes
Max Waves: 3954 -> 3951 (-0.08 %)
pipeline-db (VEG10/LLVM 10):
Totals from affected shaders:
SGPRS: 78512 -> 78464 (-0.06 %)
VGPRS: 62408 -> 62484 (0.12 %)
Spilled SGPRs: 1502 -> 1502 (0.00 %)
Code Size:
8106188 ->
8103372 (-0.03 %) bytes
Max Waves: 7759 -> 7753 (-0.08 %)
pipeline-db (VEGA10/LLVM 11 -
92744f62478):
Totals from affected shaders:
SGPRS: 112760 -> 113232 (0.42 %)
VGPRS: 111132 -> 110568 (-0.51 %)
Spilled SGPRs: 5870 -> 5940 (1.19 %)
Spilled VGPRs: 650 -> 652 (0.31 %)
Code Size:
11887232 ->
11561744 (-2.74 %) bytes
Max Waves: 8964 -> 9015 (0.57 %)
LLVM 11 (master) is more affected than previous versions, but
based on the small impact with LLVM 9/10, I decided to emit it
unconditionally.
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4326>
H.J. Lu [Tue, 18 Feb 2020 22:05:39 +0000 (14:05 -0800)]
x86: Add ENDBR at function entries
Intel Control-flow Enforcement Technology (CET):
https://software.intel.com/en-us/articles/intel-sdm
contains shadow stack (SHSTK) and indirect branch tracking (IBT).
When IBT is enabled, all indirect branch targets must start with
ENDBR instruction which is a NOP on non-CET processors.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2538
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3865>
Marek Olšák [Thu, 26 Mar 2020 04:30:53 +0000 (00:30 -0400)]
mesa: try to fix the android build
Fixes: 8a3e2cd9b26
Closes: #2685
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4325>
Francisco Jerez [Thu, 19 Mar 2020 20:08:56 +0000 (13:08 -0700)]
intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround.
This has been reported to fix a hang in Shadow of Mordor on Gen12.
One of its compute shaders seems to cause an in-order exec_all
dependency to be merged into an out-of-order SET dependency slot,
which would prevent us from baking the SET dependency into the parent
instruction, leading to an assert failure in emit_inst_dependencies()
(Thanks to Rafael for noticing that). Prevent that by avoiding
combination of in-order dependencies whenever that would cause a SET
dependency to be demoted to a SYNC.NOP instruction.
Fixes: e14529ff3262a527 "intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow."
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
H.J. Lu [Thu, 27 Feb 2020 17:18:37 +0000 (09:18 -0800)]
x86_init_func_common: Add ENDBR at function entry
Intel Control-flow Enforcement Technology (CET):
https://software.intel.com/en-us/articles/intel-sdm
when IBT is enabled, all indirect branch targets must start with ENDBR
instruction which is a NOP on non-CET processors.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2575
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben.widawsky@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3985>
Danylo Piliaiev [Thu, 26 Mar 2020 12:07:46 +0000 (14:07 +0200)]
intel/aub_viewer: Fix format specifier for uint64_t
Use PRIx64 instead of lx for uint64_t
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2692
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4331>
Icecream95 [Wed, 25 Mar 2020 08:05:16 +0000 (21:05 +1300)]
panfrost: Extend the tiled store fast-path to loads
The access functions are forced to be inline, so performance shouldn't
be impacted for stores.
WebGL performance in Firefox is more than doubled, and track loading
in STK is noticeably faster.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4317>
Icecream95 [Wed, 25 Mar 2020 07:01:08 +0000 (20:01 +1300)]
mesa/format_utils: Add a fast-path for RGBA to BGRA
This is similar to an existing fast-path, but this is for an array
source while the existing one is for an array destination.
Firefox can hit this case for WebGL when GL compositing is not used.
For a WebGL sample on the Panfrost driver, the frame-rate increased
from 19.4 fps to 20.6 fps, which is a 6% gain.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4315>
Tapani Pälli [Sat, 14 Mar 2020 06:57:02 +0000 (08:57 +0200)]
glsl: set error_emitted true if type not ok for assignment
Patch changes also existing assert to not trigger when we have
error types in assignment.
v2: simplify, cleanup (Ian)
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2629
Fixes: d1fa69ed61d ("glsl: do not attempt assignment if operand type not parsed correctly")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4178>
Alexandros Frantzis [Tue, 24 Mar 2020 14:34:05 +0000 (16:34 +0200)]
gitlab-ci: Fix traces caching in tracie
We are currently comparing a hex string representation of the git lfs
OID with a byte array representation of the locally calculated OID,
causing detection of valid cached traces to fail. Ensure we are
comparing compatible representations (in this case hex strings).
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4300>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4300>
Boris Brezillon [Tue, 17 Mar 2020 13:38:44 +0000 (13:38 +0000)]
vtn/opencl: add rint-support
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Wed, 25 Mar 2020 20:19:01 +0000 (21:19 +0100)]
vtn/opencl: add native exp2/log2-support
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Fri, 13 Mar 2020 11:36:19 +0000 (12:36 +0100)]
vtn/opencl: add native exp10/log10-support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Fri, 13 Mar 2020 10:57:52 +0000 (11:57 +0100)]
vtn/opencl: add native exp/log-support
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Thu, 12 Mar 2020 14:58:04 +0000 (15:58 +0100)]
compiler/nir: move build_log helper into builtin-builder
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Thu, 12 Mar 2020 14:00:37 +0000 (15:00 +0100)]
compiler/nir: move build_exp helper into builtin-builder
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Erik Faye-Lund [Tue, 10 Mar 2020 17:19:15 +0000 (18:19 +0100)]
vtn/opencl: fully enable OpenCLstd_Clz
Fixes: 7325f6ac987 ("vtn/opencl: add clz support")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4318>
Neil Armstrong [Wed, 25 Mar 2020 16:06:18 +0000 (17:06 +0100)]
gitlab-ci: re-enable mali400/450 and t820 jobs
The FILES_HOST_NAME and FILES_HOST_URL are in the baylibre's runner
environment to make it more flexible.
Also use the new aarch64 mesa-ci-aarch64-lava-baylibre runner with
embedded nginx server to serve the LAVA artifacts.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Neil Armstrong [Wed, 25 Mar 2020 16:05:46 +0000 (17:05 +0100)]
gitlab-ci: add FILES_HOST_URL and move FILES_HOST_NAME into jobs
The FILES_HOST_URL & FILES_HOST_NAME will be in the Baylibre's runner
environment, move them into the t860/t720/t760 jobs using Collabora's
runner.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Tomeu Vizoso [Tue, 24 Mar 2020 11:58:43 +0000 (12:58 +0100)]
gitlab-ci: Serve files for LAVA via separate service
Currently, we store the kernel and ramdisk for each LAVA job in the
artifacts of the job that built them. Because artifacts are stored in
GCE and LAVA labs aren't, this causes a lot of egress with is expensive.
To avoid this, have runners download most of the data via the (cached)
container images once, and for each job upload the kernel and ramdisk to
a server outside GCE.
Right now we only have Collabora's runner with a local web server, so
jobs that go to Baylibre's lab have been disabled.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Tomeu Vizoso [Tue, 24 Mar 2020 11:58:30 +0000 (12:58 +0100)]
gitlab-ci: Place files from the Mesa repo into the build tarball
There's some files from the .gitlab-ci directory that are needed in the
test stage and that, because the Mesa repository isn't checked out in
that stage, need to be made available through other means.
Because those files are going to be needed in LAVA devices, place them
ino the tarball containing the built files so it's available to both
gitlab-ci runners and LAVA devices.
Before those files were passed in the artifacts of the Gitlab CI job,
but this commit places them into the built tarball so scripts later in
the pipeline don't need to account for this discrepancy.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4295>
Marek Olšák [Mon, 23 Mar 2020 18:50:53 +0000 (14:50 -0400)]
radeonsi: enable full out-of-order drawing when allow_draw_out_of_order is set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
Marek Olšák [Thu, 30 Jan 2020 23:56:22 +0000 (18:56 -0500)]
mesa: allow out-of-order drawing to optimize immediate mode if it's safe
This increases performance by 11-13% in Viewperf11/Catia - first scene.
Set allow_draw_out_of_order=true to enable this.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4152>
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