radeonsi/gfx10: fix ds.ordered.add intrinsic for compute-based culling

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269>

diff --git a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
index ec95ec1214f0d25207b909f4990ab034ffa35494..7bd14446580e8ac03bf50cc6e5fb98942a1f6ad9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
+++ b/src/gallium/drivers/radeonsi/si_compute_prim_discard.c
@@ -240,6 +240,9 @@ si_build_ds_ordered_op(struct si_shader_context *ctx, const char *opcode,
                       LLVMValueRef m0, LLVMValueRef value, unsigned ordered_count_index,
                       bool release, bool done)
 {
+       if (ctx->screen->info.chip_class >= GFX10)
+               ordered_count_index |= 1 << 24; /* number of dwords == 1 */
+
        LLVMValueRef args[] = {
                LLVMBuildIntToPtr(ctx->ac.builder, m0,
                                  LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS), ""),