panfrost: Guard against reading past end of buffer

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: split asserts in pandecode

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

llvmpipe: fix undefined shift 1 << 31.

Pointed out by coverity.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

swrast: fix undefined shift of 1 << 31

Pointed out by coverity

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

draw: fix undefined shift of (1 << 31)

Pointed out by a coverity scan.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

iris: Actually pin the scratch BO.

We were pinning it for compute shaders, and pinning it when restoring
saved buffers, but we never actually pinned it in the original batch
for VS/TCS/TES/GS/FS.

Fixes rendering in GFXBench5's Tessellation demo and a bunch of Piglit
geometry shader tests.

anv: store heap address bounds when initializing physical device

We can then reuse those bounds to initialize the VMA heaps at logical
device creation.

This fixes an issue on EHL which has only 36bits of VMA. We were
incorrectly using the fixed 48bits upper bound to initialize the
logical device heap, resulting in addresses beyong the device's
limits.

v2: Don't confuse heap size (limited by system memory) and VMA size
   (limited by number of addressing bits the platform has)

v3: Fix low heap vma_size :( (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)

intel/common: Support bigger right-shifts with mi_builder

Because why not?

anv/cmd_buffer: Use gen_mi_sub instead of gen_mi_add with a negative

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Move mi_memcpy and mi_memset to gen_mi_builder

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for queries

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for conditional rendering

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for indirect dispatch

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for indirect draw parameters

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for computing resolve predicates

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for CmdDrawIndirectByteCount

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/common: Add unit tests for gen_mi_builder

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/common: Add a MI command builder

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

v3d: Add an optimization pass for redundant flags updates.

Our exec masking introduces lots of redundant flags updates, and even
without that there will be cases where NIR comparisons on the same sources
for different reasons may generate the same comparison instruction before
the selection.

total instructions in shared programs: 6492930 -> 6460934 (-0.49%)
total uniforms in shared programs: 2117460 -> 2115106 (-0.11%)
total spills in shared programs: 4983 -> 4987 (0.08%)
total fills in shared programs: 6408 -> 6416 (0.12%)

kmsro: Extend to include armada-drm

This allows using the Marvell Armada display controllers (with the
armada drm modesetting driver) along with the render-only drivers,
such as Etnaviv on an OLPC XO-1.75 laptop.

v2:
- Add to Android.mk too

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Eric Anholt <eric@anholt.net>

lima: implement blit with util_blitter

As we have already prepared for using util_blitter, use it to implement
lima_blit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

lima: make lima_context_framebuffer subtype of pipe_framebuffer_state

Currently the lima driver saves the framebuffer state in its
from-scratch struct lima_context_framebuffer. However, util_blitter
requires to save framebuffer with standard struct
pipe_framebuffer_state.

Make the lima_context_framebuffer a subtype of the standard
pipe_framebuffer_state, thus the standard part can be used for
util_blitter framebuffer state saving.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

lima: add dummy set_sample_mask function

The set_sample_mask function is required in util_blitter.

Add a dummy one to make util_blitter work.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

gitlab-ci: build gallium extra hud

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

meson: remove meson-created megadrivers symlinks

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110356
Fixes: aa7afe324c2092fb31f9 "meson: strip rpath from megadrivers"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir: initialise some variables in opt_if_loop_last_continue()

Fixes a couple of Coverity warnings CID 1444626.

Fixes: e30804c6024f ("nir/radv: remove restrictions on opt_if_loop_last_continue()")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nir/xfb: do not use bare interface type

In commit 3b3653c4cfb we decided not to use bare types; hence do not use
bare type when comparing with interface type to find out if the xfb
variable is an array block.

This fixes dEQP-VK.transform_feedback.* tests.

Fixes: 3b3653c4cfb ("nir/spirv: don't use bare types, remove assert in
                     split vars for testing")
CC: Dave Airlie <airlied@redhat.com>
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gitlab-ci: Run CI pipeline for all branches in the main repository

In turn, do not run the pipeline for the master branch in forked
repositories.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

virgl: use debug_printf instead of fprintf

While we're at it, prefix the string with "VIRGL: ", to match similar
code elsewhere in virgl.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

virgl: do not warn about display-target binding

We never want to display a transfer-temp surface, so let's ignore that
flag when calculating the new binding flags.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

virgl: only warn about unchecked flags

The other flags are already vetted, so there's no point in reporting
them.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

virgl: unsigned int -> unsigned

We don't usually spell out the int part of unsigned.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

egl: setup fds array correctly when exporting dmabuf

For formats with multiple planes, application will pass a num_planes
sized fds array which should be initialized properly in case fds amount
utilized by the driver is less than the number of planes.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

docs: update calendar, and news item and link release notes for 19.0.2

docs: Add sha256 sums for 19.0.2

docs: Add release notes for 19.0.2

gallium/aux: Report error if loading of a pipe driver fails.

Skip over non-existent files.
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

kmsro: Add platform support for exynos and sun4i

v2:
- add Android.mk change

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Qiang Yu <yuq825@gmail.com>

kmsro: Add lima renderonly support

Enable using lima for KMS renderonly. This still needs KMS driver
name mapping to kmsro to be used automatically.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Qiang Yu <yuq825@gmail.com>

gallium: add lima driver

v2:
- use renamed util_dynarray_grow_cap
- use DEBUG_GET_ONCE_FLAGS_OPTION for debug flags
- remove DRM_FORMAT_MOD_ARM_AGTB_MODE0 usage
- compute min/max index in driver

v3:
- fix plbu framebuffer state calculation
- fix color_16pc assemble
- use nir_lower_all_source_mods for lowering neg/abs/sat
- use float arrary for static GPU data
- add disassemble comment for static shader code
- use drm_find_modifier

v4:
- use lima_nir_lower_uniform_to_scalar

v5:
- remove nir_opt_global_to_local when rebase

Cc: Rob Clark <robdclark@gmail.com>
Cc: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Arno Messiaen <arnomessiaen@gmail.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: marmeladema <xademax@gmail.com>
Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rohan Garg <rohan@garg.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>

drm-uapi: add lima_drm.h

Acked-by: Eric Anholt <eric@anholt.net>
Signed-of-by: Qiang Yu <yuq825@gmail.com>

gallium/u_vbuf: export u_vbuf_get_minmax_index

This helper function can be used by driver which
always need min/max index.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Qiang Yu <yuq825@gmail.com>

u_dynarray: add util_dynarray_grow_cap

This is for the case that user only know a max size
it wants to append to the array and enlarge the array
capacity before writing into it.

v2:
- rename newsize to newcap
- rename util_dynarray_enlarge to util_dynarray_grow_cap

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

u_math: add ushort_to_float/float_to_ushort

v2:
- return 0 for NaN too

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: trace: Add missing fence related wrappers

Without that kmscube with GALLIUM_TRACE would segfault like:

  #0  0x0000000000000000 in  ()
  #1  0x0000ffff8f311760 in dri2_create_fence_fd (_ctx=0xaaaae266b8b0, fd=10) at ../src/gallium/state_trackers/dri/dri_helpers.c:122
  #2  0x0000ffff90788670 in dri2_create_sync (drv=0xaaaae2667910, disp=0xaaaae26691f0, type=12612, attrib_list=0xaaaae26b9290) at ../src/egl/drivers/dri2/egl_dri2.c:2993
  #3  0x0000ffff90776a9c in _eglCreateSync (disp=0xaaaae26691f0, type=12612, attrib_list=0xaaaae26b9290, orig_is_EGLAttrib=0, invalid_type_error=12292) at ../src/egl/main/eglapi.c:1823
  #4  0x0000ffff90776be4 in eglCreateSyncKHR (dpy=0xaaaae26691f0, type=12612, int_list=0xfffff662e828) at ../src/egl/main/eglapi.c:1848

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

intel/tools: Remove redundant definitions of INTEL_DEBUG

INTEL_DEBUG is declared extern and defined in gen_debug.c

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/common: move gen_debug to intel/dev

libintel_common depends on libintel_compiler, but it contains debug
functionality that is needed by libintel_compiler.  Break the circular
dependency by moving gen_debug files to libintel_dev.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: support INTEL_NO_HW environment variable

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Fix the description of Coffeelake pci-id 0x3E98

According to Intel website [1], the description of chipset 8086:3E98 is
Intel(R) UHD Graphics 630.  Besides, xserver also mentions it as
"Intel(R) UHD Graphics 630 (Coffeelake 3x8 GT2)" in commit d3a26bbf
(DRI2: Add another Coffeelake PCI ID) [2].

This patch modifies the description to sync with xserver.

[1]: https://ark.intel.com/content/www/us/en/ark/products/134896/intel-core-i5-9600k-processor-9m-cache-up-to-4-60-ghz.html
[2]: https://gitlab.freedesktop.org/xorg/xserver/commit/d3a26bbf618507e1ca05b2bc99a880075b77db77

Fixes: commit 44f1dcf9b3fd "i965: Add a new CFL PCI ID."
Signed-off-by: Jian-Hong Pan <jian-hong@endlessm.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Anuj Phogat anuj.phogat@gmail.com

Partially revert "gallium: fix autotools build of pipe_msm.la"

This partially reverts commit 356ec7a21960d77db282f67af577dcdb46966b5a.
There are symbols needed by libglsl missing, so we might as well skip
the entire library.

Fixes: 356ec7a21960d77db282f67af577dcdb46966b5a
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Acked-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Vinson Lee <vlee@freedesktop.org>

vc4: Upload CS/VS UBO uniforms together.

Same as I did for V3D, drop all this code trying to GC the
non-indirectly-loaded uniforms from the UBO that's used for indirect
access of gallium cb[0].  While it does successfully drop some of those,
it came at the cost of uploading the VS's indirect unifroms twice, for the
bin and render versions of the shader.

With the UBO loads simplified, I was also able to easily backport V3D's
change to pack a UBO offset into the uniform_data[] field so that we don't
need to do the add of the uniform base in the shader.

As a bonus, now vc4 doesn't depend on mesa/st type_size functions.

total uniforms in shared programs: 25514 -> 25490 (-0.09%)
total instructions in shared programs: 77019 -> 76836 (-0.24%)

vc4: Split UBO0 and UBO1 address uniform handling.

I'm going to extend how UBO0 works in a moment.

vc4: Don't forget to set the range when scalarizing our uniforms.

In the next commit, we'll want this for handling UBO access clamping.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st: Lower uniforms in st in the !PIPE_CAP_PACKED_UNIFORMS case as well.

PIPE_CAP_PACKED_UNIFORMS conflates several things: Lowering uniforms i/o
at the st level instead of the backend, packing uniforms with no padding
at all, and lowering to UBOs.

Requiring backends to lower uniforms i/o for !PIPE_CAP_PACKED_UNIFORMS
leads to the driver needing to either link against the type size function
in mesa/st, or duplicating it in the backend.  Given that all backends
want this lower-io as far as I can tell, just move it to mesa/st to
resolve the link issue and avoid the driver author needing to understand
st's uniforms layout.

Incidentally, fixes uniform layout failures in nouveau in:

dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment
dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex
dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_fragment
dEQP-GLES2.functional.shaders.struct.uniform.sampler_array_vertex

and I think in Lima as well.

v2: fix indents

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: don't use default pipeline cache for hits for VK_EXT_pipeline_creation_feedback

If the user didn't provide a pipeline cache and we're using the
default internal pipeline cache, then we shouldn't consider a cache
hit for VK_EXT_pipeline_creation_feedback as the application did not
provide a cache.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6601e5d6fc68cd ("anv: implement VK_EXT_pipeline_creation_feedback")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Revert "glsl: fix shader_storage_blocks_write_access for SSBO block arrays"

This reverts commit b7ca074cc0df6101c428b2dfa53a59a0c6620af2.

It broke a lot of tests.

glsl/standalone: add GLES3.1 and GLES3.2 compatibility

also set some constants for SSBOs.

With that it can compile the shader from:
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.18

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

virgl: use debug_printf instead of fprintf

While we're at it, prefix the string with "VIRGL: ", to match similar
code elsewhere in virgl.

Fixes: d7b31969767 ("virgl: Return an error if we use fp64 on top of GLES")
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>

virgl: Enable passing arrays as input to fragment shaders

This is needed to properly handle interpolateAt* when the input to be
interpolated is passed as array in the original GLSL.

Currently, the the GLSL compiler would lower selecting the correct input so
that the interpolant parameter to interpolateAt* is a temporary, and this
can not be used to create a valid shader on the host side, because here the
parameter must a shader input.

By allowing the passing the created TGSI allows to create proper GLSL.
This is related to the virglrenderer bug
  https://gitlab.freedesktop.org/virgl/virglrenderer/issues/74

v2: Squash the two patches handling these flags into another

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

Gallium: Add new CAP that indicated whether IO array definitions can be shriked

PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS is added to indicate whether the TGSI
pass to shrink IO arrays should be skipped to enforce the originally declared array
sizes and locations instead.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

wsi: allow to override the present mode with MESA_VK_WSI_PRESENT_MODE

This is common to all Vulkan drivers and all WSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: enable VK_AMD_gpu_shader_half_float

Should be safe to enable as all instructions seem to support 16-bit.
Unfortunately, there is no CTS test.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add 16-bit support to ac_build_ddxy()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: fix nir_op_b2f16

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

virgl: Set bind when creating temp resource.

virgl render complains about "Illegal resource" when running
dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_window,
the reason is that a zero bind value was given for temp resource.

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

radv: Add non-uniform indexing lowering.

This patch does it as late as possible so the potential extra
basic blocks don't inhibit other optimizations.

Big thanks to Jason for writing the lowering pass.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

nir: Add access qualifiers on load_ubo intrinsic.

Otherwise nir_lower_non_uniform_access crashes when it tries
to get the access of a load_ubo.

Fixes: 8ed583fe523 "spirv: Handle the NonUniformEXT decoration"
Fixes: e50ab2c0f23 "nir: Add access flags to deref and SSBO atomics"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

glsl: fix shader_storage_blocks_write_access for SSBO block arrays

CTS: GL45-CTS.compute_shader.resources-max

Fixes: 4e1e8f684bf "glsl: remember which SSBOs are not read-only and pass it to gallium"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

freedreno: PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT unreachable statement

There seems to be a duplicate return statement,
as A2XX doesn't support shader buffers.

Reviewed-by: Rob Clark <robdclark@gmail.com>

genxml: sort xml files using new script

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: add a sorting script

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

bin: drop unused import from install_megadrivers.py

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

anv: advertise 8 subtexel/mipmap precision bits

So far ANV was advertising 4 bits for both subTexelPrecisionBits and
mipmapPrecisionBits. But these values were not actually verified.

But it seems the right value is actually 8 bits for both cases.

Unfortunately Intel PRM does not clarify how many bits the hardware use.
For the mipmap case, there is the following reference in PRM Volume 6
(3D Media GPGPU), specifically in LOD Computation Pseudocode:

```
Bias: S4.8
MinLod: U4.8
MaxLod: U4.8
Base: U4.1
MIPCnt: U4
SurfMinLod: U4.8
ResMinLod: U4.8
``

We have other clues, though:

- On one side, dEQP-VK.texture.explicit_lod.* tests fail when using 4
bits, but work when using 8 bits. These tests try to mimic the expected
behaviour as much real as possible, and they use the reported
subTexelPrecisionBits and mipmapPrecisionBits reported to get this.

- On the other side, the equivalent driver for Windows is reporting 8
bits for both elements. Not sure if they got to verify it from the PRM
or from a diffent source.

CC: Jason Ekstrand <jason@jlekstrand.net>
CC: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

st/va: reverse qt matrix back to its original order

The quantiser matrix that VAAPI provides has been applied with inverse z-scan.
However, what we expect in MPEG2 picture description is the original order.
Therefore, we need to reverse it back to its original order.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110257
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

glsl/linker: location aliasing requires types to have the same width

From the OpenGL 4.60.5 spec, section 4.4.1 Input Layout Qualifiers,
Page 67, (Location aliasing):

  " Further, when location aliasing, the aliases sharing the location
    must have the same underlying numerical type and bit
    width (floating-point or integer, 32-bit versus 64-bit, etc.) and
    the same auxiliary storage and interpolation qualification."

Additionally, we have improved the linker error descriptions.
Specifically, when taking structs into account we were producing a
linker error because we assumed that all components in each location
were used and that would cause component aliasing. This is not
accurate of the actual problem. Now, the failure specifies that the
underlying numerical type incompatibility is the cause for the
failure.

Fixes the following piglit test:

tests/spec/arb_enhanced_layouts/linker/component-layout/vs-to-fs-width-mismatch-double-float.shader_test

v2:
  - Do not assert if we see invalid numerical types. These come
    straight from shader code, so we should produce linker errors if
    shaders attempt to do location aliasing on variables that are not
    numerical such as records.
  - While we are at it, improve error reporting for the case of
    numerical type mismatch to include the shader stage.

v3:
  - Allow location aliasing of images and samplers. If we get these
    it means bindless support is active and they should be handled
    as 64-bit integers (Ilia)
  - Make sure we produce link errors for any non-numerical type
    for which we attempt location aliasing, not just structs.

v4:
  - Rebased with minor fixes (Andres).
  - Added fixing tag to the commit log (Andres).

v5:
  - Remove the helper function and check individually for the
    underlying numerical type and bit width (Timothy).
  - Implicitly, assume that any non-treated type which is checked for
    its underlying numerical type is either integer or
    float and has a defined bit width (Timothy).
  - Implicitly, assume that structs are the only non-treated
    non-numerical type (Timothy).
  - Improve the linker error descriptions and commit log (Andres).

Fixes: 13652e7516a ("glsl/linker: Fix type checks for location aliasing")
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Cc: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

softpipe: Enable PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT

The offset alignment must be set to s16 because the tile cache is
implemented to require this.

This enables ARB_buffer_texture_range and OES_texture_buffer for
softpipe. The according deqp-gles31 tests pass.

Also update the feature table.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

softpipe: Add an extra code path for the buffer texel lookup

With buffers the addressing is done on a per-byte bases so the code
path for normal textures doesn't work properly. Also add an assert
to make sure that the bit cound for storing the X coordinate is
large enough.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

softpipe: raise number of bits used for X coordinate texture lookup

With buffers the addressing is done on a per byte basis and we with
a maximal block size of 16 byte we have to take into acount four more
bits. For simplicity just remove the TEX_TILE_SIZE_LOG2, which is 5 bit.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

softpipe: Don't use mag filter for gather op

For the gather op no magnifictaion filter is provided, so always use
the filter given for minification (which is the linear filter)

Fixes: 0dff1533f25951adda3c36be6d9efa944741befb
    softpipe: Use mag texture filter also for clamped lod == 0

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

nir: Get rid of global registers

We have a pass to lower global registers to locals and many drivers
dutifully call it.  However, no one ever creates a global register ever
so it's all dead code.  It's time we bury it.

Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Get rid of nir_register::is_packed

All we ever do is initialize it to zero, clone it, print it, and
validate it.  No one ever sets or uses it.

Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

virgl: add support for ARB_indirect_parameters

The protocol changes are already in place for it.

Reviewed-By: Gert Wollny <gert.wollny@collabora.com>

virgl: add support for ARB_multi_draw_indirect

This will pass the multi draw through to the host if it has
support for it instead of using the st to emulate it

Reviewed-By: Gert Wollny <gert.wollny@collabora.com>

virgl: add support for missing command buffer binding.

When I added indirect support I forgot this, however to use it
now we need to check for a new enough capability on the host side.

Reviewed-By: Gert Wollny <gert.wollny@collabora.com>

docs: Add NV_compute_shader_derivatives to 19.1.0 relnotes

anv: Implement VK_NV_compute_shader_derivatives

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

spirv: Add support for DerivativeGroup capabilities

As defined in SPV_NV_compute_shader_derivatives. These control how the
invocations are arranged in a CS when doing derivative and related
operations (which are also enabled by the extension).

Since we expect valid SPIR-V, we don't need to do more work at SPIR-V
level to enable the derivative and related operations to be called.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

iris: Enable NV_compute_shader_derivatives

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gallium: Add PIPE_CAP_COMPUTE_SHADER_DERIVATIVES

To enable NV_compute_shader_derivatives, which allows derivatives (and
texture lookups with implicit derivatives) in compute shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Advertise NV_compute_shader_derivatives

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

intel/fs: Use NIR_PASS_V when lowering CS intrinsics

This will make that step visible in NIR_PRINT=1.

v2: Also use the macro for the cleanup passes.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Don't loop when lowering CS intrinsics

This was needed when certain intrinsics were lowered to other ones
that were defined by the same pass.  After 060817b2 "intel,nir: Move
gl_LocalInvocationID lowering to nir_lower_system_values" we don't
need the loop anymore.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Add support for CS to group invocations in quads

When using quads, instead of mapping the elements to the next 4 local
invocation indices, we map the two next in the "current" row and two
next in the "next row".  A side effect is that a thread will execute
the indices in a different order.

We now perform the lowering of both local invocation ID and index
together -- and don't rely anymore on lowering done by
nir_lower_system_values.  That is convenient when doing the math for
quads, because we need X and Y to get the right invocation index.

When the pass progresses, fold the constants and clean up to reduce
the noise from the indexing math.

This implements the derivative_group_quadsNV semantics from
NV_compute_shader_derivatives.

v2: Take subgroup_id into account, otherwise only values in the first
    subgroup would be used. (Jason)

v3: Calculate invocation index and ID together, to avoid duplicating
    some math in the quads case when both index and ID are used. (Jason)

v4: Don't call cleanup passes as part of the lowering, let that to the
    call site. (Jason)
    Change calculation to use less instructions. (Jason)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v3)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Use TEX_LOGICAL whenever implicit lod is supported

Make sure we include compute shaders that have a derivative group
defined.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Don't set LOD=0 for compute shader that has derivative group

When using NV_compute_shader_derivatives to set a derivative group,
a compute shader supports texture with implicit LOD calculation, so
don't set an explicit LOD.

Note if the extension is used but the derivative group is not
specified, it will default to LOD=0 as before.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/algebraic: Lower CS derivatives to zero when no group defined

In compute shaders if no derivative group is defined, the derivatives
will always be zero.  Specified in NV_compute_shader_derivatives.

To make the check more convenient, add a "info" local variable to the
generated code so we can refer to it in the Python rules.  (Jason)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: Parse and propagate derivative_group to shader_info

NV_compute_shader_derivatives allow selecting between two possible
arrangements (quads and linear) when calculating derivatives and
certain subgroup operations in case of Vulkan.  So parse and propagate
those up to shader_info.h.

v2: Do not fail when ARB_compute_variable_group_size is being used,
    since we are still clarifying what is the right thing to do here.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Enable texture builtins for NV_compute_shader_derivatives

Renamed a few predicates from "fs_only" to be "derivative_only" (or
similar pairs).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Enable derivative builtins for NV_compute_shader_derivatives

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Remove redundant conditions when asserting in_qualifier

As the code evolved, we ended up with a redundant conditions.  Clean
this up.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>