mesa.git
8 years agost/nine: Implement D3DRS_SPECULARENABLE
Patrick Rudolph [Tue, 22 Sep 2015 10:57:37 +0000 (12:57 +0200)]
st/nine: Implement D3DRS_SPECULARENABLE

Implement fixed function D3DRS_SPECULARENABLE.
Fixes failing WINE tests in test_specular_lighting() (visual.c)

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
8 years agost/nine: Fix D3DRS_LOCALVIEWER being ignored
Patrick Rudolph [Tue, 22 Sep 2015 15:29:42 +0000 (17:29 +0200)]
st/nine: Fix D3DRS_LOCALVIEWER being ignored

Set key->localviewer to D3DRS_LOCALVIEWER.

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
8 years agost/nine: Fix rounding issue with vs1.1 a0 reg
Axel Davy [Wed, 11 Nov 2015 09:15:19 +0000 (10:15 +0100)]
st/nine: Fix rounding issue with vs1.1 a0 reg

vs1.1 rounds a0 to lowest integer, while
other versions do round to closest.

To use the same path as the other versions (with ARR),
we were substracting 0.5 for vs1.1 to get round to lowest.

This gives wrong result if a0 is set to 0:
round(0 - 0.5) = -1

Instead just use ARL for vs1.1

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
8 years agost/nine: Fix D3DPMISCCAPS_FOGANDSPECULARALPHA support
Axel Davy [Sat, 17 Oct 2015 11:54:18 +0000 (13:54 +0200)]
st/nine: Fix D3DPMISCCAPS_FOGANDSPECULARALPHA support

The documentation of the flag doesn't make sense.
To sum up the doc, if not set, specular alpha contains fog,
and if set specular alpha contains 0 (except for ff).

However in practice when the flag is there, apps do use specular alpha
as if it could be used normally, which makes much more sense than the doc.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
8 years agost/nine: Fix AlphaCmpCaps
Patrick Rudolph [Thu, 24 Dec 2015 10:32:37 +0000 (11:32 +0100)]
st/nine: Fix AlphaCmpCaps

AlphaCmpCaps should advertise D3DPCMPCAPS_NEVER as well.

Fixes https://github.com/iXit/Mesa-3D/issues/142

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
8 years agoradeonsi: implement PK2H and UP2H opcodes
Marek Olšák [Fri, 29 Jan 2016 23:30:02 +0000 (00:30 +0100)]
radeonsi: implement PK2H and UP2H opcodes

Based on a gallivm patch by Ilia Mirkin.

+8 piglit regressions due to precision issues (I blame the tests)

The benefit is that we'll get v_cvt_f32_f16 and v_cvt_f16_f32 instead
of emulation with integer instructions. They are GLSL 4.00 intrinsics.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agoglsl: Ensure glsl/ exists before making the lexer/parser.
Matt Turner [Wed, 3 Feb 2016 20:03:13 +0000 (12:03 -0800)]
glsl: Ensure glsl/ exists before making the lexer/parser.

Reported-by: Jan Ziak <0xe2.0x9a.0x9b@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93989

8 years agoi965/fs: Allocate single register at a time for constants.
Matt Turner [Mon, 1 Feb 2016 19:14:01 +0000 (11:14 -0800)]
i965/fs: Allocate single register at a time for constants.

No instruction counts changed, but:

  total cycles in shared programs: 64834502 -> 64781530 (-0.08%)
  cycles in affected programs: 16331544 -> 16278572 (-0.32%)
  helped: 4757
  HURT: 4288

  GAINED: 66
  LOST:   20

I remember trying this when I first wrote the pass, but it wasn't
helpful at the time.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoradeonsi: fix Hyper-Z on Stoney
Marek Olšák [Thu, 28 Jan 2016 00:35:52 +0000 (01:35 +0100)]
radeonsi: fix Hyper-Z on Stoney

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agomesa: Use SSE prefetch instructions rather than 3DNow instructions
Patrick Baggett [Wed, 3 Feb 2016 21:05:54 +0000 (08:05 +1100)]
mesa: Use SSE prefetch instructions rather than 3DNow instructions

64-bit Pentium 4 CPUs don't have the 3DNow prefetch instructions
which results in an Illegal instruction crash.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Timothy Arceri <t_arceri@yahoo.com.au>
https://bugs.freedesktop.org/show_bug.cgi?id=27512

8 years agonv50/ir: make sure to fetch all sources before creating instruction
Ilia Mirkin [Wed, 3 Feb 2016 23:16:04 +0000 (18:16 -0500)]
nv50/ir: make sure to fetch all sources before creating instruction

We must fetch all sources into the instruction stream before generating
the instruction that uses them. Otherwise we'll define values after
using them, which won't work so well.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agonv50: avoid freeing the symbols if they're about to be stored
Ilia Mirkin [Wed, 3 Feb 2016 18:52:26 +0000 (13:52 -0500)]
nv50: avoid freeing the symbols if they're about to be stored

Spotted by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agost/mesa: fix potential null deref if no shader is passed in
Ilia Mirkin [Wed, 3 Feb 2016 18:51:19 +0000 (13:51 -0500)]
st/mesa: fix potential null deref if no shader is passed in

Spotted by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agoglx: update to updated version of EXT_create_context_es2_profile
Ilia Mirkin [Tue, 19 Jan 2016 15:07:04 +0000 (10:07 -0500)]
glx: update to updated version of EXT_create_context_es2_profile

The EXT spec has been updated to:
 - logically combine the es2_profile and es_profile exts
 - allow any legal version to be requested

dEQP tests request a specific ES version when using GLX, so this allows
dEQP upstream to run against GLX with the appropriate X server patch
(which had similar disabling logic).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
Reviewed-by: Adam Jackson <ajax@redhat.com> (v3)
v1 -> v2:
 - distinguish between DRI_API_GLES{,2,3}
 - add GLX_EXT_create_context_es_profile client-side support
v2 -> v3:
 - fix error in computing mask

8 years agodir-locals.el: set case-label offset to 0
Ilia Mirkin [Wed, 3 Feb 2016 18:07:58 +0000 (13:07 -0500)]
dir-locals.el: set case-label offset to 0

While this is the default, private .emacs files might have it set to
something else. No harm in forcing it to 0.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoappveyor: Bump shallow clone depth.
Jose Fonseca [Sun, 24 Jan 2016 18:33:58 +0000 (18:33 +0000)]
appveyor: Bump shallow clone depth.

To prevent build failures when a large patch series is committed, like
happened in https://ci.appveyor.com/project/jrfonseca-fdo/mesa/build/322
due to 10 commits between dac2964f3ebd96d5ac227984ab0cd79c2c3b2a1a and
6f428328d34bed16edb8709e4a117eb710d7893d where submitted before the
build slave started the git clone.

100 commits should be bigger than any patch series seen in practice, and
it takes practically the same time to download as 5 commits.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agoRevert "compiler: removed unused Makefile.sources"
Rob Clark [Wed, 3 Feb 2016 19:35:10 +0000 (14:35 -0500)]
Revert "compiler: removed unused Makefile.sources"

Whoops, didn't mean to push this one.

This reverts commit 78f4c555b93eb0951dcd9c5812109d506dd03023.

8 years agocompiler: fix .gitignore for glsl_compiler
Rob Clark [Wed, 3 Feb 2016 18:32:46 +0000 (13:32 -0500)]
compiler: fix .gitignore for glsl_compiler

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agocompiler: removed unused Makefile.sources
Rob Clark [Sat, 30 Jan 2016 20:04:19 +0000 (15:04 -0500)]
compiler: removed unused Makefile.sources

We seem to end up w/ duplication between compiler/Makefile.sources and
compiler/glsl/Makefile.sources.  The latter appears unused.  Delete it.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agogallium: fix the documentation of PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
Nicolai Hähnle [Tue, 26 Jan 2016 16:03:11 +0000 (11:03 -0500)]
gallium: fix the documentation of PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE

This parameter is equivalent to the corresponding OpenGL implementation
limit which is in texels, not bytes.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: support PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
Nicolai Hähnle [Tue, 26 Jan 2016 15:29:50 +0000 (10:29 -0500)]
gallium/radeon: support PIPE_CAP_SURFACE_REINTERPRET_BLOCKS

This is already used internally in si_resource_copy_region for compressed
textures, so the only real change here is the adjusted surface size
computation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: implement PBO upload for glCompressedTex(Sub)Image
Nicolai Hähnle [Sat, 16 Jan 2016 01:09:40 +0000 (20:09 -0500)]
st/mesa: implement PBO upload for glCompressedTex(Sub)Image

v2:
- use st->pbo_upload.enabled flag

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: redirect CompressedTexSubImage to our own implementation
Nicolai Hähnle [Fri, 15 Jan 2016 23:24:10 +0000 (18:24 -0500)]
st/mesa: redirect CompressedTexSubImage to our own implementation

This is where PBO upload will go.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: inline the implementation of _mesa_store_compressed_teximage
Nicolai Hähnle [Fri, 15 Jan 2016 23:17:17 +0000 (18:17 -0500)]
st/mesa: inline the implementation of _mesa_store_compressed_teximage

We will write our own version of texsubimage for PBO uploads, and we will
want to call that here as well.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: implement PBO upload for multiple layers
Nicolai Hähnle [Thu, 21 Jan 2016 17:54:54 +0000 (12:54 -0500)]
st/mesa: implement PBO upload for multiple layers

Use instancing to generate two triangles for each destination layer and use
a geometry shader to route the layer index.

v2:
- directly write layer in VS if supported by the driver (Marek Olšák)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: Accelerate PBO uploads
Fredrik Höglund [Fri, 8 Jan 2016 21:31:14 +0000 (16:31 -0500)]
st/mesa: Accelerate PBO uploads

Create a PIPE_BUFFER sampler view on the pixel-unpack buffer, and draw
the image on the texture with a fragment shader that maps fragment
coordinates to buffer coordinates.

Modifications by Nicolai Hähnle:
- various cleanups and fixes (e.g. error handling, corner cases)
- split try_pbo_upload into two functions, which will allow code to be
  shared with compressed texture uploads
- modify the source format selection to only test for support against
  the PIPE_BUFFER target

v2:
- update handling of TGSI_SEMANTIC_POSITION for recent changes in master
- MaxTextureBufferSize is number of texels, not bytes (Ilia Mirkin)
- only enable when integers are supported (Marek Olšák)
- try harder to hit the TextureBufferOffsetAlignment
- remove unnecessary MOV from the fragment shader

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agost/mesa: use the correct address generation functions in st_TexSubImage blit
Nicolai Hähnle [Sat, 16 Jan 2016 20:15:13 +0000 (15:15 -0500)]
st/mesa: use the correct address generation functions in st_TexSubImage blit

We need to tell the address generation functions about the dimensionality of
the texture to correctly implement the part of Section 3.8.1 (Texture Image
Specification) of the OpenGL 2.1 specification which says:

    "For the purposes of decoding the texture image, TexImage2D is
    equivalent to calling TexImage3D with corresponding arguments
    and depth of 1, except that
      ...
      * UNPACK SKIP IMAGES is ignored."

Fixes a low impact bug that was found by chance while browsing the spec and
extending piglit tests.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agogallium: Add PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
Nicolai Hähnle [Tue, 26 Jan 2016 15:27:58 +0000 (10:27 -0500)]
gallium: Add PIPE_CAP_SURFACE_REINTERPRET_BLOCKS

This cap indicates whether pipe->create_surface can reinterpret a texture
as a surface with a format of different block width/height (but equal
block size).

v2: fix whitespace

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agogallium: Add PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
Nicolai Hähnle [Tue, 26 Jan 2016 15:26:30 +0000 (10:26 -0500)]
gallium: Add PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY

This cap indicates that the driver only supports R, RG, RGB and RGBA
formats for PIPE_BUFFER sampler views.

v2: move into "unsupported features" section for nouveau (Ilia Mirkin)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agomesa: add MESA_NO_MINMAX_CACHE environment variable
Nicolai Hähnle [Mon, 11 Jan 2016 20:56:22 +0000 (15:56 -0500)]
mesa: add MESA_NO_MINMAX_CACHE environment variable

When set to a truish value, this globally disables the minmax cache for all
buffer objects.

No #ifdef DEBUG guards because this option can be interesting for
benchmarking.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agovbo: disable the minmax cache when the hit rate is low
Nicolai Hähnle [Mon, 11 Jan 2016 20:07:48 +0000 (15:07 -0500)]
vbo: disable the minmax cache when the hit rate is low

When applications stream their index buffers, the caches for those BOs become
useless and add overhead, so we want to disable them. The tricky part is
coming up with the right heuristic for *when* to disable them.

The first question is which hit rate to aim for. Since I'm not aware of any
interesting borderline applications that do something like "draw two or three
times for each upload", I just kept it simple.

The second question is how soon we should give up on the caching. Applications
might have a warm-up phase where they fill a buffer gradually but then keep
reusing it. For this reason, I count the number of indices that hit and miss
(instead of the number of calls that hit or miss), since comparing that to
the size of the buffer makes sense.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa: add USAGE_DISABLE_MINMAX_CACHE flag to buffer UsageHistory
Nicolai Hähnle [Mon, 11 Jan 2016 20:46:39 +0000 (15:46 -0500)]
mesa: add USAGE_DISABLE_MINMAX_CACHE flag to buffer UsageHistory

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agovbo: cache/memoize the result of vbo_get_minmax_indices (v3)
Nicolai Hähnle [Mon, 11 Jan 2016 19:54:53 +0000 (14:54 -0500)]
vbo: cache/memoize the result of vbo_get_minmax_indices (v3)

Some games developers are unaware that an index buffer in a VBO still needs
to be read by the CPU if some varying data comes from a user pointer (unless
glDrawRangeElements and friends are used). This is particularly bad when
they tell us that the index buffer should live in VRAM.

This cache helps, e.g. lifting This War Of Mine (a particularly bad
offender) from under 10fps to slightly over 20fps on a Carrizo.

Note that there is nothing prohibiting a user from rendering from multiple
threads simultaneously with the same index buffer, hence the locking. (The
internal buffer map taken for the buffer still leads to a race, but at least
the locks are a move in the right direction.)

v2: disable the cache on USAGE_TEXTURE_BUFFER as well (Chris Forbes)

v3:
- use bool instead of GLboolean for MinMaxCacheDirty (Ian Romanick)
- replace the sticky USAGE_PERSISTENT_WRITE_MAP bit by a direct
  AccessFlags check

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agovbo: move vbo_get_minmax_indices into its own source file
Nicolai Hähnle [Wed, 6 Jan 2016 19:06:32 +0000 (14:06 -0500)]
vbo: move vbo_get_minmax_indices into its own source file

We will add more code for caching/memoization. Moving the existing code
into its own file helps keep things modular.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa/main: bail earlier for size == 0 in _mesa_clear_buffer_sub_data
Nicolai Hähnle [Wed, 6 Jan 2016 22:57:49 +0000 (17:57 -0500)]
mesa/main: bail earlier for size == 0 in _mesa_clear_buffer_sub_data

Note that the conversion of the clear data (when data != NULL) can fail due
to an out of memory condition, but it does not check any error conditions
mandated by the spec. Therefore, it is safe to skip when size == 0.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa/main: add USAGE_PIXEL_PACK_BUFFER flag to buffer UsageHistory
Nicolai Hähnle [Thu, 7 Jan 2016 19:48:27 +0000 (14:48 -0500)]
mesa/main: add USAGE_PIXEL_PACK_BUFFER flag to buffer UsageHistory

We will want to disable minmax index caching for buffers that are used in this
way.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory
Nicolai Hähnle [Wed, 6 Jan 2016 22:38:19 +0000 (17:38 -0500)]
mesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory

We will want to disable minmax index caching for buffers that are used in this
way.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoutil/hash_table: add _mesa_hash_table_num_entries
Nicolai Hähnle [Mon, 11 Jan 2016 20:07:27 +0000 (15:07 -0500)]
util/hash_table: add _mesa_hash_table_num_entries

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoutil/hash_table: add _mesa_hash_table_clear (v4)
Nicolai Hähnle [Wed, 6 Jan 2016 19:50:46 +0000 (14:50 -0500)]
util/hash_table: add _mesa_hash_table_clear (v4)

v4: coding style change (Matt Turner)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v3)
8 years agost/omx/dec/h264: fix corruption when scaling matrix present flag set
Leo Liu [Mon, 1 Feb 2016 18:32:31 +0000 (13:32 -0500)]
st/omx/dec/h264: fix corruption when scaling matrix present flag set

The scaling list should be filled out with zig zag scan

v2: integrate zig zag scan for list 4x4 to vl(Christian)
v3: move list determination out from the loop(Ilia)

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agovl: add zig zag scan for list 4x4
Leo Liu [Mon, 1 Feb 2016 17:04:34 +0000 (12:04 -0500)]
vl: add zig zag scan for list 4x4

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
8 years agollvmpipe: use scissor_planes_needed helper function
Roland Scheidegger [Tue, 2 Feb 2016 23:36:15 +0000 (00:36 +0100)]
llvmpipe: use scissor_planes_needed helper function

So it doesn't get out of sync in multiple places.

8 years agoi965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONE
Jordan Justen [Tue, 8 Jul 2014 18:17:57 +0000 (18:17 +0000)]
i965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONE

GEN8_SURFACE_AUX_MODE_NONE is 0, so this is a no-op.

Yet, this also makes it clear that we can compare aux_mode to the
other GEN8_SURFACE_AUX_MODE_ values. We will want to compare to
GEN8_SURFACE_AUX_MODE_HIZ.

v2: Some very minor cherry-pick conflicts due to moving it around in the series.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
8 years agomesa: use default geometry's samples when there are no attachments
Ilia Mirkin [Sun, 31 Jan 2016 06:09:40 +0000 (01:09 -0500)]
mesa: use default geometry's samples when there are no attachments

Whether multisampling is turned on depends, in part, on whether
attachments are themselves multisample surfaces. However when there are
no attachments, we should rely on the default geometry for this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa: invalidate framebuffer when changing parameters
Ilia Mirkin [Sat, 23 Jan 2016 14:27:22 +0000 (09:27 -0500)]
mesa: invalidate framebuffer when changing parameters

This fixes dEQP-GLES31.functional.fbo.completeness.no_attachments

When the width or height are 0, the framebuffer is incomplete. We may
also not have been passing the new state down to the driver when the
widths/heights/etc changed. Make sure to dirty the state so that the
framebuffer state is revalidated at draw time.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agomesa: use geometric helper for computing min samples
Ilia Mirkin [Sun, 31 Jan 2016 05:44:14 +0000 (00:44 -0500)]
mesa: use geometric helper for computing min samples

In case we have a draw buffer without attachments, we should be looking
at the default number of samples.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agomesa: the _mesa_geometric_* functions require full types from mtypes.h
Ilia Mirkin [Sat, 23 Jan 2016 13:25:35 +0000 (08:25 -0500)]
mesa: the _mesa_geometric_* functions require full types from mtypes.h

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agowinsys/radeon: Do not deinit the pb cache if it was not initialized
Niels Ole Salscheider [Fri, 29 Jan 2016 21:48:57 +0000 (22:48 +0100)]
winsys/radeon: Do not deinit the pb cache if it was not initialized

This fixes a crash in pb_cache_release_all_buffers.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agotgsi/scan: add tgsi_shader_info::reads_samplemask
Marek Olšák [Fri, 8 Jan 2016 23:47:39 +0000 (00:47 +0100)]
tgsi/scan: add tgsi_shader_info::reads_samplemask

8 years agoradeonsi: rework RB+ for Stoney
Marek Olšák [Sun, 17 Jan 2016 20:13:16 +0000 (21:13 +0100)]
radeonsi: rework RB+ for Stoney

This fixes it.

States which also need to be taken into account:
- SPI color formats - each down-conversion format supports only a limited set
  of SPI formats
- whether MSAA resolving and logic op are enabled

These need special handling:
- blending
- disabled channels

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: rename cb_target_mask state to cb_render_state
Marek Olšák [Wed, 23 Dec 2015 14:51:25 +0000 (15:51 +0100)]
radeonsi: rename cb_target_mask state to cb_render_state

and rename a variable in the function.

SX_PS_DOWNCONVERT will be emitted here.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: treat intensity render targets exactly like red
Marek Olšák [Thu, 28 Jan 2016 00:35:19 +0000 (01:35 +0100)]
radeonsi: treat intensity render targets exactly like red

The motivation is to simplify the Stoney RB+ code.
Intensity is already treated as red except here.

No piglit regressions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agotgsi: set correct src type for UP2H
Marek Olšák [Fri, 29 Jan 2016 23:38:53 +0000 (00:38 +0100)]
tgsi: set correct src type for UP2H

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agoutil/hash_table: don't compare deleted entries
Connor Abbott [Sun, 15 Nov 2015 01:24:31 +0000 (20:24 -0500)]
util/hash_table: don't compare deleted entries

The equivalent of the last patch for the hash table. I'm not aware of
any issues this fixes.

v2:
- use entry_is_deleted (Timothy)

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
8 years agoutil/set: don't compare against deleted entries
Connor Abbott [Sun, 15 Nov 2015 01:20:42 +0000 (20:20 -0500)]
util/set: don't compare against deleted entries

When we delete entries in the hash set, we mark them "deleted" by
setting their key to the deleted_key, which points to a dummy
deleted_key_value. When searching for an entry, we normally skip over
those, but set_add() had some code for searching for duplicate entries
which forgot to skip over deleted entries. This led to a segfault inside
the NIR vectorization pass, since its key comparison function
interpreted the memory where deleted_key_value resides as a pointer and
tried to dereference it.

v2:
- add better commit message (Timothy)
- use entry_is_deleted (Timothy)

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
8 years agoglsl: Disable tree grafting optimization for shared variables
Jordan Justen [Wed, 20 Jan 2016 07:27:22 +0000 (23:27 -0800)]
glsl: Disable tree grafting optimization for shared variables

Fixes:
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_groups
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_invocation
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_group
 * dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_invocation

From https://android.googlesource.com/platform/external/deqp

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoglsl: Enable debug prints for do_common_optimization
Jordan Justen [Wed, 20 Jan 2016 07:23:23 +0000 (23:23 -0800)]
glsl: Enable debug prints for do_common_optimization

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoRevert "i965: Provide sse2 version for rgba8 <-> bgra8 swizzle"
Roland Scheidegger [Tue, 2 Feb 2016 14:45:59 +0000 (15:45 +0100)]
Revert "i965: Provide sse2 version for rgba8 <-> bgra8 swizzle"

This reverts commit ab30426e335116e29473faaafe8b57ec760516ee.

Apparently the memory isn't quite as aligned when this gets called
as it should be, causing crashes. (Albeit this looks independent
from this code, should crash just as well if ssse3 is enabled when
compiling without this patch.)
https://bugs.freedesktop.org/show_bug.cgi?id=93962

8 years agovirgl: mark function as static
Dave Airlie [Tue, 2 Feb 2016 07:54:43 +0000 (17:54 +1000)]
virgl: mark function as static

This is fallout from the previous changes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93961

Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agogallivm: add PK2H/UP2H support
Roland Scheidegger [Tue, 2 Feb 2016 02:51:22 +0000 (03:51 +0100)]
gallivm: add PK2H/UP2H support

Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due to those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agogallivm: add PK2H/UP2H support
Roland Scheidegger [Fri, 29 Jan 2016 01:49:22 +0000 (02:49 +0100)]
gallivm: add PK2H/UP2H support

Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).

8 years agotgsi: add PK2H/UP2H support
Roland Scheidegger [Tue, 2 Feb 2016 02:36:19 +0000 (03:36 +0100)]
tgsi: add PK2H/UP2H support

The util functions handle the half-float conversion.
Note that piglit won't like it much due to:
a) The util functions use magic float mul conversion but when run inside
softpipe/llvmpipe, denorms are flushed to zero, therefore when the conversion
is from/to f16 denorm the result will be zero. This is a bug which should be
fixed in these functions (should not rely on denorms being available), but
will happen elsewhere just the same (e.g. conversion to f16 render targets).
b) The util functions use trunc round mode rather than round-to-nearest. This
is NOT a bug (as it is a d3d10 requirement). This will result of rounding not
representable finite values to MAX_F16 rather than INFINITY. My belief is the
piglit tests are wrong here but it's difficult to tell (generally glsl
rounding mode is undefined, however I'm not sure if rounding mode might need
to be consistent for different operations). Nevertheless, for gl it would be
better to use round-to-nearest, but using different rounding for GL and d3d10
is an unsolved problem (as it affects things like conversion to f16 render
targets, clear colors, this shader opcode).

Hence for now don't enable the cap bit (so the code is unused).
(Code is from imirkin, comment from sroland)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmvware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agollvmpipe: drop scissor planes early if the tri is fully inside them
Roland Scheidegger [Tue, 2 Feb 2016 02:14:12 +0000 (03:14 +0100)]
llvmpipe: drop scissor planes early if the tri is fully inside them

If the tri is fully inside a scissor edge (or rather, we just use the
bounding box of the tri for the comparison), then we can drop these
additional scissor "planes" early. We do not even need to allocate
space for them in the tri.

The math actually appears to be slightly iffy due to bounding boxes
being rounded, but it doesn't matter in the end.

Those scissor rects are costly - the 4 planes from the scissor are
already more expensive to calculate than the 3 planes from the tri itself,
and it also prevents us from using the specialized raster code for small
tris.

This helps openarena performance by about 8% or so. Of course, it helps
there that while openarena often enables scissoring (and even moves the
scissor rect around) I have not seen a single tri actually hit the
scissor rect, ever.

v2: drop individual scissor edges, and do it earlier, not even allocating
space for them.
v3: help the compiler a bit with simpler code, suggested by Brian.

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agollvmpipe: minor cleanup of sse2 for calc_fixed_position
Roland Scheidegger [Sun, 31 Jan 2016 00:27:09 +0000 (01:27 +0100)]
llvmpipe: minor cleanup of sse2 for calc_fixed_position

Just slightly simpler assembly.

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agollvmpipe: use vector loads for (optimized) tri raster funcs
Roland Scheidegger [Sun, 31 Jan 2016 00:26:59 +0000 (01:26 +0100)]
llvmpipe: use vector loads for (optimized) tri raster funcs

When we switched to 64bit rasterization, we could no longer use straight
aligned loads for loading the plane data. However, what the code actually
does for loading 3 planes, is 12 scalar loads + 9 unpacks, and then there's
another 8 unpacks for the transpose we need (!).

It would be possible to do the (scalar) loads of course already transposed
(at least saving the additional unpacks), however instead just use
(un)aligned vector loads, and recalculate the eo values, which is much less
instructions (note in case of the triangle_32_3_4 case, the eo values are
not even used, making the scalar loads + unpacks for them all the more
pointless).

This drops execution time of the triangle_32_3_4 function considerably,
albeit it doesn't really make a measurable difference (for small tris we're
essentially limited by vertex throughput in any case), for triangle_32_3_16
it's essentially noise (the loop is more costly than the initial code there).

(I'm thinking about just ditching storing the eo values in the plane data,
so could switch back to using aligned planes, however right now they are
still used in the other raster functions dealing with planes with scalar
code. Also not touching the ppc code, might not be that bad there in any
case.)

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agoi965: Provide sse2 version for rgba8 <-> bgra8 swizzle
Roland Scheidegger [Fri, 29 Jan 2016 02:18:36 +0000 (03:18 +0100)]
i965: Provide sse2 version for rgba8 <-> bgra8 swizzle

The existing code used ssse3, and because it isn't compiled in a separate
file compiled with that, it is usually not used (that, of course, could
be fixed...), whereas sse2 is always present at least with 64bit builds.
This should be pretty much as fast as the pshufb version, albeit those
code paths aren't really used on chips without llc in any case.

v2: fix andnot argument order, add comments
v3: use pshuflw/hw instead of shifts (suggested by Matt Turner), cut comments

Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agomesa: fix typo in python scripts
Roland Scheidegger [Fri, 29 Jan 2016 01:58:29 +0000 (02:58 +0100)]
mesa: fix typo in python scripts

Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agovirgl: also build vtest for Android
Rob Herring [Fri, 29 Jan 2016 18:52:28 +0000 (12:52 -0600)]
virgl: also build vtest for Android

Enabling swrast on Android causes a link error because vtest is missing.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agovirgl: fix reference counting of prime handles
Rob Herring [Fri, 29 Jan 2016 22:36:29 +0000 (16:36 -0600)]
virgl: fix reference counting of prime handles

The virgl reference counting of buffers is broken for prime fd buffers.
Each prime fd passed into virgl_drm_winsys_resource_create_handle creates
a new resource. The solution requires creating a separate hash table to
track flink names separately from prime handles.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agovirgl: reuse screen when fd is already open
Rob Herring [Fri, 29 Jan 2016 22:36:28 +0000 (16:36 -0600)]
virgl: reuse screen when fd is already open

It is necessary to share the screen between mesa and gralloc to
properly ref count resources. This implements a hash lookup on
the file description to re-use an already created screen. This is
a similar implementation as freedreno and radeon.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agonouveau/video: wrap assertion within #ifndef NDEBUG
Mauro Rossi [Mon, 1 Feb 2016 22:37:42 +0000 (23:37 +0100)]
nouveau/video: wrap assertion within #ifndef NDEBUG

The change is necessary to avoid the following building error in android:

external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next':
external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function)
       assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]);
              ^
This matches the declaration of the variables in question.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agost/mesa: treat a write as a read for range purposes
Ilia Mirkin [Fri, 29 Jan 2016 19:45:38 +0000 (14:45 -0500)]
st/mesa: treat a write as a read for range purposes

We use this logic to detect live ranges and then do plain renaming
across the whole codebase. As such, to prevent WaW hazards, we have to
treat a write as if it were also a read.

For example, the following sequence was observed before this patch:

 13: UIF TEMP[6].xxxx :0
 14:   ADD TEMP[6].x, CONST[6].xxxx, -IN[3].yyyy
 15:   RCP TEMP[7].x, TEMP[3].xxxx
 16:   MUL TEMP[3].x, TEMP[6].xxxx, TEMP[7].xxxx
 17:   ADD TEMP[6].x, CONST[7].xxxx, -IN[3].yyyy
 18:   RCP TEMP[7].x, TEMP[3].xxxx
 19:   MUL TEMP[4].x, TEMP[6].xxxx, TEMP[7].xxxx

While after this patch it becomes:

 13: UIF TEMP[7].xxxx :0
 14:   ADD TEMP[7].x, CONST[6].xxxx, -IN[3].yyyy
 15:   RCP TEMP[8].x, TEMP[3].xxxx
 16:   MUL TEMP[4].x, TEMP[7].xxxx, TEMP[8].xxxx
 17:   ADD TEMP[7].x, CONST[7].xxxx, -IN[3].yyyy
 18:   RCP TEMP[8].x, TEMP[3].xxxx
 19:   MUL TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx

Most importantly note that in the first example, the second RCP is done
on the result of the MUL while in the second, the second RCP should have
the same value as the first. Looking at the GLSL source, it is apparent
that both of the RCP's should have had the same source.

Looking at what's going on, the GLSL looks something like

  float tmin_8;
  float tmin_10;
  tmin_10 = tmin_8;
... lots of code ...
  tmin_8 = tmpvar_17;
... more code that never looks at tmin_8 ...

And so we end up with a last_read somewhere at the beginning, and a
first_write somewhere at the bottom. For some reason DCE doesn't remove
it, but even if that were fixed, DCE doesn't handle 100% of cases, esp
including loops.

With the last_read somewhere high up, we overwrite the previously
correct (and large) last_read with a low one, and then proceed to decide
to merge all kinds of junk onto this temp. Even if that weren't the
case, and there were just some writes after the last read, then we might
still overwrite a merged value with one of those.

As a result, we should treat a write as a last_read for the purpose of
determining the live range.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
8 years agoi965/gen7+: Use NIR for lowering of pack/unpack opcodes.
Matt Turner [Mon, 25 Jan 2016 19:07:28 +0000 (11:07 -0800)]
i965/gen7+: Use NIR for lowering of pack/unpack opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965/vec4: Implement nir_op_pack_uvec2_to_uint.
Matt Turner [Mon, 25 Jan 2016 18:49:15 +0000 (10:49 -0800)]
i965/vec4: Implement nir_op_pack_uvec2_to_uint.

And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agonir: Add lowering support for unpacking opcodes.
Matt Turner [Mon, 25 Jan 2016 19:07:02 +0000 (11:07 -0800)]
nir: Add lowering support for unpacking opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agonir: Add lowering support for packing opcodes.
Matt Turner [Mon, 25 Jan 2016 19:05:52 +0000 (11:05 -0800)]
nir: Add lowering support for packing opcodes.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965/fs: Implement support for extract_word.
Matt Turner [Thu, 21 Jan 2016 02:56:37 +0000 (18:56 -0800)]
i965/fs: Implement support for extract_word.

The vec4 backend will lower it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agonir: Add opcodes to extract bytes or words.
Matt Turner [Thu, 21 Jan 2016 17:09:29 +0000 (09:09 -0800)]
nir: Add opcodes to extract bytes or words.

The uint versions zero extend while the int versions sign extend.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoglsl: Remove 2x16 half-precision pack/unpack opcodes.
Matt Turner [Thu, 21 Jan 2016 19:46:22 +0000 (11:46 -0800)]
glsl: Remove 2x16 half-precision pack/unpack opcodes.

i965/fs was the only consumer, and we're now doing the lowering in NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.
Matt Turner [Thu, 21 Jan 2016 23:30:57 +0000 (15:30 -0800)]
i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agonir: Add lowering of nir_op_unpack_half_2x16.
Matt Turner [Thu, 21 Jan 2016 23:46:47 +0000 (15:46 -0800)]
nir: Add lowering of nir_op_unpack_half_2x16.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965: Make separate nir_options for scalar/vector stages.
Matt Turner [Thu, 21 Jan 2016 17:30:05 +0000 (09:30 -0800)]
i965: Make separate nir_options for scalar/vector stages.

We'll want to have different lowering options set for scalar/vector
stages.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965: Move brw_compiler_create() to new brw_compiler.c.
Matt Turner [Thu, 21 Jan 2016 17:19:53 +0000 (09:19 -0800)]
i965: Move brw_compiler_create() to new brw_compiler.c.

A future patch will want to use designated initalizers, which aren't
available in C++, but this is C.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agonir: Make argument order of unop_convert match binop_convert.
Matt Turner [Thu, 21 Jan 2016 17:54:19 +0000 (09:54 -0800)]
nir: Make argument order of unop_convert match binop_convert.

Strangely the return and parameter types were reversed.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: enable enums for OES_geometry_shader
Marta Lofstedt [Tue, 26 Jan 2016 08:48:50 +0000 (09:48 +0100)]
mesa: enable enums for OES_geometry_shader

Enable GL_OES_geometry_shader enums for OpenGL ES 3.1.

V4: EXTRA tokens updated according to comments from Ilia Mirkin.

V5: Account for check_extra does not evaluate "or" lazy. Fix issues
with EXTRA_EXT_FB_NO_ATTACH_CS.

Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agogallium: Add DragonFly support
François Tigeot [Sun, 17 Jan 2016 09:10:21 +0000 (10:10 +0100)]
gallium: Add DragonFly support

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agonv50/ir: get rid of memory stores with nop values
Ilia Mirkin [Fri, 29 Jan 2016 23:23:21 +0000 (18:23 -0500)]
nv50/ir: get rid of memory stores with nop values

This happens especially with exports and varying packing, where the last
bits aren't always filled in. We end up trying to do quad-wide stores,
which ends up being a lot of register moves that carefully preserve the
nop value. Instead don't do the stores.

total instructions in shared programs : 6131375 -> 6125267 (-0.10%)
total gprs used in shared programs    : 910139 -> 895501 (-1.61%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst
    helped           0        7442        4693
      hurt           0          90        2687

Most of the helped/hurt instruction changes are by one or two ops
because can no longer do quad-wide stores in all cases.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: fix false global CSE on instructions with multiple defs
Ilia Mirkin [Sat, 30 Jan 2016 22:13:33 +0000 (17:13 -0500)]
nv50/ir: fix false global CSE on instructions with multiple defs

If an instruction has multiple defs, we have to do a lot more checks to
make sure that we can move it forward. Among other things, various code
likes to do

    a, b = tex()
    if () c = a
    else c = b

which means that a single phi node will have results pointing at the
same instruction. We obviously can't propagate the tex in this case, but
properly accounting for this situation is tricky. Just don't try for
instructions with multiple defs.

This fixes about 20 shaders in shader-db, including the dolphin efb2ram
shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
8 years agonv50,nvc0: fix buffer clearing to respect engine alignment requirements
Ilia Mirkin [Sat, 30 Jan 2016 15:02:43 +0000 (10:02 -0500)]
nv50,nvc0: fix buffer clearing to respect engine alignment requirements

It appears that the nvidia render engine is quite picky when it comes to
linear surfaces. It doesn't like non-256-byte aligned offsets, and
apparently doesn't even do non-256-byte strides.

This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0.

As a side-effect this also allows RGB32 clears to work via GPU data
upload instead of synchronizing the buffer to the CPU (nvc0 only).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> # tested on GF108, GT215
Tested-by: Nick Sarnie <commendsarnex@gmail.com> # GK208
Cc: mesa-stable@lists.freedesktop.org
8 years agofreedreno/ir3: ignore clip-vertex varying
Rob Clark [Wed, 27 Jan 2016 17:05:12 +0000 (12:05 -0500)]
freedreno/ir3: ignore clip-vertex varying

Since we emulate clip-planes, the clip-vertex is used within the VS
itself (thanks to nir_lower_clip).  So just ignore it as a VS output.
Fixes a boatload of piglit tests that were asserting on unknown
varying slot.

(Also unrelated spelling/typo fix.)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: don't ignore local vars
Rob Clark [Sat, 7 Nov 2015 13:46:02 +0000 (08:46 -0500)]
freedreno/ir3: don't ignore local vars

With glsl_to_nir we end up with local variables, instead of global, for
arrays.

Note that we'll eventually have to do something more clever, I think,
when we support multiple functions, but that will probably take some
work in a few places.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: handle tex instrs w/ const offset
Rob Clark [Thu, 5 Nov 2015 20:38:32 +0000 (15:38 -0500)]
freedreno/ir3: handle tex instrs w/ const offset

Something we start to see with glsl_to_nir.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: support load_front_face intrinsic
Rob Clark [Thu, 5 Nov 2015 18:31:25 +0000 (13:31 -0500)]
freedreno/ir3: support load_front_face intrinsic

With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE.
But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno: limit string marker to max packet size
Rob Clark [Sun, 24 Jan 2016 18:18:39 +0000 (13:18 -0500)]
freedreno: limit string marker to max packet size

Experimentally derived max size.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agonvc0: avoid crashing when there are holes in vertex array bindings
Ilia Mirkin [Sat, 30 Jan 2016 01:28:12 +0000 (20:28 -0500)]
nvc0: avoid crashing when there are holes in vertex array bindings

When using the "shared" vertex array configuration strategy, we bind
each of the buffers as a separate array. However there can be holes in
such vertex buffer lists, so just emit a disable for those.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
8 years agonvc0: enable atomic counters and ssbo
Ilia Mirkin [Sun, 3 Jan 2016 03:23:44 +0000 (22:23 -0500)]
nvc0: enable atomic counters and ssbo

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: handle new TGSI MEMBAR opcode
Ilia Mirkin [Sun, 17 Jan 2016 09:34:08 +0000 (04:34 -0500)]
nv50/ir: handle new TGSI MEMBAR opcode

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0/ir: fix atomic compare-and-swap arguments
Ilia Mirkin [Mon, 11 Jan 2016 02:47:04 +0000 (21:47 -0500)]
nvc0/ir: fix atomic compare-and-swap arguments

Teach the emitter that the two registers are sequential, and drop the
second arg entirely, in favor of a double-wide first argument.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: add support for indirect buffer loading
Ilia Mirkin [Tue, 19 Jan 2016 04:34:01 +0000 (23:34 -0500)]
nv50/ir: add support for indirect buffer loading

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: add SUQ op by reading the info from driver constbuf
Ilia Mirkin [Mon, 14 Dec 2015 05:13:34 +0000 (00:13 -0500)]
nv50/ir: add SUQ op by reading the info from driver constbuf

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>