Dmitry Selyutin [Sun, 18 Sep 2022 16:05:42 +0000 (19:05 +0300)]
test_pysvp64dis: test RC1/~RC1 in ff/pr
Dmitry Selyutin [Sun, 18 Sep 2022 16:05:11 +0000 (19:05 +0300)]
power_insn: fix Rc operand accessor
Dmitry Selyutin [Sun, 18 Sep 2022 15:32:33 +0000 (18:32 +0300)]
power_insn: support RC1/~RC1 in ff/pr
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:23:20 +0000 (16:23 +0100)]
comment principle behind new tables in power_insn.py
https://libre-soc.org/irclog/%23libre-soc.2022-09-18.log.html#t2022-09-18T16:22:37
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:17:59 +0000 (16:17 +0100)]
redo branch mode as a table, in power_insn.py
Dmitry Selyutin [Sun, 18 Sep 2022 15:17:05 +0000 (18:17 +0300)]
power_insn: adjust table comments
Dmitry Selyutin [Sun, 18 Sep 2022 15:13:40 +0000 (18:13 +0300)]
power_insn: another minor ld/st imm table cleanup
Dmitry Selyutin [Sun, 18 Sep 2022 15:12:24 +0000 (18:12 +0300)]
pysvp64asm: make zz also set src_zero
Dmitry Selyutin [Sun, 18 Sep 2022 15:08:18 +0000 (18:08 +0300)]
power_insn: minor CR cleanup
Dmitry Selyutin [Sun, 18 Sep 2022 15:06:00 +0000 (18:06 +0300)]
power_insn: minor cleanup
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:06:37 +0000 (16:06 +0100)]
code-morph CR ops to table in power_insn.py
put 3/5-bit detection into one of the options to search in mask/val form
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:52:41 +0000 (15:52 +0100)]
code-morph in power_insn.py - move table-search to separate area
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:50:25 +0000 (15:50 +0100)]
LDST_IDX Mode converted to table
(and fixed bug double-LDST_IMM test) in power_insn.py
Dmitry Selyutin [Sun, 18 Sep 2022 14:08:52 +0000 (17:08 +0300)]
power_insn: support m/sm/dm specifiers
Dmitry Selyutin [Sun, 18 Sep 2022 13:54:01 +0000 (16:54 +0300)]
power_insn: pass record to specifiers
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:13:33 +0000 (15:13 +0100)]
replace LDST_IMM mode with mask/value match table in power_insn.py
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:07:49 +0000 (15:07 +0100)]
remove (invalid) NormalSaturationExtRM mode from power_insn.py
(was in SUBVL>1 which is now gone)
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:04:22 +0000 (15:04 +0100)]
reduce NORMAL svp64 mode down to a mask-value search
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 13:45:32 +0000 (14:45 +0100)]
remove subvector mode from power_insn.py
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 13:34:15 +0000 (14:34 +0100)]
adapt test_12_mr to /mrr and /mr modes, svm is gone, /mr is missing
Dmitry Selyutin [Sun, 18 Sep 2022 09:07:57 +0000 (12:07 +0300)]
test_pysvp64dis: test mrr/svm specifiers
Dmitry Selyutin [Sun, 18 Sep 2022 10:40:56 +0000 (13:40 +0300)]
power_fields: fix __lt__ operator
Dmitry Selyutin [Sun, 18 Sep 2022 09:29:58 +0000 (12:29 +0300)]
power_insn: support mrr specifier
Dmitry Selyutin [Sun, 18 Sep 2022 09:07:17 +0000 (12:07 +0300)]
power_insn: support svm specifier
Dmitry Selyutin [Sun, 18 Sep 2022 10:26:19 +0000 (13:26 +0300)]
power_insn: sync RM modes
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 13:29:50 +0000 (14:29 +0100)]
remove subvector mode from sv/trans/svp64.py
Dmitry Selyutin [Sun, 18 Sep 2022 09:01:04 +0000 (12:01 +0300)]
power_insn: support w/dw/sw specifiers
Dmitry Selyutin [Sun, 18 Sep 2022 08:52:13 +0000 (11:52 +0300)]
power_insn: decouple branch modes
Dmitry Selyutin [Sun, 18 Sep 2022 08:46:49 +0000 (11:46 +0300)]
power_insn: decouple cr_op modes
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 08:50:08 +0000 (09:50 +0100)]
change sv/trans/svp64.py source/dest elwidth assembler naming
https://libre-soc.org/irclog/%23libre-soc.2022-09-18.log.html#t2022-09-18T09:40:40
Dmitry Selyutin [Sun, 18 Sep 2022 08:31:02 +0000 (11:31 +0300)]
test_pysvp64dis: test sw specifier
Dmitry Selyutin [Sun, 18 Sep 2022 08:29:36 +0000 (11:29 +0300)]
power_insn: support sw specifier
Dmitry Selyutin [Sun, 18 Sep 2022 08:26:34 +0000 (11:26 +0300)]
power_insn: decouple common normal and ld/st RM
Dmitry Selyutin [Sun, 18 Sep 2022 08:09:07 +0000 (11:09 +0300)]
power_insn: support ew specifier
Dmitry Selyutin [Sun, 18 Sep 2022 08:06:04 +0000 (11:06 +0300)]
power_insn: simplify subvl disassembly
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 20:52:50 +0000 (21:52 +0100)]
add sat/satu test_12_sat to test_pysvp64dis.py
Dmitry Selyutin [Sat, 17 Sep 2022 20:48:34 +0000 (23:48 +0300)]
power_insn: fix sat checks
Dmitry Selyutin [Sat, 17 Sep 2022 20:42:48 +0000 (23:42 +0300)]
pysvp64asm: SVP64 instruction debug logs
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 20:47:02 +0000 (21:47 +0100)]
whoops. mode-bits need to be put in MSB0 order. sigh
Dmitry Selyutin [Sat, 17 Sep 2022 20:26:42 +0000 (23:26 +0300)]
power_fields: fix mapping class accessor
Dmitry Selyutin [Sat, 17 Sep 2022 19:54:02 +0000 (22:54 +0300)]
power_fields: support boolean checks
Dmitry Selyutin [Sat, 17 Sep 2022 19:46:37 +0000 (22:46 +0300)]
power_insn: fix zz specifiers
Dmitry Selyutin [Sat, 17 Sep 2022 19:31:42 +0000 (22:31 +0300)]
power_insn: drop field length method again
Dmitry Selyutin [Sat, 17 Sep 2022 18:57:27 +0000 (21:57 +0300)]
power_insn: decouple base ld/st idx RM
Dmitry Selyutin [Sat, 17 Sep 2022 18:53:08 +0000 (21:53 +0300)]
power_insn: decouple base ld/st imm RM
Dmitry Selyutin [Sat, 17 Sep 2022 18:43:01 +0000 (21:43 +0300)]
power_insn: decouple base normal RM
Dmitry Selyutin [Sat, 17 Sep 2022 16:17:33 +0000 (19:17 +0300)]
power_insn: support saturation mode
Dmitry Selyutin [Sat, 17 Sep 2022 16:07:53 +0000 (19:07 +0300)]
power_insn: support dz/sz specifiers
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 19:48:57 +0000 (20:48 +0100)]
add zz mode to sv/trans/svp64.py as a hack
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 18:53:34 +0000 (19:53 +0100)]
remove sv.setvl/pk/up/pu - these are all gone in favour of using
a hack-job on svstep 0b11nn
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 18:46:18 +0000 (19:46 +0100)]
add MASK_SRC to power_insn.py (SVmask_src from enums)
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 18:37:52 +0000 (19:37 +0100)]
add SVmask_src enum, rename fields to EN and NO to make it easier
to detect/read
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 18:31:30 +0000 (19:31 +0100)]
as a double-check sv_analysis new CSV column "SM" was all set to zero
by now changing it to 1, this diff/commit shows exactly which
files are now classified as MASK_SRC=enabled
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 18:23:25 +0000 (19:23 +0100)]
add a "SM" column into RM*.csv (and LDSTRM*.csv) identifying if MASK_SRC
is active. this makes disassembly much easier, no need to check RM type
or count the number of registers
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 17:50:41 +0000 (18:50 +0100)]
add sv.add/ew=XX test to test_pysvp64dis.py
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 17:11:33 +0000 (18:11 +0100)]
remove pack/unpack modes from power_insn.py, they no longer exist
Dmitry Selyutin [Sat, 17 Sep 2022 15:42:17 +0000 (18:42 +0300)]
selectable_int: drop redundant operators
Dmitry Selyutin [Sat, 17 Sep 2022 13:54:01 +0000 (16:54 +0300)]
power_insn: support vec2/vec3/vec4
Dmitry Selyutin [Sat, 17 Sep 2022 13:52:34 +0000 (16:52 +0300)]
power_insn: support specifiers
Dmitry Selyutin [Sat, 17 Sep 2022 13:51:50 +0000 (16:51 +0300)]
power_fields: fix comparison operators
Dmitry Selyutin [Sat, 17 Sep 2022 13:03:30 +0000 (16:03 +0300)]
power_insn: refactor and fix RM mappings
Dmitry Selyutin [Sat, 17 Sep 2022 12:57:40 +0000 (15:57 +0300)]
power_fields: fix field slicing
Dmitry Selyutin [Sat, 17 Sep 2022 12:44:28 +0000 (15:44 +0300)]
power_insn: fix mapping bits accessors
Dmitry Selyutin [Sat, 17 Sep 2022 12:41:59 +0000 (15:41 +0300)]
power_fields: support traversing over instances
Dmitry Selyutin [Sat, 17 Sep 2022 09:13:35 +0000 (12:13 +0300)]
power_insn: drop redundant table
Dmitry Selyutin [Sat, 17 Sep 2022 09:13:11 +0000 (12:13 +0300)]
power_fields: inherit docstrings upon remap
Luke Kenneth Casson Leighton [Sat, 17 Sep 2022 15:53:28 +0000 (16:53 +0100)]
add vec2/3/4 test_pysvp64dis test
Luke Kenneth Casson Leighton [Fri, 16 Sep 2022 21:44:45 +0000 (22:44 +0100)]
comments on test_9_fptrans
Dmitry Selyutin [Fri, 16 Sep 2022 19:50:40 +0000 (22:50 +0300)]
test_power_decoder: mark minor_19.csv as opint
Dmitry Selyutin [Fri, 16 Sep 2022 16:54:04 +0000 (19:54 +0300)]
test_pysvp64dis: test fptrans
Dmitry Selyutin [Fri, 16 Sep 2022 16:54:04 +0000 (19:54 +0300)]
selectable_int: replace bit_count with bit_length
Dmitry Selyutin [Fri, 16 Sep 2022 16:54:04 +0000 (19:54 +0300)]
sv_binutils_fptrans: adopt script for reuse
Dmitry Selyutin [Fri, 16 Sep 2022 14:39:51 +0000 (17:39 +0300)]
power_insn: postpone updating per-instruction operands
Dmitry Selyutin [Thu, 15 Sep 2022 20:56:49 +0000 (23:56 +0300)]
power_insn: perform faster PPC database lookups
Dmitry Selyutin [Wed, 14 Sep 2022 23:04:35 +0000 (02:04 +0300)]
sv_binutils_fptrans: fix disassembly
Dmitry Selyutin [Wed, 14 Sep 2022 23:04:35 +0000 (02:04 +0300)]
sv_binutils_fptrans: fptrans binutils generator
Dmitry Selyutin [Wed, 14 Sep 2022 23:04:12 +0000 (02:04 +0300)]
power_insn: support instruction bytes conversion
Dmitry Selyutin [Wed, 14 Sep 2022 22:50:10 +0000 (01:50 +0300)]
selectable_int: allow setting multiple bit
Dmitry Selyutin [Wed, 14 Sep 2022 22:49:15 +0000 (01:49 +0300)]
power_insn: allow accessing instruction bits
Luke Kenneth Casson Leighton [Thu, 15 Sep 2022 20:48:28 +0000 (21:48 +0100)]
add minor_4.csv for maddld/maddhdu/maddhd and to insn_db.csv
also add test_pysvp64dis.py to check it asm/disasms
Luke Kenneth Casson Leighton [Thu, 15 Sep 2022 00:46:14 +0000 (01:46 +0100)]
fix sprset mtspr/mfspr pseudocode with wrong definition of
spr, not existent in the Power v3.0 spec.
https://bugs.libre-soc.org/show_bug.cgi?id=917#c54
works fine, required removal of hack in ISACaller to uppercase spr
to SPR
Jacob Lifshay [Wed, 14 Sep 2022 15:35:03 +0000 (08:35 -0700)]
add svp64 fptrans tests
Jacob Lifshay [Wed, 14 Sep 2022 15:33:55 +0000 (08:33 -0700)]
include *all* fprs/gprs/cr-fields in SimState
Jacob Lifshay [Wed, 14 Sep 2022 15:33:10 +0000 (08:33 -0700)]
fix sv_analysis for fpown and frootn
Jacob Lifshay [Wed, 14 Sep 2022 15:31:34 +0000 (08:31 -0700)]
fix some typos
Dmitry Selyutin [Tue, 13 Sep 2022 19:12:37 +0000 (22:12 +0300)]
power_insn: support signed operands
Dmitry Selyutin [Tue, 13 Sep 2022 12:18:41 +0000 (15:18 +0300)]
power_insn: support branch RM
Dmitry Selyutin [Tue, 13 Sep 2022 11:48:40 +0000 (14:48 +0300)]
power_insn: support CR RM
Dmitry Selyutin [Tue, 13 Sep 2022 13:09:52 +0000 (16:09 +0300)]
power_enums: convert SVExtra to RegType
Dmitry Selyutin [Mon, 12 Sep 2022 19:28:52 +0000 (22:28 +0300)]
power_insn: refactor RM mapping
Dmitry Selyutin [Mon, 12 Sep 2022 19:28:24 +0000 (22:28 +0300)]
sv_binutils: support multiple opcodes; minor fixes
Luke Kenneth Casson Leighton [Tue, 13 Sep 2022 19:31:45 +0000 (20:31 +0100)]
correct assrmbler in test_pysvpy4dis.py
Jacob Lifshay [Tue, 13 Sep 2022 18:01:29 +0000 (11:01 -0700)]
fix X-FORM lines for fptrans -- I forgot Rc
Jacob Lifshay [Tue, 13 Sep 2022 17:59:22 +0000 (10:59 -0700)]
add missing X-FORM lines for fptrans
Jacob Lifshay [Tue, 13 Sep 2022 17:30:55 +0000 (10:30 -0700)]
add comment that fptrans test cases output values are probably not all correct
[skip ci]
Jacob Lifshay [Tue, 13 Sep 2022 17:19:57 +0000 (10:19 -0700)]
add new fptrans unit tests
Jacob Lifshay [Tue, 13 Sep 2022 17:19:06 +0000 (10:19 -0700)]
add fptrans support to isa caller
Jacob Lifshay [Tue, 13 Sep 2022 17:18:40 +0000 (10:18 -0700)]
add fp support to TestRunnerBase
Luke Kenneth Casson Leighton [Tue, 13 Sep 2022 15:23:54 +0000 (16:23 +0100)]
add first pack/unpack to ISACaller
Luke Kenneth Casson Leighton [Tue, 13 Sep 2022 13:42:53 +0000 (14:42 +0100)]
add setter/getter properties to SVP64State, minor code-morph in ISACaller