arch-arm: Adapting IllegalExecution fault for AArch32

The Illegal Execution fault triggered by the setting of processor state
PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED
exception fault.  We are hence copying the UndefinedInstruction AArch32
fields into the IllegalInstSetStateFault.

Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add Illegal Execution flag to PCState

This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage.  This is
done by adding the illegalExecution field to the PCState.

Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Read APSR in User Mode

This patch substitutes reads to the CPSR in user mode (MRS CPSR) to
reads to APSR (Application Program Status Register).
This is the user level alias for the CPSR. The APSR is a subset of the
CPSR.

Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

system-arm: Split the VExpress_GEM5_V1 base dts

With the introduction of the new DPU model, we need different
variations of the VExpress_GEM5_V1 platform. This splits the platform
dtsi file into a separate file for the base platform and the
HDLCD-based platform. This matches the hierarchy in RealView.py.

Change-Id: Id02380122655b5d3aa3548a703fdef178bba17d9
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11035
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Add new VExpress_GEM5_V1_Base Platform

Add a new VExpress_GEM5_V1_Base Platform which configures basic on
chip devices. The original VExpress_GEM5_V1 will inherit the Base and
add more on chip devices (currently only the HDLCD). This change will
make it possible to create variations of the base platform with
different devices.

Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10807
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu-minor: Remove redundant thread startup call

Don't call startup() twice on each of the threads.

Change-Id: Ibe3d1f25c4fdff291ee310abb9bcad3b184bab20
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11037

dev-arm: Remove deprecated GIC test interfaces

Change-Id: I4c5203b216387d9a4f041c7a00caea926e5cfca6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10810

tests: Make "UnitTest"s more like GTest so they can be in other dirs.

The original implementation of UnitTest forced all the output binaries
to live in the unittest directory, effectively forcing a flat
namespace, and seperating the tests from the things they were supposed
to be testing.

This changes makes them work more like the newer GTest tests in that
they can be based out of whatever directory makes sense, although
they're currently all still in unittest for the time being.

This change also gets rid of automatically tagging the sources
associated with a test with the tests name. The first reason for that
was that this also forced a flat namespace, since the tests names
didn't have any reference to the test's path. Second, this way of
pulling in additional files wasn't necessary any more, now that the
UnitTest sources could be source filters like they can be for GTests.

Change-Id: I3d96ed766ac5170842dbd6daee39f2873bcd6c75
Reviewed-on: https://gem5-review.googlesource.com/10701
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Remove unnecessary cast in SectorTags::findVictim

Removes an uneccessary cast that also caused an unused variable
error (due to -Werror) when compiling .fast targets.

Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980
Reviewed-on: https://gem5-review.googlesource.com/11119
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix missing Request allocation

This patch is fixing a missing allocation for a Request buffer
in the Stage2Translation class.

Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11095
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Insert on block allocation

When a block is being replaced in an allocation, if successfull,
the block will be inserted. Therefore we move the insertion
functionality to allocateBlock().

allocateBlock's signature has been modified to allow this
modification.

Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc
Reviewed-on: https://gem5-review.googlesource.com/10812
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make packet const in insertBlock

The packet should not be modified within insertBlock.

Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a
Reviewed-on: https://gem5-review.googlesource.com/10811
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create Sector Cache

Implementation of Sector Caches, i.e., a cache with multiple
sequential data entries per tag entry for Set Associtive
placement policies.

Change-Id: I8e1e9448fa44ba308ccb16cd5bcc5fd36c988feb
Reviewed-on: https://gem5-review.googlesource.com/9741
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

ruby: Fix initial weight in weighted LRU

Initial weight was using the timestamp instead of the weight.

Change-Id: I61d3c8424f85fd6856957087c477afda111f8ca7
Reviewed-on: https://gem5-review.googlesource.com/10801
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

misc: Substitute pointer to Request with aliased RequestPtr

Every usage of Request* in the code has been replaced with the
RequestPtr alias.  This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.

Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-cache: Change Cache block tag check

Change tag to address check for compatibility with sector design.
Cache should not use tag, as sector sub-blocks share them, and
it could lead to wrong accesses.

Change-Id: Id1fa26f417595f475c5b5c07ae1f02f5fa0684ba
Reviewed-on: https://gem5-review.googlesource.com/10723
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use secure bit in findVictim

Sector caches must know if there was a sector hit in order
to decide whether a victim's sector must be fully evicted
to give place to a new sector or not.

In order to do so it needs the tag and secure information.

Change-Id: Ib554169e25fa131d6bf986561f7970b787c56874
Reviewed-on: https://gem5-review.googlesource.com/10722
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move tagsInUse to children

Move tagsInUse to children, as sector caches have different
tag invalidation and insertion, and thus they must handle
updating this variable.

Change-Id: I875c9b7364a909c76daf610d1e226c4e82063870
Reviewed-on: https://gem5-review.googlesource.com/10721
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Return evictions along with victims

For both sector and compressed caches multiple blocks may need
to be evicted in order to make room for a new block.

For example, when replacing a sector, all the blocks in this
sector must be evicted. A replacement, however, does not always
need to evict multiple blocks, as it is in the case of an
insertion of a block whose sector is already present in the cache
(i.e., its corresponding entry in the sector had not been brought
in yet, so it was invalid).

This patch creates the cache framework for that to happen.

Change-Id: I77bedf69637cf899fef4d9432eb6da8529ea398b
Reviewed-on: https://gem5-review.googlesource.com/10142
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use ReplaceableEntry in findBlockBySetAndWay

With a sector cache you can't find a block using only its set
and way, as there is the sector offset to take into account. As
all of these blocks inherit from ReplaceableEntry, the return
type of this function has been updated.

This function has also been declared closer to findBlock() due
to their similar functionality.

Change-Id: I4730a2b4ebb5738f7fc118201e208a1b9c3ba8e8
Reviewed-on: https://gem5-review.googlesource.com/10141
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

sim: Rename the SimObject cxx_bases field to cxx_extra_bases.

cxx_bases adds in additional c++ base classes beyond those implied by
the python SimObject inheritance hierarchy. To imply the fact that
these are additional bases, and to disambiguate a future mechanism
which changes the implied bases, this flag/field is being renamed from
cxx_bases to cxx_extra_bases.

As far as I can tell, this field was only used internally in
SimObject.py.

Change-Id: Ie7cc3d0107ff71cc31424d6e20c9a2f430022ab9
Reviewed-on: https://gem5-review.googlesource.com/10661
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1

Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1
platform.

Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2327

dev-arm: Add a MMIO transport interface for VirtIO

The MMIO interface currently only supports a subset of version 0.9.5
of the VirtIO specification. It has the following known limitations:

  * The queue size hint (the QUEUE_NUM register) is ignored.

  * Queue alignment is assumed to be hard-coded to
    VirtQueue::ALIGN_SIZE (4096 bytes).

  * Only 4096 byte pages are currently supported.

Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev-arm: Add a GIC interrupt adaptor

Add GIC-based interrupt adaptor implementations that support PPI
(ArmPPI) and SPI (ArmSPI) delivery. In addition to being useful for
"normal" memory-mapped devices, the PPI adaptor makes it possible to
use the same device model to generate both PPIs and SPIs (e.g., the
PMU).

Change-Id: I73d6591c168040faef2443430c4f1da10c387a2a
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2521
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Remove dead doingStage2 variable in PT walker

Change-Id: Iab5ecec56120c725847b2e462fd4793cfac87d3c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10815

system-arm: Update gem5 timer interrupt specification

The DTB for the VExpress_GEM5_V1 was incorrectly flagging timer
interrupts as being edge triggered. Describe the interrupt as being
level triggered to match Juno and FVP.

Change-Id: I9ce4b8959e7cc28d8b208727119ff20e581311f8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10024
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Perform stage 2 lookups using the EL2 state

Change-Id: Ic56b694f22a26e9c208a10e5703d4b5b0900070f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10507
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Respect EL from translation type

There are cases where instructions request translations in the context
of a lower EL. This is currently not respected in the TLB and the page
table walker. Fix that.

Change-Id: Icd59657a1ecfd8bd75a001bb1a4e41a6f4808a36
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10506
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Fix page size handling when merging stage 1 and 2

The current code to merge translation entries from stage 1 and stage 2
doesn't handle cases where the page sizes at the different stages
differ. This change fixes both the case when the hypervisor has a
larger page size and when it has a smaller page size.

Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10505
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

dev, arm: Add support for HYP & secure timers

Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10023
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Adjust breakpoint EC depending on source state

The software breakpoint exception class needs to be adjusted depending
on the source EL's execution state. This change fixes an incorrect
exception class when taking a breakpoint from aarch64.

Change-Id: I99d87a04be6bf9ce3a69f6b19969fa006cfd63a4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-cache: Privatize extractSet

Only BaseSetAssoc uses extractSet(). Besides, skewed caches need
the way information to know which set an address is located at.

Change-Id: Id222e907dc550d053018561bb2683cfc415471ec
Reviewed-on: https://gem5-review.googlesource.com/9962
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Create an address aware TempCacheBlk

tempBlock has its member variables  manually set in order to allow
it to be used in the block address regeneration function. This is
not necessary, and ti can be simply given the address, so  it does
not need to be aware of set and tag. This will simplify
implementation of sector and skewed caches.

Change-Id: Iaffb10c323509722cd5589fe1030b818d43336d6
Reviewed-on: https://gem5-review.googlesource.com/9961
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix secure bit modification

Secure bit was being updated outside insertion.

Change-Id: I83d9b010e8cf64013bbea9bae3ea68b0c414a189
Reviewed-on: https://gem5-review.googlesource.com/10622
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Replace block visitor with std::function

This change modifies forEachBlk tags function to accept std::function
as parameter. It also adds an anyBlk tags function that given a
condition, it iterates through the blocks and returns whether the
condition is met.

Finally, it uses forEachBlk to implement the print, computeStats and
cleanupRefs functions that also work for the FALRU class.

Change-Id: I2f75f4baa1fdd5a1d343a63ecace3eb9458fbf03
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10621
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix include directives in the cache related classes

Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c
Reviewed-on: https://gem5-review.googlesource.com/10433
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add a non-coherent cache

The class re-uses the existing MSHR and write queue. At the moment
every single access is handled by the cache, even uncacheable
accesses, and nothing is forwarded.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a
Reviewed-on: https://gem5-review.googlesource.com/8291
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move cache bypass mechanism to the ports

Cache bypass is necessary for cpu models like the KvmCPU. Previously
the bypass would happen at the cache classes. With this change the
bypassing happens directly at the ports.

Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62
Reviewed-on: https://gem5-review.googlesource.com/10432
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Adopt a more sensible cache class hierarchy

This patch changes what goes into the BaseCache and what goes into the
Cache, to make it easier to add a NoncoherentCache with as much re-use
as possible. A number of redundant members and definitions are also
removed in the process.

This is a modified version of a changeset put together by Andreas
Hansson <andreas.hansson@arm.com>

Change-Id: Ie9dd73c4ec07732e778e7416b712dad8b4bd5d4b
Reviewed-on: https://gem5-review.googlesource.com/10431
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add helper function to perform evictions

Change-Id: I2df24eb1a8516220bec9b685c8c09bf55be18681
Reviewed-on: https://gem5-review.googlesource.com/10430
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Delegate block invalidation to block allocation

For a block replacement we first select a victim block, we invalidate
it and then populate it with the new information. Prior to this change
BaseTags::insertBlock() did the invalidation and filled in the block
with the new information. Now that the replacements stat is moved to
the BaseCache, insertBlock does not need to perform the invalidation
and as a result we can unify the block eviction code in BaseCache.

Change-Id: I5bdf00b2dab2752ed2137ab7201ed1dc451333b3
Reviewed-on: https://gem5-review.googlesource.com/10429
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Refactor the recvAtomic function

The recvAtomic function in the cache handles atomic requests. Over
time, recvAtomic has grown in complexity and code size. This change
factors out some of its functionality in a separate functiona. The new
functions handles atomic requests that miss.

Change-Id: If77d2de1e3e802e1da37f889f68910e700c59209
Reviewed-on: https://gem5-review.googlesource.com/10425
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Refactor the cache recvTimingReq function

The recvTimingReq function in the cache handles timing requests. Over
time, recvTimingReq has grown in complexity and code size. This change
factors out some of its functionality in two separate functions. The
new functions handle timing requests that hit and timing requests that
miss separately.

Change-Id: I09902d648d7272f0f9ec2851fa6376f7305ba418
Reviewed-on: https://gem5-review.googlesource.com/10424
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Refactor the cache recvTimingResp function

The recvTimingResp function in the cache handles timing
responses. Over time, recvTimingResp has grown in complexity and code
size. This change factors out some of its functionality to a separate
function. The new function iterates through the in-service targets and
handles them accordingly.

Change-Id: I0ef28288640f6be1b30452b0664d32432e692ea6
Reviewed-on: https://gem5-review.googlesource.com/10423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Fix RandomReplData

Random replacement policy's data was being instantiated with
the incorrect class.

Change-Id: Ib573a6b5a63868d6069997c6279bec3b10c6b9b9
Reviewed-on: https://gem5-review.googlesource.com/10623
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

gpu-compute: use X86ISA::TlbEntry over GpuTlbEntry

GpuTlbEntry was derived from a vanilla X86ISA::TlbEntry definition. It
wrapped the class and included an extra member "valid". This member was
intended to report on the validity of the entry, however it introduced
bugs when folks forgot to set field properly in the code. So, instead of
keeping the extra field which we might forget to set, we track validity by
using nullptr for invalid tlb entries (as the tlb entries are dynamically
allocated). This saves on the extra class definition and prevents bugs
creeping into the code since the checks are intrinsically tied into
accessing any of the X86ISA::TlbEntry members.

This changeset fixes the issues introduced by a8d030522, a4e722725, and
2a15bfd79.

Change-Id: I30ebe3ec223fb833f3795bf0403d0016ac9a8bc2
Reviewed-on: https://gem5-review.googlesource.com/10481
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

dev: Exit correctly in dist-gem5 for SE mode

Do not allow the exit() syscall to terminate gem5 when running in dist-gem5
mode.  The exit must be coordinated by the distributed interface instead.

Change-Id: I57f47610b59fe9e18ba3a1667fb5e45cecac1a81
Reviewed-on: https://gem5-review.googlesource.com/10461
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Mohammad Alian <m.alian1369@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Determine if an MSHR has requests from another cache

To decide whether we allocate upon receiving a response we need to
determine if any of the currently serviced requests (non-deferred
targets) is comming from another cache. This change adds support for
tracking this information in the MSHR.

Change-Id: If1db93c12b6af5813b91b9d6b6e5e196d327f038
Reviewed-on: https://gem5-review.googlesource.com/10422
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Remove unusued MISCREG_A64_UNIMPL

In case the decoder fails to find a suitable MiscReg during a MSR/MRS
in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra
MISCREG_A64_UNIMPL register.

Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: MPIDR.MT = 1 in a multithreaded system

MPIDR.MT Indicates whether the lowest level of affinity consists of
logical PEs that are implemented using a multithreading type approach

Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10502
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined

In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:

<op1> is in the range 0 - 7
<CRn> can take the values 11, 15
<CRm> is in the range 0 - 15
<op2> is in the range 0 - 7

Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

cpu: Avoid unnecessary dynamic_pointer_cast in atomic model

In the atomic model a dynamic_pointer_cast is performed at every tick to
check if the fault is a SyscallRetryFault. This was happening even when
there was no generated fault.

Change-Id: I7f4afeffffdf4f988230e05286602d8d9a919c6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10101
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Implement ARMv8.1 TTBR1_EL2 register

This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for
getting the translation table base address when a Host Operating System
is running at EL2. (HCR_EL2.E2H = 1)

Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10382
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Add E2H bit to HCR_EL2 System register

This patch adds the EL2 Host bit to the HCR_EL2 register.  Enables a
configuration where a Host Operating System is running in EL2, and the
Host Operating System's applications are running in EL0.

Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10381
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

x86: Add op classes to the MediaOps.

The ISA parser had been assuming these microops were all FloatAddOp
which is usually not correct.

Change-Id: Ic54881d16f16b50c3d6a8c74b94bff9ae3b1f43e
Reviewed-on: https://gem5-review.googlesource.com/10541
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Tariq Azmy <tariqslayer01@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem: Add support for more flexible DRAM timing and topologies

This patch has 2 main aspects:
1) Add new parameter to adjust write-to-write delay
2) Enable support of more than 64 banks per controller

Changes for new parameter:
Incorporated a new parameter, tCCD_L_WR, which defaults to tCCD_L.
This parameter can be used to set a unique delay between writes and
between reads.

To incorporate this parameter in the controller, modified the DRAMCtrl
class to have separate variables for read and write column delays.
Used these variables to account for tRTW, tWTR, tBURST, tCCD_L, and tCS
as well as the new tCCD_L_WR parameter.

Changes to support more than 64 banks:
Modified the logic selecting the next command (reorderQueue
and minBankPrep functions).  Replaced the unint64_t variables with
a vector of uint32_t elements.  There is a uint32_t element defined
per ranks to allow up to 32 banks per rank.  This will automatically
scale with ranks without issue.
Change will allow analysis of memory sub-systems beyond the current
landscape.

Change-Id: I0ce466efed58276f843ad90e9ecc0ece6c37d646
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10103
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem: Optimize self-refresh entry

Self-refresh is entered during a refresh event, when the
rank was previously in a precharge power-down state.
The original code would enter self-refresh after a refresh
was issued.  The device subsequently will issue a refresh
on self-refresh entry.  On self-refresh exit, the controller
will issue another refresh command.

Devices require at least one additional refresh to be issued
between self-refresh exit and re-entry.  This ensures that enough
refreshes occur in the case when the device narrowly missed a
refresh on self-refresh exit.

To minimize the number of refresh operations and still maintain
the device requirement, the current logic does the following:
1) The controller will still enter self-refresh from a refresh
   event, when the previous state was precharge power-down.
   However, the refresh itself will be bypassed and the controller
   will immediately issue a self-refresh entry.
2) On a self-refresh exit, the controller will immediately
   issue a refresh command (per the original logic).  This ensures
   the devices requirements are met and is a convenient way to
   kick off the command state machine.

Change-Id: I1c4b0dcbfa3bdafd755f3ccd65e267fcd700c491
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10102
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Move reference count stats update to blk invalidation

The tags in the cache keep track of the number of references to the
blocks as well as the average number of references between an
insertion and the next invalidation. Previously the stats where
updated only on block insertion and invalidations were ignored. This
changes moves the update of the counters to the block invalidation
function.

Change-Id: Ie7672c13813ec278a65232694024d2e5e17c4612
Reviewed-on: https://gem5-review.googlesource.com/10428
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Remove isTouched field from the CacheBlk

At the moment isTouched is used in the warm-up detection mechanism but
it keeps track of the same information as isValid(). This change
removes it and substitutes its use by isValid().

Change-Id: I611ddf2fa4562ae3b3b2ed2fb74d26abd2e5ec62
Reviewed-on: https://gem5-review.googlesource.com/10427
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Move replacements stat to the base cache class

Change-Id: I25dbcfcddfe1c422a76eb1af3f726c1360d8d110
Reviewed-on: https://gem5-review.googlesource.com/10426
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

base: Add M5 flag for [[nodiscard]] attribute

This change adds the M5_NODISCARD keyword to allow use of the
[[nodiscard]] attribute with compilers that support C++17. Currently,
C++17 is not a requirement and therefore the M5_NODISCARD has not
effect and does not break compilation for older compilers.

Change-Id: Ifc5c8f34764da3c7291066dcb2ff908c97738c3d
Reviewed-on: https://gem5-review.googlesource.com/10441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-cache: Simplify writeback for the tempBlock in recvTimingResp

When we use the tempBlock to fill-in, we have to write it back and
invalidate it at the end of current transaction. This patch simplifies
the writeback flow by treating it as a regular writeback.

Change-Id: I257be7bbff211e2832ad001a4e991daf67704485
Reviewed-on: https://gem5-review.googlesource.com/10421
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

SYS_GET_CMDLINE was declared as having 1 parameter when it is really
supposed to have two parameters.

Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8
Reported-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10022
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Add support for semihosting STDIO redirection

The Arm Semihosting layer currently assumes that the guest application
shares STDIO with gem5. This makes it hard to distinguish application
output from gem5's output and makes it impossible to redirect STDIN
when running in interactive mode. Add support for custom STDIO
redirection when instantiating the Semihosting model.

Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10021
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

style: fix amd license and style issues

Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5
Reviewed-on: https://gem5-review.googlesource.com/10463
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

gpu-compute: Cleanup the scheduler a bit

Change-Id: If2c626544f208e15c91be975dee9253126862ced
Reviewed-on: https://gem5-review.googlesource.com/10222
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-riscv: Update CSR implementations

This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. As interrupts, faults, and privilege levels are not yet
supported, there are no meaninful side effects that are implemented.
Performance counters are also not yet implemented, as they do not have
specifications. Currently they act as cycle counters.

Note that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
based on privilege will come in a future patch.

Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Reviewed-on: https://gem5-review.googlesource.com/7441
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

sim: Remove trailing dot when assigning a master's name

This patch fixes the master's name allocation in the system. The error
was occurring when a submaster was not specified in getMasterId: a
trailing separation dot was still added to the master's name.

Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10301
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base, dev: Fix port message for vnc and terminal

When running gem5, the simulator outputs the following message to
describe the ports used by the VNC server and ther terminal:

Listening for system connection on port 5900
Listening for system connection on port 3456

The code used to extract the basename ('terminal' or 'vncserver') and
print that instead of system. However, this doesn't seem to work any
more. Change the code to output the full object name instead.

Change-Id: Ib27f66a5f8ba64c7a875b4e2f26a2e2ff48db8f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10026
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit.  This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Create block insertion function

Create a block insertion function to be used when inserting
blocks. This resets the number of references to 1 (the
insertion is taken into account), sets the insertion tick,
and set secure state.

Change-Id: Ifc34cbbd1c125207ce47912d188809221c7a157e
Reviewed-on: https://gem5-review.googlesource.com/9824
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Map ID_x_EL1 registers to AArch32 version

AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts.  Those
registers must be initialized even when the highest Exception Level is
using AArch64.

Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Add support for a simple debug UART

Add a simple memory-mapped device that forwards writes to a serial
devices and treats reads as reads from the device. Unlike real UART
models, this one doesn't support interrupts.

This is useful to implement various debug devices that exist in many
systems.

Change-Id: I1e4300e4d3b70825a15d03f47d4e026941f9066c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10025
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

scons: Fix --with-ubsan/asan compilation flags

SConstruct was using an undefined env variable; this patch uses the main
Environment variable.

Change-Id: I30ab6b4bbfa6d9a71a30fb33406a799bfb476821
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10181
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-ruby: Consistent dprintf formats for issue outcomes

Change-Id: I053fc42f0d5f678f8e3434b53a0f09e00fc3e345
Reviewed-on: https://gem5-review.googlesource.com/10221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch-x86: Enable fstatfs for x86_64

Change-Id: Ic871f852c4892f2228f0d9bb3cc5cb66887d9736
Reviewed-on: https://gem5-review.googlesource.com/10201
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Create Second-Chance replacement policy

Implementation of a Second-Chance replacement policy. Similar to FIFO,
but every block is given a second chance if it has been touched.

Change-Id: Id4d52b698d0045a4914a4d848fdf9c3c00a28508
Reviewed-on: https://gem5-review.googlesource.com/9441
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: ReplacementPolicy specific replacement data

Replacement data is specific for each replacement policy, and thus
should be instantiated differently by each policy.

Touch() and reset() do not need to be aware of CacheBlk, as they
only update its ReplacementData.

Invalidate() makes replacement policies independent of cache blocks,
by removing the awareness of the valid state.

An inheritable base ReplaceableEntry class was created to allow usage
of replacement policies with any table-like structure.

Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b
Reviewed-on: https://gem5-review.googlesource.com/9421
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-x86: implement movntps/movntpd SSE insts

These are non-temporal packed SSE stores.

Change-Id: I526cd6551b38d6d35010bc6173f23d017106b466
Reviewed-on: https://gem5-review.googlesource.com/9861
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Add a ld/st microop flag for marking an access uncacheable.

This percolates down to the memory request object which will have its
"UNCACHEABLE" flag set.

Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce
Reviewed-on: https://gem5-review.googlesource.com/9881
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

arch-x86: Enable the umask system call

Change-Id: I309beb1604657e8d1807ac90458709df57f0f819
Reviewed-on: https://gem5-review.googlesource.com/10161
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

sim,cpu,mem,arch: Introduced MasterInfo data structure

With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Use block iteration in BaseSetAssoc

Use block iteration instead of numSets and assoc in print(),
cleanupRefs() and computeStats().

This makes these functions rely solely on what they are used for:
printing and calculating stats of blocks. With the addition of
Sectors an extra indirection level is added, and thus these
functions would be skipping blocks.

Change-Id: I0006f82736cce02ba3e501ffafe9236f748daf32
Reviewed-on: https://gem5-review.googlesource.com/10143
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

docs: Fix power model doxygen

Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/9981
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Use findBlock in FALRU's block access

An access must perform a block search, which is done by findBlock.

The tagHash is indexed by tags, so use extractTag instead of re-
implementing its functionality.

Change-Id: Ib5abacbc65cddf0f2d7e4440eb5355b56998a585
Reviewed-on: https://gem5-review.googlesource.com/10082
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Use secure flag in FALRU's findBlock

FALRU's findBlock() must use the secure flag to assure proper
functionality.

Change-Id: I54e9fbd3c9093b3e8043c4c6c850b74a8f1f5ec0
Reviewed-on: https://gem5-review.googlesource.com/10081
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Add ARMv8.1 TTBR1_EL2 register

This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg
table, but stil leaving it unimplemented (Accessing it through MSR/MRS
causes an exception)

Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10063
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix Unknown Instruction disassemble

Do not print the entire ExtMachInst when disassembling an Unknown
Instruction.

Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10062
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Change disassemble when MSR to UNKNOWN register

This patch changes the fault being thrown when MSR/MRS to an unknown
Misc register in AArch64. While previously the instruction was decoded
as an Unknown instruction (hence not printing any information), it is
now decoded as a FailUnimplemented and the unrecognized System register
numbers (CRn, op0...) are printed.

Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10061
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Create NRU Replacement Policy

Implementation of a Not Recently Used replacement policy.

Change-Id: I24ab3a6f1db6dcb756b869cfebb5c4bc544170e8
Reviewed-on: https://gem5-review.googlesource.com/9001
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: Fix masking in CPACR_EL1

Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit
CPACR_EL1[31] is RES0 but should be made stateful, since it allows
programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1
is removed.

Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10046
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Mask out unsupported trapped exception handling bits

Floating-point trapped exception handlings are not currently
supported in gem5, therefore the corresponding bits are RAZ/WI in
FCPR.

Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10045
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix FPEXC32_EL2 to FPEXC mapping

The mapping between MISCREG_FPEXC32_EL2 and MISCREG_FPEXC was
missing, this patch adds the mapping.

Change-Id: I2e7fa0456b73662ff9f950deb5c7e648a1bdd9ca
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10043
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Adding MiscReg Priv (EL1) global flag

This patch introduces a single global flag for setting RW access
permission at EL1 level, in either secure and non-secure mode.

Change-Id: I35df66a73349044ca996b5c04c5a2476f3a7abdf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10042
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Correct masking of cp10 and cp11 in CPACR

This patch fixes the masking of cp10 and cp11 in CPACR according to
NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state,
if EL3 is implemented and is using AArch32...", which is specified in
ARM ARM.

Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10044
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Using explicit invalidation in TLB

When setting TLB related MiscRegs, using explicit TLB regs invalidation
rather than implicit switch-case fallthrough

Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10041
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem-cache: Revamp multiple size tracking for FALRU caches

This change fixes a few bugs and refactors the mechanism by which
caches that use the FALRU tags can output statistics for multiple
cache sizes ranging from the minimum cache of interest up to the
actual configured cache size.

Change-Id: Ibea029cf275a8c068c26eceeb06c761fc53aede2
Reviewed-on: https://gem5-review.googlesource.com/9826
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>