Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 11:17:33 +0000 (12:17 +0100)]
move remaining 4 terms, use Term class
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 11:05:04 +0000 (12:05 +0100)]
derive new class Term and ProductTerm
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:48:58 +0000 (11:48 +0100)]
use Cat (again) on intermediate values
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:32:15 +0000 (11:32 +0100)]
simplify sign/term bits using Cat
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:13:59 +0000 (11:13 +0100)]
move product terms to separate module (Term)
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 09:57:23 +0000 (10:57 +0100)]
add new Terms class, get part_pts into intermediary
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 09:11:34 +0000 (10:11 +0100)]
part replaced by bit_select
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:41:41 +0000 (09:41 +0100)]
whoops, a-enabled and b-enabled swapped
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:24:20 +0000 (09:24 +0100)]
stash intermediaries for output into temp signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:13:28 +0000 (09:13 +0100)]
assignment in Cat wrong way round
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:07:36 +0000 (09:07 +0100)]
use reset_less
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:02:32 +0000 (09:02 +0100)]
whoops use already-used list
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:00:18 +0000 (09:00 +0100)]
boolean logic inversion, x = ~a & ~b & ~c ==> ~(a | b | c) then use list
of terms, use bool(), and graph size is reduced
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:49:23 +0000 (08:49 +0100)]
concatenate parts using list then Cat() - again, simplifies output
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:40:34 +0000 (08:40 +0100)]
a_enabled and b_enabled into signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:31:24 +0000 (08:31 +0100)]
add intermediate values as signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:17:24 +0000 (08:17 +0100)]
move variable to pyi file
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:14:10 +0000 (08:14 +0100)]
store mask in intermediary
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:06:20 +0000 (08:06 +0100)]
use Cat instead of for-loops: cleans up the yosys graphviz massively
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 06:56:20 +0000 (07:56 +0100)]
move typing to multiplier.pyi
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 06:45:18 +0000 (07:45 +0100)]
add partitioned multiplier/adder
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 04:24:38 +0000 (05:24 +0100)]
rename fp div classes and submodule
Luke Kenneth Casson Leighton [Fri, 16 Aug 2019 10:24:40 +0000 (11:24 +0100)]
test flipping of latchable pipeline stage between sync and comb modes
Luke Kenneth Casson Leighton [Fri, 16 Aug 2019 03:38:00 +0000 (04:38 +0100)]
update comments
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 17:23:12 +0000 (18:23 +0100)]
set up data in temporaries correctly
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 16:57:05 +0000 (17:57 +0100)]
update MaskCancellable docstrings
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 16:51:20 +0000 (17:51 +0100)]
add dynamic comb/sync mode to MaskCancellable
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 14:26:32 +0000 (15:26 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 14 Aug 2019 13:39:10 +0000 (14:39 +0100)]
debugging feedback pipe
Luke Kenneth Casson Leighton [Mon, 12 Aug 2019 02:25:14 +0000 (03:25 +0100)]
fix syntax errors in fmac conversion
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 12:35:24 +0000 (13:35 +0100)]
increase number of fpmul operands to 3
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 12:34:54 +0000 (13:34 +0100)]
restore old Multi-in/out behaviour
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 07:42:47 +0000 (08:42 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 06:01:00 +0000 (07:01 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 11:59:48 +0000 (12:59 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 10:58:19 +0000 (11:58 +0100)]
{x}{y} in verilog means x occurrences of y
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 10:18:09 +0000 (11:18 +0100)]
{x}{y} in verilog means x occurrences of y
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 07:53:28 +0000 (08:53 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 06:29:09 +0000 (07:29 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 11:26:13 +0000 (12:26 +0100)]
route-back experimentation
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 02:20:56 +0000 (03:20 +0100)]
add experimental feedback pipe test
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 00:15:16 +0000 (01:15 +0100)]
respect Ready/Valid signalling (stall capability) in MaskCancellable
this will be needed for pipeline bypassing
Luke Kenneth Casson Leighton [Tue, 6 Aug 2019 11:19:33 +0000 (12:19 +0100)]
add mask cancellation to FPDIV and to fpmux unit test
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:37:13 +0000 (08:37 +0100)]
multiply mask width for concurrent pipeline
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:36:41 +0000 (08:36 +0100)]
hack to set predicate mask (if it exists)
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:36:11 +0000 (08:36 +0100)]
whoops inherit from MaskCancellable not SimpleHandshake
Luke Kenneth Casson Leighton [Sun, 4 Aug 2019 11:34:38 +0000 (12:34 +0100)]
added maskwidth and dynamic use of MaskCancellable, no "bugs", still to
confirm if it works
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 22:39:12 +0000 (23:39 +0100)]
only pass on the uncancelled mask bits
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 22:29:54 +0000 (23:29 +0100)]
test actual cancellation mask (works)
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 21:29:32 +0000 (22:29 +0100)]
add 2 extra stages to cancel test
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 09:49:31 +0000 (10:49 +0100)]
give names to muxer submodules
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 09:38:51 +0000 (10:38 +0100)]
pass on stop bits as well
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 09:28:37 +0000 (10:28 +0100)]
concatenate mask bits on fan-in, split on fan-out
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 05:17:26 +0000 (06:17 +0100)]
add maskable in/out cancellable test
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 04:37:40 +0000 (05:37 +0100)]
add in cancelmask
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 01:19:51 +0000 (02:19 +0100)]
explain comments
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 01:10:04 +0000 (02:10 +0100)]
generate mask il
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 01:06:22 +0000 (02:06 +0100)]
mask sort-of working as long as "ready" is always true
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 00:38:09 +0000 (01:38 +0100)]
add mask to NextControl
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 00:32:42 +0000 (01:32 +0100)]
add mask to PrevControl
Luke Kenneth Casson Leighton [Fri, 2 Aug 2019 00:50:40 +0000 (01:50 +0100)]
add first draft MaskCancellable pipe class
Luke Kenneth Casson Leighton [Fri, 2 Aug 2019 00:50:22 +0000 (01:50 +0100)]
update to nmutil Memory API
Luke Kenneth Casson Leighton [Fri, 2 Aug 2019 00:49:55 +0000 (01:49 +0100)]
update test
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 22:54:52 +0000 (23:54 +0100)]
whitespace
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 07:48:29 +0000 (08:48 +0100)]
move priority picker from soc to nmutil
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 07:42:16 +0000 (08:42 +0100)]
add copy of inout mux pipe
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 07:41:31 +0000 (08:41 +0100)]
whitespace
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:35:28 +0000 (02:35 +0100)]
whitespace
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:35:15 +0000 (02:35 +0100)]
remove more redundant modules
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:25:37 +0000 (02:25 +0100)]
comment; remove unneeded code
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:23:10 +0000 (02:23 +0100)]
remove i_specfn and o_specfn from FP*MuxInOut, use self.alu.ispec() and ospec()
every class has an alu object, the pipe specs are the same for all use-cases
so....
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:10:59 +0000 (02:10 +0100)]
correct library name
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:06:56 +0000 (02:06 +0100)]
add copyright notice
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 01:05:51 +0000 (02:05 +0100)]
update comments
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 00:02:40 +0000 (01:02 +0100)]
add bugreport crossreference
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 00:02:05 +0000 (01:02 +0100)]
add bugreport link
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:57:19 +0000 (00:57 +0100)]
add to float2int unit tests
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:57:05 +0000 (00:57 +0100)]
adjust float2int range to cope with larger-to-smaller
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:32:35 +0000 (00:32 +0100)]
use PipeModBase in float2int fcvt
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:24:14 +0000 (00:24 +0100)]
use alternative logic for roundz detect exponent increase
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:19:26 +0000 (00:19 +0100)]
remove unneeded modules
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:18:39 +0000 (00:18 +0100)]
comment
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:16:27 +0000 (00:16 +0100)]
convert to use unittest in fcvt
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:13:51 +0000 (00:13 +0100)]
increase number of test runs
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:12:10 +0000 (00:12 +0100)]
whoops broke downconvert rounding
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 23:03:29 +0000 (00:03 +0100)]
tidyup of fcvt downsize
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 22:54:28 +0000 (23:54 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 22:54:06 +0000 (23:54 +0100)]
reorg / tidyup fcvt upsize.py
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 22:41:31 +0000 (23:41 +0100)]
rename FPADDBaseData to FPBaseData and move to separate module
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 21:40:18 +0000 (22:40 +0100)]
cleanup
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 21:32:56 +0000 (22:32 +0100)]
move FPPackData to separate module
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 21:23:42 +0000 (22:23 +0100)]
update comments/clarify
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 21:05:43 +0000 (22:05 +0100)]
tidyup of FPAdd Align
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:55:15 +0000 (21:55 +0100)]
remove unneeded modules
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:52:05 +0000 (21:52 +0100)]
update comments
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:51:40 +0000 (21:51 +0100)]
update comments
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:49:15 +0000 (21:49 +0100)]
update comments
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:39:13 +0000 (21:39 +0100)]
move assignment into out_do_z condition
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:31:33 +0000 (21:31 +0100)]
add __init__.py files
Luke Kenneth Casson Leighton [Wed, 31 Jul 2019 20:27:58 +0000 (21:27 +0100)]
remove unneeded imports, update copyright notice