Samuel Pitoiset [Wed, 6 Apr 2016 14:19:37 +0000 (16:19 +0200)]
nvc0: enable RGB10_A2UI format on GK104
No clue why this was not enabled by default before, maybe because
the SULDP conversion was wrong. Anyway, this helps in fixing all
rgb10_a2ui piglit tests.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sat, 9 Apr 2016 18:15:13 +0000 (20:15 +0200)]
nvc0: shift address with blocksize for image buffers
This fixes a bunch of dEQP image buffers related tests.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sat, 9 Apr 2016 18:31:45 +0000 (20:31 +0200)]
nvc0: fix address offset when images have multiple levels
This fixes arb_shader_image_load_store-level.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 5 Apr 2016 11:53:56 +0000 (13:53 +0200)]
nvc0: bind images on 3D shaders for Kepler
Similar to surfaces validation for compute shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Thu, 7 Apr 2016 22:56:54 +0000 (00:56 +0200)]
nvc0: bind images on compute shaders for Kepler
Old surfaces validation code will be removed once images are completely
done for Fermi/Kepler, that explains why I only disable it for now.
This also introduces nvc0_get_surface_dims() which computes correct
dimensions regarding the given target.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 22 Mar 2016 17:00:09 +0000 (18:00 +0100)]
nvc0: reserve an area for surfaces info in the driver constbuf
To process surfaces coordinates from the codegen part, and because
some information like the format is not always available (eg. when
writeonly is used), we have to stick some surfaces data in the
driver constbuf. This is especially true for OpenCL because we don't
know the format at shader compile time.
This bumps the size of each shader area from 1K to 2K.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 18 Mar 2016 10:11:24 +0000 (11:11 +0100)]
nvc0: add preliminary support for images
This implements set_shader_images() and resource invalidation for
images. As OpenGL requires at least 8 images, we are going to expose
this minimum value even if this might be raised for Kepler, but this
limit is mainly for Fermi because the hardware only accepts 8 images.
Based on original patch by Ilia Mirkin.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 26 Apr 2016 16:14:05 +0000 (18:14 +0200)]
gk110/ir: add emission for (a OP b) OP c
This is pretty similar to NVC0 except that offsets have changed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Tue, 26 Apr 2016 16:12:59 +0000 (18:12 +0200)]
nvc0/ir: fix wrong emission of (a OP b) OP c
The third source must be emitted at offset 49 instead of 17 and the
not modifier is at 52 instead of 20. If you look a bit above in
emitLogicOp() you will see that the dest is emitted at 17 which
confirms that src(2) is obviously wrong.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Jose Fonseca [Mon, 18 Apr 2016 15:55:44 +0000 (16:55 +0100)]
scons: Support Clang on Windows.
- Introduce 'gcc_compat' env flag, for all compilers that define __GNUC__,
(which includes Clang when it's not emulating MSVC.)
- Clang doesn't support whole program optimization
- Disable enumerator value warnings (not sure why Clang warns about them,
as my understanding is that MSVC promotes enums to unsigned ints
automatically.)
This is not enough to build with Clang + AddressSanitizer though. More
follow up changes will be required for that.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Mon, 18 Apr 2016 11:08:35 +0000 (12:08 +0100)]
gallium: Include intrin.h instead of defining ourselves.
More portable, particularly when building with Clang, which implements
all MSVC intrisincs in its own intrin.h, but doesn't actually support
`#pragma instrinsic`.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Mon, 18 Apr 2016 10:47:07 +0000 (11:47 +0100)]
scons: Whenever possible decide what to do based on platform and not compiler.
Because compilers like GCC and Clang are effectively available everywhere
so their presence/absence is seldom conclusive.
Furthermore, all compilers we use now have stdint.h.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Mon, 18 Apr 2016 10:41:11 +0000 (11:41 +0100)]
scons: Move fallback HAVE_* definitions to headers.
These were being defined in SCons, but it's not practical:
- we actually need to include Gallium headers from external source trees, with
completely disjoint build infrastructure, and it's unsustainable to
replicate the HAVE_xxx checks or even hard-coded defines across
everywhere.
- checking compiler version via command line doesn't really work due to
Clang essentially being like a cameleon which can fake either GCC or
MSVC
There's no change for autoconf.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Juha-Pekka Heikkila [Fri, 22 Apr 2016 06:45:10 +0000 (09:45 +0300)]
nir: Add missing break into switch in construct_value()
There seemed to be missing one break in nested switchcases.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bas Nieuwenhuizen [Thu, 21 Apr 2016 18:34:04 +0000 (20:34 +0200)]
radeonsi: Fix memory leak in error path.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Oded Gabbay [Tue, 26 Apr 2016 10:47:28 +0000 (13:47 +0300)]
radeonsi: fix build error because of missing param
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Oded Gabbay [Tue, 19 Apr 2016 21:17:45 +0000 (00:17 +0300)]
r600g: use do_endian_swap in texture swapping function
For some texture formats we need to take "do_endian_swap" into account
when configuring their swizzling.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Oded Gabbay [Thu, 21 Apr 2016 12:51:40 +0000 (15:51 +0300)]
r600g: use do_endian_swap in color swapping functions
For some formats we need to take "do_endian_swap" into account when
configuring swapping for color buffers.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Oded Gabbay [Tue, 19 Apr 2016 13:25:23 +0000 (16:25 +0300)]
r600g: set endianess of 16/32-bit buffers according to do_endian_swap
This patch modifies r600_colorformat_endian_swap(), so for 16-bit and for
32-bit buffers, the endianess configuration will be determined not only
by the color/texture format, but also by the do_endian_swap parameter.
The only exception is for array formats, which are always set to not do
swapping, because for them gallium sets an alias based on the machine's
endianess.
v4:
V_0280A0_COLOR_16_16 and V_0280A0_COLOR_16_16_FLOAT should be set to
8IN16 because the bytes inside need to be swapped even for array formats.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Oded Gabbay [Mon, 21 Mar 2016 21:46:15 +0000 (23:46 +0200)]
r600g/radeonsi: send endian info to format translation functions
Because r600 GPUs can't do swap in their DB unit, we need to disable
endianess swapping for textures that are handled by DB.
There are four format translation functions in r600g driver:
- r600_translate_texformat
- r600_colorformat_endian_swap
- r600_translate_colorformat
- r600_translate_colorswap
This patch adds a new parameters to those functions, called
"do_endian_swap". When running in a big-endian machine, the calling
functions will check whether the texture/color is handled by DB -
"rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will
send FALSE through this parameter. Otherwise, they will send TRUE.
The translation functions, in specific cases, will look at this parameter
and configure the swapping accordingly.
v4:
evergreen_init_color_surface_rat() is only used by compute and don't
handle DB surfaces, so just sent hard-coded FALSE to translation
functions when called by it.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sun, 24 Apr 2016 17:15:59 +0000 (13:15 -0400)]
glsl: add ability to use essl 3.20
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sun, 24 Apr 2016 17:24:25 +0000 (13:24 -0400)]
main: select ES3.2 version when all extensions are available
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 26 Apr 2016 00:45:00 +0000 (10:45 +1000)]
tgsi: pass a shader type to the machine create and clean up.
There was definitely bugs here mixing up the PIPE_ and TGSI_ defines,
hopefully they didn't cause any problems, since mostly it was special
cases for GEOMETRY.
This clarifies at shader machine create what type of shader this
machine will execute. This is needed also for compute shaders where
we don't want to allocate inputs/outputs.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 25 Apr 2016 23:42:38 +0000 (09:42 +1000)]
gallium/tgsi: move tgsi_exec.h header out of draw_context.h
It gets annoying that changing the tgsi exec rebuilds the state
tracker unnecessarily. Putting this include into draw_gs.h which
uses it causes a lot less rebuilds.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Roland Scheidegger [Tue, 26 Apr 2016 02:53:01 +0000 (04:53 +0200)]
gallivm: make sampling more robust against bogus coordinates
Some cases (especially these using fract for coord wrapping) did not handle
NaNs (or Infs) correctly - the following code assumed the fract result
could not be outside [0,1], but if the input is a NaN (or +-Inf) the fract
result was NaN - which then could produce out-of-bound offsets.
(Note that the explicit NaN behavior changes for min/max on x86 sse don't
result in actual changes in the generated jit code, but may on other
architectures. Found by looking through all the wrap functions.)
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94955
No piglit changes.
(v2: fix min/max typo in coord_mirror, add comment)
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Dave Airlie [Mon, 25 Apr 2016 23:35:49 +0000 (09:35 +1000)]
radeonsi: fix missing include for Elements.
Since u_blitter.h no longer defines this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Mon, 25 Apr 2016 22:15:25 +0000 (00:15 +0200)]
nvc0: bump the amount of shared memory per MP on Maxwell
According to the CUDA compute capability version, GM10x can expose
64KB of shared memory while GM20x can use 96KB.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Mon, 25 Apr 2016 21:59:44 +0000 (07:59 +1000)]
r600: fix missing include for Elements macro
This got removed from u_blitter.h and we were taking it from
there, this should just move to ARRAY_SIZE eventually.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Mon, 25 Apr 2016 20:45:17 +0000 (22:45 +0200)]
gm107/ir: s/invalid load/invalid store/
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Sun, 24 Apr 2016 20:41:12 +0000 (16:41 -0400)]
freedreno/a3xx: remove unused fxn
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 24 Apr 2016 18:01:58 +0000 (14:01 -0400)]
freedreno/ir3: convert over to ralloc
The home-grown heap scheme (which is ultra-simple but probably not good
to always allocate and memset such a chunk of memory up front) was a
remnant of fdre (where the ir originally came from). But since we have
ralloc in mesa, lets just use that instead.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 25 Apr 2016 17:16:10 +0000 (13:16 -0400)]
mesa/st: log some additional invalid-fbo cases
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Rob Clark [Mon, 25 Apr 2016 15:47:21 +0000 (11:47 -0400)]
freedreno: honor handle->offset
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 25 Apr 2016 12:24:43 +0000 (08:24 -0400)]
freedreno: disallow cat4 immed src
Normally this would never happen (constant-propagation in NIR would
eliminate the instruction), except it does happen for 'undef' which
we turn into immed 0.0 for bookkeeping purposes.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 25 Apr 2016 19:38:18 +0000 (15:38 -0400)]
freedreno/a4xx: add render-target formats
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 25 Apr 2016 19:36:55 +0000 (15:36 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 25 Apr 2016 18:22:45 +0000 (14:22 -0400)]
freedreno: reduce line width for deqp further
See
a7eb12d0.. but that wasn't restrictive enough. Fixes
dEQP-GLES3.functional.rasterization.primitives.line_strip_wide, and
similar
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 23 Apr 2016 13:03:28 +0000 (09:03 -0400)]
freedreno/ir3: fix sin/cos
We seem to need range reduction to get sane results. Fixes glmark2
jellyfish bench, and a whole bunch of
dEQP-GLES3.functional.shaders.builtin_functions.precision.{sin,cos,tan}.*
v2: squashed in android build fixes from Rob Herring
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Tue, 29 Mar 2016 08:32:52 +0000 (01:32 -0700)]
i965: Unroll SIMD16 DDY_FINE on Sandybridge.
This fixes 10 dEQP-GLES3 subtests:
dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*.
Matt noticed that our Piglit tests for this use even numbered registers,
while the failing dEQP tests use odd numbered registers. We believe
that it works for even numbered registers, but not otherwise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Mon, 25 Apr 2016 16:13:32 +0000 (10:13 -0600)]
docs: update the instructions for getting a git account
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Mon, 25 Apr 2016 19:28:56 +0000 (13:28 -0600)]
docs: update link to Intel's graphics website
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jordan Justen [Mon, 25 Apr 2016 02:38:03 +0000 (19:38 -0700)]
mesa/gles: Allow format GL_RED to be used with MESA_FORMAT_R_UNORM
If the bound framebuffer has a format of MESA_FORMAT_R_UNORM, then
IMPLEMENTATION_COLOR_READ_FORMAT will return GL_RED. This change
applies to OpenGLES contexts where additional restrictions are placed
on the formats that are allowed to be supported.
Fixes OpenGLES 3.1 CTS tests:
* ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC16
* ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC16Linear
* ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC32F
* ES31-CTS.texture_border_clamp.sampling_texture.Texture2DDC32FLinear
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Charmaine Lee [Fri, 22 Apr 2016 23:06:32 +0000 (16:06 -0700)]
svga: eliminiate unnecessary constant buffer updates
Currently if the texture binding is changed, emit_fs_consts()
is triggered to update texture scaling factor for
rectangle texture or texture buffer size in the constant buffer.
But the update is only relevant if the texture binding includes
a rectangle texture or a texture buffer.
To eliminate the unnecessary constant buffer updates due to other texture
binding changes, a new flag SVGA_NEW_TEXTURE_CONSTS will be used
to trigger fragment shader constant buffer update when a rectangle texture
or a texture buffer is bound.
With this patch, the number of constant buffer updates in Lightsmark2008
reduces from hundreds per frame to about 28 per frame.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Thu, 21 Apr 2016 15:28:26 +0000 (08:28 -0700)]
svga: mark the texture dirty for write transfer map only
Instead of unconditionally mark the texture subresource dirty at transfer map,
we'll set the dirty bit for write transfer only.
Tested with lightsmark2008 and glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Wed, 20 Apr 2016 01:12:17 +0000 (18:12 -0700)]
svga: fix assert with PIPE_QUERY_OCCLUSION_PREDICATE for non-vgpu10
With this patch, when running in hardware version 11, we'll use
SVGA3D_QUERYTYPE_OCCLUSION query type for PIPE_QUERY_OCCLUSION_PREDICATE
and return TRUE if samples-passed count is greater than 0.
Fixes glretrace/solidworks2012_viewport running in hardware version 11.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Fri, 15 Apr 2016 00:33:32 +0000 (17:33 -0700)]
svga: minimize surface flush
Currently, we always do a surface flush when we try to establish
a synchronized write transfer map. But if the subresource has not
been modified, we can skip the surface flush. In other words,
we only need to do a surface flush if the to-be-mapped subresource
has been modified in this command buffer.
With this patch, lightsmark2008 shows about 15% performance improvement.
Reviewed-by: Brian Paul <brianp@vmware.com>
Frederic Devernay [Mon, 25 Apr 2016 16:39:43 +0000 (10:39 -0600)]
glapi: fix _glapi_get_proc_address() for mangled function names
In the dispatch table, all functions are stored without the "m" prefix.
Modify code so that OSMesaGetProcAddress works both with gl and mgl
prefixes. Similar to
https://lists.freedesktop.org/archives/mesa-dev/2015-September/095251.html
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94994
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 25 Apr 2016 15:38:05 +0000 (09:38 -0600)]
util/blitter: use ARRAY_SIZE macro
And remove local definition of Elements() macro.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Mon, 25 Apr 2016 15:34:40 +0000 (09:34 -0600)]
svga: s/Elements/ARRAY_SIZE/
Standardize on the later macro rather than a mix of both.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Fri, 15 Apr 2016 21:58:05 +0000 (15:58 -0600)]
svga: whitespace and formatting fixes in svga_pipe_rasterizer.c
Brian Paul [Fri, 15 Apr 2016 21:57:55 +0000 (15:57 -0600)]
svga: whitespace and formatting fixes in svga_pipe_depthstencil.c
Brian Paul [Fri, 15 Apr 2016 21:54:15 +0000 (15:54 -0600)]
svga: whitespace and formatting fixes in svga_pipe_sampler.c
Brian Paul [Fri, 15 Apr 2016 18:14:27 +0000 (12:14 -0600)]
gallium/util: initialize pipe_framebuffer_state to zeros
To silence a valgrind uninitialized memory warning.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94955
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Thu, 14 Apr 2016 23:23:30 +0000 (17:23 -0600)]
util/cache: add comments, fix formatting
Kenneth Graunke [Sat, 9 Apr 2016 01:49:22 +0000 (18:49 -0700)]
i965: Mark URB reads as volatile.
They can be affected by URB writes.
In the upcoming scalar TCS backend, this prevents read-modify-write
cycles from being broken by CSE removing reads.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Kenneth Graunke [Mon, 11 Apr 2016 04:28:37 +0000 (21:28 -0700)]
i965: Make a few tessellation related functions non-static.
Also, move them to brw_shader.cpp so they're in a location for code
used by both the vec4 and fs worlds.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Brian Paul [Fri, 15 Apr 2016 21:30:34 +0000 (15:30 -0600)]
svga: separate HUD counters for state objects
Count depth/stencil, blend, sampler, etc. state objects separately
but just report the sum for the HUD. This change lets us use gdb to
see the breakdown of state objects in more detail.
Also, count sampler views too.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Robert Foss [Thu, 21 Apr 2016 21:49:20 +0000 (17:49 -0400)]
st/omx: Fix resource leak on OMX_ErrorNone
Avoid leaking buffer allocated for task if an error has occured.
Coverity id:
1213929
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Jonathan Gray [Sat, 23 Apr 2016 07:27:58 +0000 (17:27 +1000)]
isl: remove ffs function that conflicts with system headers
Remove a wrapper around __builtin_ffs that conflicts with system
headers on OpenBSD and perhaps elsewhere:
isl_priv.h:44: error: conflicting types for 'ffs'
v2: include strings.h to ensure prototype is found
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:16 +0000 (04:00 +0300)]
gallium: use unreachable instead of asserts
Avoids warnings in release builds.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:15 +0000 (04:00 +0300)]
anv: fix warnings in release build
Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:14 +0000 (04:00 +0300)]
isl: fix warnings in release build
Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:13 +0000 (04:00 +0300)]
spirv: fix warning in release build
Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:12 +0000 (04:00 +0300)]
gallium: fix warnings in release build
Mark variables MAYBE_UNUSED to avoid unused-but-set-variable warnings
in release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:11 +0000 (04:00 +0300)]
glsl: fix warning in release build
Mark variable MAYBE_UNUSED to avoid unused-but-set-variable warning in
release build.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Grazvydas Ignotas [Sat, 16 Apr 2016 01:00:10 +0000 (04:00 +0300)]
util: add MAYBE_UNUSED for config dependent variables
This is mostly for variables that are only used in asserts and cause
unused-but-set-variable warnings in release builds. Could just use
UNUSED directly, but MAYBE_UNUSED should be less confusing and is
similar to what the Linux kernel has.
And yes __attribute__((unused)) can be used on variables on both GCC 4.2
(oldest supported by mesa) and clang 3.0 (just some random old version,
not sure what's the minimum for mesa).
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Hans de Goede [Thu, 21 Apr 2016 13:43:51 +0000 (15:43 +0200)]
nouveau: codegen: combineLd/St do not combine indirect loads
combineLd/St would combine, i.e. :
st u32 # g[$r2+0x0] $r2
st u32 # g[$r2+0x4] $r3
into:
st u64 # g[$r2+0x0] $r2d
But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders
This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Sun, 24 Apr 2016 15:40:12 +0000 (11:40 -0400)]
freedreno/ir3: relax restriction in grouping
Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw
Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 24 Apr 2016 15:39:54 +0000 (11:39 -0400)]
freedreno/ir3: fix small memory leak
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 22 Apr 2016 22:39:10 +0000 (18:39 -0400)]
freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always. For
example, in a sam(w) which only writes the 4th component.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 19 Apr 2016 13:02:23 +0000 (09:02 -0400)]
freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions. But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures. Work around this
setting up a second texture state and using that to sample alpha
separately.
This way, srgb->linear conversion happens in hw *prior* to
interpolation.
This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 22 Apr 2016 19:39:35 +0000 (15:39 -0400)]
Revert "freedreno/a4xx: lower srgb in shader for astc textures"
Better workaround in the following patch.
This reverts commit
899bd63acefd49a668e11c42d2ad92fa55aa157d.
Rob Clark [Fri, 22 Apr 2016 21:04:20 +0000 (17:04 -0400)]
freedreno/a4xx: blend state no longer depends on fb state
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Marek Olšák [Sun, 24 Apr 2016 13:13:28 +0000 (15:13 +0200)]
Revert "st/dri: add 32-bit RGBX/RGBA formats"
This reverts commit
ccdcf91104a5f07127b5b8d8570b5c4bbcf86647.
It breaks most KDE apps, because DRI doesn't support the RGBA component
ordering.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95071
Jonathan Gray [Sat, 23 Apr 2016 07:42:38 +0000 (17:42 +1000)]
genxml: use PYTHON3
Allows the build to work when the python3 binary is not "python3".
v2: remove x bit from the script at Emil's suggestion
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nanley Chery [Mon, 11 Apr 2016 23:33:21 +0000 (16:33 -0700)]
i965/tex_image: Flush certain subnormal ASTC channel values
When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
required to flush to zero the UNORM16 channel values that would be
denormalized. This is specifically required for the values: 1, 2, and 3.
Fixes the 14 failing tests in:
dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.*
v2: Split out flushing function (Kristian Høgsberg)
v3: Map with READ instead of INVALIDATE (Kenneth Graunke)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jonathan Gray [Sat, 23 Apr 2016 07:39:02 +0000 (17:39 +1000)]
configure.ac: search for and set PYTHON3
src/intel/genxml/gen_pack_header.py requires python3.
v2: check for python3.5 as well
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 1 Apr 2016 13:21:17 +0000 (16:21 +0300)]
i965/blorp: Enable for buffer resolves
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 1 Apr 2016 13:18:27 +0000 (16:18 +0300)]
i965/blorp: Enable for normal color clears
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 22 Apr 2016 06:44:13 +0000 (09:44 +0300)]
i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+
This is equivalent of
73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2
for blorp.
v2 (Ken): No need to call _mesa_format_has_color_component() now
that the number of components is gotten from
_mesa_base_format_component_count().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 22 Apr 2016 08:07:06 +0000 (11:07 +0300)]
mesa/formats: Take luminance into account in component count
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Topi Pohjolainen [Fri, 22 Apr 2016 13:14:10 +0000 (16:14 +0300)]
i965/blorp: Do not trigger re-emission of base state address
In case blorp needs to configure it will be just as if render or
compute pipeline had configured it.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 15 Apr 2016 21:10:40 +0000 (00:10 +0300)]
i965/blorp: Reconfigure base state address only if needed
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 22 Apr 2016 10:43:39 +0000 (13:43 +0300)]
i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 22 Apr 2016 08:48:56 +0000 (01:48 -0700)]
i965: Make all atoms to track BRW_NEW_BLORP by default
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
Topi Pohjolainen [Fri, 22 Apr 2016 08:25:18 +0000 (11:25 +0300)]
i965: Introduce state flag for blorp
In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw. However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them. Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.
Instead, we introduce a BRW_NEW_BLORP flag. This should be set on any
atom which emits a packet that BLORP also emits. When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.
This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.
To start, we assume that all packets need to be re-emitted. This is the
safest approach and closest to the existing code's behavior. Many of
these are obviously not required, and can be dropped in subsequent
patches.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 22 Apr 2016 13:01:12 +0000 (16:01 +0300)]
i965/blorp/gen6: Use normal base state address setup
This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Fri, 22 Apr 2016 09:33:26 +0000 (12:33 +0300)]
i965: Remove pointers to non-existing atoms
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tom Stellard [Fri, 15 Apr 2016 23:42:10 +0000 (23:42 +0000)]
radeonsi: Implement ddx/ddy on VI using ds_bpermute
The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads. These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.
DDX BEFORE: | DDX AFTER:
|
v_mbcnt_lo_u32_b32_e64 v2, -1, 0 | v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2 | v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2 | v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2 | v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2 | ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1 | ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0 | s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0) |
v_or_b32_e32 v0, 1, v2 |
v_lshlrev_b32_e32 v0, 2, v0 |
ds_read_b32 v1, v3 |
ds_read_b32 v0, v0 |
s_waitcnt lgkmcnt(0) |
|
LDS: 1 blocks | LDS: 0 blocks
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Fri, 15 Apr 2016 22:53:38 +0000 (22:53 +0000)]
radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid
We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.
v2:
- Only do this with LLVM 3.8 and newer.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Mon, 18 Apr 2016 18:33:43 +0000 (14:33 -0400)]
radeonsi: Set range metadata on calls to llvm.SI.tid
The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Mon, 18 Apr 2016 17:10:10 +0000 (13:10 -0400)]
radeonsi: Create a helper function for computing the thread id
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nanley Chery [Wed, 13 Apr 2016 00:34:49 +0000 (17:34 -0700)]
i965: Disable KHR_texture_compression_astc_hdr on Gen9
Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.
With this change, we are no longer failing the 14 tests from:
dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tim Rowley [Tue, 12 Apr 2016 23:24:18 +0000 (17:24 -0600)]
swr: [rasterizer memory] Constify load tiles
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 13 Apr 2016 01:28:50 +0000 (19:28 -0600)]
swr: [rasterizer core] CompleteDrawContext changes for gcc
Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 6 Apr 2016 21:23:14 +0000 (15:23 -0600)]
swr: [rasterizer] Small cleanups
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 6 Apr 2016 18:30:14 +0000 (12:30 -0600)]
swr: [rasterizer scripts] Knob scripts tweaks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 5 Apr 2016 22:33:02 +0000 (16:33 -0600)]
swr: [rasterizer] Interpolation utility functions
v2: use _mm_cmpunord_ps for vIsNaN
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 5 Apr 2016 02:00:13 +0000 (20:00 -0600)]
swr: [rasterizer core] TemplateArgUnroller
Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.
This allows the template argument unroller to easily be extended to enums.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 4 Apr 2016 23:16:35 +0000 (17:16 -0600)]
swr: [rasterizer core] Arena: make most allocated blocks the same size
Reduces sorting cost
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>