i965: Reupload push and pull constants when we get new shader image unit state.

Fixes several of the
"dEQP-GLES31.functional.image_load_store*load_store*single_layer" dEQP
tests that use image formats we implement using untyped surface
messages.

Cc: mesa-stable@lists.freedesktop.org
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: fix MAX_COMPUTE_SHARED_SIZE constant value

MAX_COMPUTE_SHARED_SIZE should be set to 32768. This fixes a regression
introduced in be27f77 (mesa: do not use a constant for
MAX_COMPUTE_SHARED_SIZE).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94139
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nv50/ir: add missing SV_TID and SV_CTAID sysvals on GM107

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: add MEMBAR emission for GM107

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs: document MESA_GLES_VERSION_OVERRIDE envvar

v2: Removed reference to FC not being an allowed suffix (Brian Paul)

Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: fix pipe_grid_info initializer

Fixes MSVC build error which doesn't allow empty initializers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

trace: add all compute related functions

Changes from v3:
 - dump the TGSI compute program

Changes from v2:
 - remove use of MALLOC()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: implement limits for ARB_compute_shader

According to the spec, this also increases the following minimum values:
 - MAX_COMBINED_TEXTURE_IMAGE_UNITS     96 (6*16), was 80
 - MAX_UNIFORM_BUFFER_BINDINGS          72 (6*12), was 60

ARB_compute_shader is not enabled by default because images support is
still not implemented yet. If you want to use it you need to set
MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader.

Changes from v2:
 - make use of the new PIPE_CAP_SHADER_SUPPORTED_IRS cap instead of
   enabling the extension when PIPE_CAP_COMPUTE is enabled.
 - query for PIPE_CAP_COMPUTE first
 - s/shader_supported_irs/compute_supported_irs/
 - disable ARB_compute_shader and add a comment which explains why

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add compute program dispatch callbacks

This state tracker implements DispatchCompute() and DispatchComputeIndirect().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add state validation for compute shaders

This binds atomics, constants, samplers, ssbos, textures and ubos.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add mappings for compute shader sysvals

LOCAL_INVOCATION_ID, WORK_GROUP_ID and NUM_WORK_GROUPS are respectively
mapped to THREAD_ID, BLOCK_ID and GRID_SIZE.

Changes from v2:
 - add assertions in st_translate_program()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: keep track of shared memory declarations

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add intrinsics for shared variables

This adds GLSL intrinsics for load/store and atomic operations.

Changes from v2:
 - use PROGRAM_MEMORY instead of PROGRAM_BUFFER

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add conversion for compute shaders

According to the spec, there are no predefined inputs nor any
fixed-function outputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add compute shader states

Changes from v2:
 - use as much common code as possible (eg. st_basic_variant)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add a second pipeline for compute

Compute needs a new and different validation path.

Changes from v2:
 - make use of unreachable() instead of assert() when the pipeline is
   invalid
 - move the st_pipeline enumeration to st_context.h instead of st_api.h

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi/ureg: add shared variables support for compute shaders

This introduces TGSI_FILE_MEMORY for shared, global and local memory.
Only shared memory is currently supported.

Changes from v2:
 - introduce TGSI_FILE_MEMORY

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS

This cap indicates the supported representations of programs. It should
be a mask of pipe_shader_ir bits. It will allow to enable
ARB_compute_shader if the underlying driver supports TGSI.

Changes from v2:
 - improve description of PIPE_SHADER_CAP_SUPPORTED_IRS

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add indirect compute parameters to pipe_grid_info

Like indirect draw, we need to store a resource and an offset that
needs to be 4 byte aligned. When indirect is used, the size of the
grid (in blocks) is stored with three 32-bit integers.

Changes from v2:
 - s/most values/block sizes/

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: add a new interface for pipe_context::launch_grid()

This introduces pipe_grid_info which contains all information to
describe a launch_grid call. This will be used to implement indirect
compute in the same fashion as indirect draw.

Changes from v2:
 - correctly initialize pipe_grid_info for nv50/nvc0

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium/cso: add support for compute shaders

Changes from v2:
 - removed cso_{save,restore}_compute_shader() functions and the
   compute_shader_saved variable because disabling compute shaders for
   meta ops is not currently needed

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add PROGRAM_MEMORY

This will be used for shared, global and local memory areas.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: store shared size in gl_compute_program

The size of shared variables needs to be stored in gl_compute_program
in order to set up pipe_compute_state::req_local_mem.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: do not use a constant for MAX_COMPUTE_SHARED_SIZE

This will allow to query the underlying drivers for the maximum
total storage size of all variables declared as <shared> with
PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: make compute maximums reflect driver-provided values

Looks like the various max's were never plumbed through.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Add means for limiting color resolves

Until now there has been only one type of color buffer that needs
to resolved - namely single sampled fast clear. As even the
sampler engine in GPU doesn't understand the associated meta data,
the color values need to be always resolved prior to reading them.

From SKL onwards there is new scheme supported called the lossless
compression of single sampled color buffers. This is something that
is understood by the sampling engine and therefore resolving of
these types of buffers is not necessary before sampling.
This patch adds means to make the distinction when considering if
resolve is needed.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Refactor resolving of auxiliary mode

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Don't try to create aux buffer for non-msrt aux-buffer

In addition to simply calling miptree_create() the higher level
call intel_miptree_create() also considers if the buffer should
be associated with an auxiliary buffer based on the given format.

Here we are allocating an auxiliary buffer which in turn has such
format that would mislead intel_miptree_create_layout() later on
to try to associate the auxiliary buffer with an auxiliary buffer.
To prevent this the actual buffer creation logic was split out
into its own function. Lets invoke that instead.

v2 (Ben): Do not signal msaa layout with explicit argument but
          using layout_flags instead.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Rename optimizer debug 00 filename

This allows ls, and scripts to get the file names in the correct order of
optimization.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Make brw_clear_cache NULL out stale program pointers.

The L3 partitioning code tries to look at all programs - both render
programs (VS/TCS/TES/GS/FS) and compute (CS).

After calling brw_clear_cache, all prog_data pointers are invalid and
point to freed data.  The intention was that flagging the dirty bits for
all programs would cause the next draw call to re-run the atoms for each
program stage, uploading new programs and installing new, valid pointers.

However, this doesn't quite work in our new multi-pipeline world.  When
drawing or dispatching a compute workload, we only consider the programs
for the appropriate pipeline: drawing sets up VS/TCS/TES/GS/FS, but not
CS, and vice versa.  This leaves pointers dangling a bit longer than
intended.

The L3 configuration code tries to inspect the prog_data for all shader
stages, so that we avoid having to reconfigure it when swapping back and
forth between render and compute workloads.  So we can't have dangling
pointers.

The fix is simple: have brw_clear_cache NULL out stale prog_data
pointers, making it safe to inspect.  The next L3 configuration pass
will see either the render shaders or compute shader as missing for
one go around, but will pick them up when both pipelines have run.

In other words, we'll simply reconfigure L3 twice, which is safe,
if a tiny bit wasteful - but then again, we just threw every compiled
shader we had on the floor and started recompiling the from scratch,
which is massively more wasteful, so it's not much of a concern.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jljusten@gmail.com>

mesa: avoid segfault in GetProgramPipelineInfoLog when no length

If there is no pipe info log, we would unconditionally deref length,
which was only optionally there. _mesa_copy_string handles the source
being null, as well as the length, so may as well just always call it.

Fixes a segfault in

dEQP-GLES31.functional.state_query.program_pipeline.info_log

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: reset offset/size to 0 when removing atomic binding

Similar to commit dd9d2963d6 (mesa: AtomicBufferBindings should be
initialized to zero.), we should reset these to zero when unbinding.
This fixes a number of dEQP failures due to cross-test pollution. The
tests properly unbound everything, but when querying the values again,
the expectation was that they would be 0.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

mesa: recognize enums GL_COLOR_ATTACHMENT8-31 as valid

Similar as for AUX1-3, these enums aren't invalid (i.e. -1) but also not
supported by mesa. Returning BUFFER_COUNT causes the proper error to be
returned by ReadBuffer and other functions. This resolves some failures
in

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.read_buffer

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/clear: update ClearBufferfv error handling for GL 4.5 spec

This fixes

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.clear_bufferfv

and brings the logic up to spec with GL 4.5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/clear: update ClearBufferuiv error handling for GL 4.5 spec

This fixes

dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.clear_bufferuiv

and brings the logic up to spec with GL 4.5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/clear: simplify ClearBufferiv error handling

Might as well handle everything in the same error call.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/clear: remove dead code handling ClearBufferiv(GL_DEPTH)

There's a hunk above which sets INVALID_ENUM for GL_DEPTH
unconditionally.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: allow DEPTH_STENCIL_TEXTURE_MODE queries in GLES 3.1 contexts

This fixes

dEQP-GLES31.functional.state_query.texture.texture_2d_multisample.depth_stencil_mode_integer

and a few related tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

i915: include teximage.h

To get _mesa_num_tex_faces() prototype.

i965: include teximage.h

To get _mesa_num_tex_faces() prototype.

st/nine: Implement Managed vertex/index buffers

We were implementing those the same way than
the default pool, which is sub-optimal.

The buffer is supposed to return pointer to
a ram copy when user locks, and automatically
update the vram copy when needed.

v2: Rename NineBuffer9_Validate to NineBuffer9_Upload
Rename validate_buffers to update_managed_buffers
Initialize NineBuffer9 managed fields after the resource
is allocated. In case of allocation failure, when the dtor
is executed, This->base.pool is then rightfully set.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Align stack for entry points

For 32 bits, incoming stack is 4-byte aligned.
We need to realign the stack to 16-byte at some point,
or there are issues later (crash with SSE, llvm, etc).

This patch chooses to align the stack at API entry points.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Drop path for ureg_NRM and ureg_CLAMP

using MIN/MAX is fine instead of CLAMP.
NRM doesn't exist anymore.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Remove usage of SQRT in ff code

SQRT is not supported everywhere, so replace
it by RSQ + MUL and handle case <= 0.

Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Fix stateblocks crashes with lights

We had several issues of crashes with it.
This should fix it.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: SCRATCH does support all formats

Add new argument to d3d9_to_pipe_format_checked to
be able to bypass format support checks. This argument
is set to TRUE when the requested Pool is SCRATCH.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Add format checks to create_zs_or_rt_surface

Returns INVALIDCALL when trying to create a surface
of unsupported format.

In practice, apps are supposed to check for format
support before trying to create a render target
of that format. However some bad behaving apps
could just try to create the surface and deduce if
it failed that it wasn't supported.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Support ATI1/ATI2 for CubeTexture

Texture and CubeTexture use common code,
and thus ATI1/ATI2 is already implemented
for CubeTexture.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Clean pSharedHandle Texture ctors checks

Clarify the behaviour and clean the checks

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Move texture creation checks

We were having checks at both Create*Texture functions
and in ctors.

Move all Create*Texture checks to ctors.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Clean useless code in texture9.c

This->base.base.resource is worth NULL
for SYSTEMMEM textures.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Do not set SHARED flag for shared textures.

We do not support shared textures, thus no need to set
the shared flag.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

st/nine: Do not set resource usage for SYSTEMMEM

We do not create a resource for SYSTEMMEM textures,
thus we do not need to set resource usage.

The only exception is vertexbuffer SYSTEMMEM, since
we do use a pipe resource for them.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

mesa: move _mesa_num_tex_faces() to teximage.h

So it's near the other cube map helper functions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: simplify some code with new _mesa_cube_face_target() function

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: add _mesa_cube_face_target() helper

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: make _mesa_tex_target_to_face() an inline function

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: remove _ARB suffix from cube map enums

Just minor clean-up so we're consistent everywhere.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

docs: Visual Studio 2013 or later is now required

glsl: replace _strtoui64() with strtoull() for MSVC

Now that MSVC 2013 is required we can remove this.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: Use _aligned_malloc/free for MinGW too.

We already use these for gallium in
src/gallium/auxiliary/os/os_memory_stdc.h and it's always better to
minimize divergences between MinGW and MSVC.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Remove support for MSVC2008.

Spotted by Emil Velikov.

Trivial.

util/u_atomic: Remove MSVC 2008 support.

Spotted by Emil Velikov.

Trivial.

i965: Stop considering if msrt aux buffers need aux buffer

Auxiliary buffers are always created with sample number of zero
which effectively prevents intel_miptree_create_layout() from trying
to associate auxiliary buffers with auxiliary buffers.

Now that there is more direct path available lets start using it
instead and stop even checking for such (im)possibility.

v2 (Ben): Do not signal msaa layout with explicit argument but
          using layout_flags instead.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Separate miptree creation from auxiliary buffer setup

Currently the logic allocating and setting up miptrees is closely
combined with decision making when to re-allocate buffers in
X-tiled layout and when to associate colors with auxiliary buffers.

These auxiliary buffers are in turn also represented as miptrees
and are created by the same miptree creation logic calling itself
recursively. This means considering in vain if the auxiliary buffers
should be represented in X-tiled layout or if they should be
associated with auxiliary buffers again.
While this is somewhat unnecessary, this doesn't impose any problems
currently. Miptrees for auxiliary buffers are created as simgle-sampled
fusing the consideration for multi-sampled compression auxiliary
buffers. The format in turn is such that is not applicable for
single-sampled fast clears (that would require accompaning auxiliary
buffer).
But once the driver starts to support lossless compression of color
buffers the auxiliary buffer will have a format that would itself
be applicable for lossless compression. This would be rather
difficult and ugly to detect in the current miptree creation logic,
and therefore this patch seeks to separate the association logic
from the general allocation and setup steps.

v2 (Ben):
   - Do not reconsider for X-tiling in intel_miptree_create()
     as it was just forced to Y-tiling in miptree_create().
   - Do not drop checks for allocation failures.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Isolate aligned dimensions for stencil only

This makes the logic a little more explicit and helps to keep
subsequent patches easier to read.

Suggested-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Restore vbo after color resolve during brw_try_draw_prims()

Part of brw_try_draw_prims() is a check to validate textures
(brw_validate_textures()). In case of textures that currently have
only level zero but are marked for mipmap generation, i965 driver
will decide to replace the underlying buffer with a larger one
capable of holding also the additional levels. This results into
blit from the original buffer to the newly allocated (see
intel_miptree_copy_teximage()). This blit is currently handled with
blitter engine and hence it won't effect the ongoing draw operation.
However, this blit in turn may trigger color resolve on the source
buffer. In principle, this should be possible with fast cleared
buffers but I only started hitting it when I enabled lossless
compression (that reguires similar resolve to fast cleared buffers).

Now, the color resolve is a meta operation and uses the same drawing
path we are already in middle of. After quite a bit of debugging I
realized that the resolve will modify the current vbo setup but it
won't restore it afterwards resulting in the original draw call
using wrong vertex data.
When brw_try_draw_prims() gets called, the vbo logic in the Mesa
core (see vbo_draw_arrays()) has just bound the vbo (see
vbo_bind_arrays() and recalculate_input_bindings()). Color resolve
operation will overwrite the vbo setup by calling vbo_bind_arrays()
against the resolve rectangle (see brw_draw_rectlist()). Once the
color resolve is done the vbo setup is left to the resolve rectangle
state and the original drawing call yields bogus results.

This patch aims to restore the original state after the color
resolve by calling vbo_bind_arrays() yet again after the vertex
array state in the core context have been restored.

Now having said all this, I'd also like to state that I'm quite
uncomfortable with the nested meta operations. Ths original draw
call in this case is in fact a meta operation itself. It is a blit
from level zero to level one when generating the additional mipmap
levels (see _mesa_meta_GenerateMipmap()). Imagine the complexity
if the blit in the middle from buffer to another would go to meta
path also instead of blitter.

I would very tempted to try to move all the resolves to happen
before a meta operation is started.
Additionally I still feel that work I did earlier in the spring/
summer time moving meta operations to use direct state upload
bypassing the core context would make sense.

v2: Force input recalculation by setting the flag explicitly

v3: Do not attempt to restore vbo for opengles1 which doesn't
    support vertex buffer objects.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Validate textures before altering driver state

Validation may kick off copies and subsequently color resolves.
Color resolves (and the copies themselves if ending up in meta path)
will overwrite the internal driver state but are not prepared to
restore it. Instead of adding that capability the validation can be
simply performed before the state is updated.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make brw_clear_cache flag all the bits on both pipelines.

Setting brw->ctx.NewDriverState and brw->ctx.NewGLState affects
the dirty bits for the current pipeline.  But, we need to flag
everything dirty on *both* pipelines, so that when we switch
back, we'll realize our programs are stale and re-upload them.

To accomplish this, flag the saved state for both pipelines.
Only one of them should matter, but this way we don't have to
check which we need to set.  It's harmless to set the other.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Allow invariant qualifer in block members in desktop OpenGL.

Feedback from Khronos is that 'invariant' should be allowed on block
members for desktop OpenGL. Fix piglit regression added by fe1e89a0:
invariant-qualifier-in-out-block-01.vert

v2:
- Allow it for in/out blocks in OpenGL ES too, so when OES_shader_io_blocks
is supported we don't need to do any change (Timothy)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89330
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Consider tessellation in get_pipeline_state_l3_weights.

I think this was just missed; Curro and I were probably writing
code simultaneously and forgot to combine them at the end.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Split brw_upload_texture_surfaces into compute/render atoms.

When uploading state for the compute pipeline, we don't want to
look at VS/TCS/TES/GS/FS programs, as they might be stale, and
aren't relevant anyway.  Likewise, the render pipeline shouldn't
look at CS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93790
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

radeonsi: fix build with LLVM 3.6

Broken by this cleanup: 3dc1cb0cc7605a2f3128311f5a6052f740fc7b0d

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965/gs: Pass VerticesIn though prog_data

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass usage of depth, W, and sample mask through prog_data

We really need to stop pulling information directly out of shaders for
state setup.  For one thing, if we want any sort of an on-disk shader
cache, having all of this metadata in one place is going to be crucial.
Also, passing it all through prog_data cleans up the compiler <-> state
setup API substantially.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Refactor setup_payload_gen6 to assume FS

It's extremely FS specific so the fact that we have a stage check in the
middle of it is rather bogus.  While were here, we rename
setup_payload_gen4 and setup_payload_gen6 to make it obvious that they are
both FS specific.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nv50,nvc0: remove unused parameter in nvXX_state_validate()

This 'words' parameter is there since 2011 but it has never been used.
While we are at it, get rid of the extern declaration.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: don't validate interface blocks twice

We already check for opaque types so don't recheck for atomics
and images.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl: remove duplicate embedded struct validation

Commit c98deb18d5836f in 2010 disallowed embedded struct definitions
in ES. Then in 2013 d9bb8b7b56ce65b disallowed it for everything but
GLSL 1.10.

Commit c98deb18d5836f seemed the cleanest way to do the check so its
been extended to cover GL and the other version has been removed.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

include,gallium: Remove pre-MSVC 2013 compatibility.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

scons: Eliminate MSVC2008 compatibility.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

configure: Eliminate MSVC2008 compatibility.

We no longer need to build any part of Mesa with Windows SDK 7.0.7600 or
MSVC 2008.  MSVC 2013 will be the oldest we support.

In practice this means people are now free to declare variables in the
middle of blocks, on the whole Mesa tree.

Care should still be taken with variable length arrays and void pointer
arithmetic.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Hella-acked-by: Ian Romanick <ian.d.romanick@intel.com>

i965: ir: dump floats as %-g rather than %f, so we can see denormals

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965/gen7: Require kernel cmd_parser 5 for ARB_compute_shader

The indirect dispatch registers were whitelisted in command parser
version 5. (Version 5 is available as of Linux 4.4)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: release GLSL IR in LinkShader after it's not needed

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: call build_program_resource_list inside Driver.LinkShader

to allow LinkShader to free the GLSL IR.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

st/mesa: use correct pipe functions to create tess shaders

Broken by one of my cleanups. Spotted by luck.

Radeonsi doesn't care, because all shader create callbacks go to the same
function.

Reviewed-by: Brian Paul <brianp@vmware.com>

gallium/radeon: drop support for LLVM 3.5

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
v2: adjust the comment in the amdgpu winsys

radeonsi: obtain commonly used LLVM types only once

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: cleanup shader codegen

si_shader_ctx -> ctx
type * ptr -> type *ptr
si_shader_context *shader -> si_shader_context *ctx

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix a crash when binding a sampler buffer

Buffers don't contain r600_texture.

Broken by 7aedbbacae6d3ec3d06735fff2eb66:
"radeonsi: put image, fmask, and sampler descriptors into one array"

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94091

docs: add news item and link release notes for 11.1.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 11.1.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit e49dd21bcbabdb330620d48f5915828cfd5eb983)

docs: add release notes for 11.1.2

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 7bcd827806b0816d61122ba3d37dd40178d96d98)

nir: Remove the const_offset from nir_tex_instr

When NIR was originally drafted, there was no easy way to determine if
something was constant or not.  The result was that we had lots of
special-casing for constant values such as this.  Now that load_const
instructions are SSA-only, it's really easy to find constants and this
isn't really needed anymore.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robclark@gmail.com>

nir/lower_vec_to_movs: Better report channels handled by insert_mov

This fixes two issues.  First, we had a use-after-free in the case where
the instruction got deleted and we tried to return mov->dest.write_mask.
Second, in the case where we are doing a self-mov of a register, we delete
those channels that are moved to themselves from the write-mask.  This
means that those channels aren't reported as being handled even though they
are.  We now stash off the write-mask before remove unneeded channels so
that they still get reported as handled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94073
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

radeonsi: don't emit unnecessary NULL exports for unbound targets (v3)

v2: remove semantic index == 0 checks
    add the else statement to remove shadowing of args
v3: fix fbo-alphatest-nocolor regression

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)

i965: Make sure we blit a full compressed block

This fixes an assertion failure in [at least] one of the Unreal Engine Linux
demo/games that uses DXT1 compression. Specifically, the "Vehicle Game".

At some point, the game ends up trying to blit mip level whose size is 2x2,
which is smaller than a DXT1 block. As a result, the assertion in the blit path
is triggered. It should be safe to simply make sure we align the width and
height, which is sadly an example of compression being less efficient.

NOTE: The demo seems to work fine without the assert, and therefore release
builds of mesa wouldn't stumble over this. Perhaps there is some unnoticeable
corruption, but I had trouble spotting it.

Thanks to Jason for looking at my backtrace and figuring out what was going on.

v2: Use NPOT alignment to make sure ASTC is handled properly (Ilia)
Remove comment about how this doesn't fix other bugs, because it does.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93358
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

radeon/uvd: silence a warning

r300g: silence warnings