gem5.git
6 years agosystemc: Make sure sc_start waits for simulation even when starving.
Gabe Black [Sat, 18 Aug 2018 00:30:31 +0000 (17:30 -0700)]
systemc: Make sure sc_start waits for simulation even when starving.

Even if the simulation would return from sc_start immediately because
of starvation, this change ensures that sc_start gives control back
to gem5 so that the scheduler will have a chance to set up
sensitivities, etc., before things get torn down.

Change-Id: I39b1fd704fcbe12c299cad9dbd30258e8fe9d032
Reviewed-on: https://gem5-review.googlesource.com/12218
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Rework the init phase for the new way delta notes are handled.
Gabe Black [Fri, 17 Aug 2018 03:59:29 +0000 (20:59 -0700)]
systemc: Rework the init phase for the new way delta notes are handled.

The initialization phase had been done in a somewhat adhoc way,
partially because delta notifications were being handled as top level
gem5 events which were ordered based on their priorities. This change
makes the initialization phase happen more explicitly, and more in the
order in the spec.

Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad
Reviewed-on: https://gem5-review.googlesource.com/12217
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make a test use cout for all its messages.
Gabe Black [Fri, 17 Aug 2018 02:10:27 +0000 (19:10 -0700)]
systemc: Make a test use cout for all its messages.

This makes them end up in simout so verify.py can find them when it's
checking output.

Change-Id: I2b7b276b3e1816a257f58b0cfb13487d6296e6fd
Reviewed-on: https://gem5-review.googlesource.com/12216
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement a significant portion of sc_clock.
Gabe Black [Fri, 17 Aug 2018 02:10:09 +0000 (19:10 -0700)]
systemc: Implement a significant portion of sc_clock.

Change-Id: Ic195f46ac13b46a02c86a5fc8d90ba66a415a9c8
Reviewed-on: https://gem5-review.googlesource.com/12215
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Don't run the ready event inline when unpausing.
Gabe Black [Fri, 17 Aug 2018 02:01:28 +0000 (19:01 -0700)]
systemc: Don't run the ready event inline when unpausing.

Now that delta events are handled explicitly by the scheduler, there's
no reason to run the readyEvent inline when returning from a pause. The
delta events will necessarily be run after the evaluate and update
phases.

Change-Id: Iad6d431a87742354e3a46a0fb44c309aa785ea60
Reviewed-on: https://gem5-review.googlesource.com/12214
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Rework how delta and timed notifications/timeouts are tracked.
Gabe Black [Fri, 17 Aug 2018 01:59:06 +0000 (18:59 -0700)]
systemc: Rework how delta and timed notifications/timeouts are tracked.

Rather than delegating them entirely to the gem5 event queue and using
priorities to ensure the right thing happens, this change adds a few
new structures which keep track of them and give the scheduler more
control over what happens and in what order. The old scheme was mostly
correct, but there were some competing situations which made it next
to impossible to make everything happen at the right time.

Change-Id: I43f4dd6ddfa488a31073c0318bb41369b1a6117d
Reviewed-on: https://gem5-review.googlesource.com/12213
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agomem-ruby: Fix a bug in MessageBuffer randomization
Xianwei Zhang [Wed, 19 Sep 2018 23:14:40 +0000 (19:14 -0400)]
mem-ruby: Fix a bug in MessageBuffer randomization

In the previous implementation, messages are randomly inserted with
delays only if both RubySystem and MessageBuffer randomization flags
are set true.  However, to find race conditions and cover more slicc
transitions, ruby random testers rely on setting RubySystem flag to
turn on randomization on all message buffers.
As a fix, this patch enables a message buffer to have randomization
when either RubySystem or its own flag is set.

Change-Id: I1e076908ff07e5846ebad4f4fc1c8f28d40bbfd4
Reviewed-on: https://gem5-review.googlesource.com/12784
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosystemc: When sc_start is told to run zero time, do one delta cycle.
Gabe Black [Thu, 16 Aug 2018 21:42:24 +0000 (14:42 -0700)]
systemc: When sc_start is told to run zero time, do one delta cycle.

This is a special case which is mentioned in the spec but hadn't yet
been given any special handling in this implementation.

Change-Id: I500d046f09d916a08e22821f8d3e2f490f8ba5bb
Reviewed-on: https://gem5-review.googlesource.com/12212
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Don't run clocked thread processes during the init phase.
Gabe Black [Thu, 16 Aug 2018 07:49:25 +0000 (00:49 -0700)]
systemc: Don't run clocked thread processes during the init phase.

Change-Id: I170d67fef61dd5536a842a1f64682d90ae7a1507
Reviewed-on: https://gem5-review.googlesource.com/12211
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Track exports and prim channels, and call their callbacks.
Gabe Black [Thu, 16 Aug 2018 06:35:38 +0000 (23:35 -0700)]
systemc: Track exports and prim channels, and call their callbacks.

Also call the callbacks on the ports which were already being tracked.

Change-Id: I5ba8ea366e87fc48b58712f35b93c27bccf92cb3
Reviewed-on: https://gem5-review.googlesource.com/12210
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fix the priority of the maximum time event.
Gabe Black [Thu, 16 Aug 2018 02:16:41 +0000 (19:16 -0700)]
systemc: Fix the priority of the maximum time event.

Change-Id: I3e5e71165d06da77076f0e58012c575e24456182
Reviewed-on: https://gem5-review.googlesource.com/12209
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement a little more of sc_time.
Gabe Black [Thu, 16 Aug 2018 00:42:52 +0000 (17:42 -0700)]
systemc: Implement a little more of sc_time.

This change implements a pair of constructors, and some conversion
functions.

Change-Id: Ibd0e9ec5bcc24f4a17896313996b3112b5ef1934
Reviewed-on: https://gem5-review.googlesource.com/12208
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Teach verify.py to ignore another deprecation warning.
Gabe Black [Thu, 16 Aug 2018 00:42:30 +0000 (17:42 -0700)]
systemc: Teach verify.py to ignore another deprecation warning.

Change-Id: I4c45431abebafd69f485f9d740da30f4b957f609
Reviewed-on: https://gem5-review.googlesource.com/12207
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Generalize ignoring info messages in the reference output.
Gabe Black [Tue, 14 Aug 2018 01:50:28 +0000 (18:50 -0700)]
systemc: Generalize ignoring info messages in the reference output.

Those messages are very implementation specific and don't (generally)
affect correctness. This makes it easier to ignore info messages based
on their number.

This change also makes the output checker ignore a similarly styled
message gem5 generates. We should consider making gem5 not generate
that message and have it generate another message instead which is
specific to gem5. We would need to filter that out too when comparing
results.

Change-Id: I93b9e2d547b6259512db091cfc557d21f86f4a3d
Reviewed-on: https://gem5-review.googlesource.com/12086
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement the sc_in class.
Gabe Black [Tue, 14 Aug 2018 01:20:52 +0000 (18:20 -0700)]
systemc: Implement the sc_in class.

Change-Id: I08174462cb650c7918a4e8f5284d4ee814cf595d
Reviewed-on: https://gem5-review.googlesource.com/12085
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement port binding except positional binding.
Gabe Black [Tue, 14 Aug 2018 01:19:15 +0000 (18:19 -0700)]
systemc: Implement port binding except positional binding.

This change adds code which keeps track of ports and interfaces which
are being bound to be finalized later, and the actual port binding of
interfaces and recursive binding port ports.

Change-Id: Ifa885ed44b667254762cc101580be4f0a7d7a131
Reviewed-on: https://gem5-review.googlesource.com/12084
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make BindInfo track ports or interfaces.
Gabe Black [Tue, 14 Aug 2018 01:16:14 +0000 (18:16 -0700)]
systemc: Make BindInfo track ports or interfaces.

Change-Id: I0ca0d5de8de59d92cb65af56c25f418ff32696f4
Reviewed-on: https://gem5-review.googlesource.com/12083
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement sc_event_finder.
Gabe Black [Tue, 14 Aug 2018 01:14:35 +0000 (18:14 -0700)]
systemc: Implement sc_event_finder.

Change-Id: I22aa0a34eabf13593986a92289155257fa26c7de
Reviewed-on: https://gem5-review.googlesource.com/12082
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Exclude two more tests which have undefined functions.
Gabe Black [Tue, 14 Aug 2018 01:10:05 +0000 (18:10 -0700)]
systemc: Exclude two more tests which have undefined functions.

It seems that implementing more of systemc makes the compiler think it
wants an implementation, and so the build fails with linker errors.

Change-Id: I6f0b031f300b0ad60dac8b4462b8f4d466aa7dfa
Reviewed-on: https://gem5-review.googlesource.com/12081
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ensure delta notifications happen at the right time after sc_pause.
Gabe Black [Fri, 10 Aug 2018 03:31:35 +0000 (20:31 -0700)]
systemc: Ensure delta notifications happen at the right time after sc_pause.

Normally delta notifications would be created during the evaluation or
update phases, and so there isn't any problem with them cutting in
front of those stages. When the simulation is paused however, those
notifications could be waiting before the ready event starts and could
preempt it.

This change adds a check for that situation to the end of the pause
event and runs the evalution and update stages inline if necessary.

Change-Id: I4477b2ae8e7980406df00ba7320ae2a24ae2da9b
Reviewed-on: https://gem5-review.googlesource.com/12080
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement sc_export.
Gabe Black [Thu, 9 Aug 2018 02:31:56 +0000 (19:31 -0700)]
systemc: Implement sc_export.

This change ignores the rule that sc_exports all have to be bound
exactly once and only by the end of elaboration. If it's bound more
than once, then the earlier binding will be overwritten, and if it's
not bound at all then it will act like a null pointer. To accomodate
doing those checks in the future, the sc_export_base constructor and
destructor are in the .cc file even though they do very little so that
they can be extended to track a list of all exports which exist.

Change-Id: Ie9a3416b8fa87bca55bc9f87f3238c4de3c2e729
Reviewed-on: https://gem5-review.googlesource.com/12079
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Don't schedule the update phase if the event queue is null.
Gabe Black [Wed, 8 Aug 2018 09:56:00 +0000 (02:56 -0700)]
systemc: Don't schedule the update phase if the event queue is null.

That happens when an update is requested before the initialization
phase has started. In that case, the update phase will be manually run
and no event needs to be scheduled, even if that was possible.

Change-Id: I2008e29064d282f82bd1935dbe5b94407aa925b0
Reviewed-on: https://gem5-review.googlesource.com/12078
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Use an std::list to track all modules.
Gabe Black [Wed, 8 Aug 2018 09:03:30 +0000 (02:03 -0700)]
systemc: Use an std::list to track all modules.

This is less efficient when modules are destroyed since the list isn't
sorted, and each module needs to find its own entry to remove. The
benefit is that entries added to the end of the list while the list is
being iterated over will still be included, and that the order the
modules are added will be preserved so that it matches what the order
in the regression tests.

Change-Id: I5af5d15f316fa58561e8fd9ca77f667ddc8b2c5e
Reviewed-on: https://gem5-review.googlesource.com/12077
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Track the module in the end_of_elaboration callback.
Gabe Black [Wed, 8 Aug 2018 09:02:25 +0000 (02:02 -0700)]
systemc: Track the module in the end_of_elaboration callback.

sc_objects constructed during that callback are considered children of
the module the callback belongs to.

Change-Id: I164863a10beef6d0e2c6d9c5e8f2642d80769dca
Reviewed-on: https://gem5-review.googlesource.com/12076
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Partially implement the sc_signal class template.
Gabe Black [Wed, 8 Aug 2018 08:32:00 +0000 (01:32 -0700)]
systemc: Partially implement the sc_signal class template.

There are a few details of this class that still need to be fleshed
out, but this implements most of it.

Change-Id: I6f8b546aacd8537d4341dc91e59b95864ae0f7c4
Reviewed-on: https://gem5-review.googlesource.com/12075
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Add a nonstandard sc_status pretty printer operator.
Gabe Black [Wed, 8 Aug 2018 08:30:47 +0000 (01:30 -0700)]
systemc: Add a nonstandard sc_status pretty printer operator.

This operator exists in the Accellera implementation, and is necessary
to make the test output match.

Change-Id: I266629d6c936d4846e88e35af36555fb392b181c
Reviewed-on: https://gem5-review.googlesource.com/12074
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Set the scheduler's event queue earlier.
Gabe Black [Wed, 8 Aug 2018 08:29:27 +0000 (01:29 -0700)]
systemc: Set the scheduler's event queue earlier.

The kernel can set the event queue during its own construction which
will ensure that the scheduler can schedule events as early as
possible.

Change-Id: I0e47ca0a667e77d36c97860cd7c6b7577415c801
Reviewed-on: https://gem5-review.googlesource.com/12073
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: "Implement" sc_interface's methods.
Gabe Black [Tue, 7 Aug 2018 11:53:01 +0000 (04:53 -0700)]
systemc: "Implement" sc_interface's methods.

Most don't do anything. Make default_event() return a dummy event to
avoid dereferencing a null pointer.

Change-Id: I8d6d576d3a1f585029c387cd414bbebf2d670644
Reviewed-on: https://gem5-review.googlesource.com/12072
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement a few more member functions for sc_time.
Gabe Black [Tue, 7 Aug 2018 11:49:04 +0000 (04:49 -0700)]
systemc: Implement a few more member functions for sc_time.

Change-Id: I40a7fb278f2a0ec4124589e02e4441c1866c86ea
Reviewed-on: https://gem5-review.googlesource.com/12071
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Use the new python interface to delay fixing the timescale.
Gabe Black [Tue, 7 Aug 2018 10:54:08 +0000 (03:54 -0700)]
systemc: Use the new python interface to delay fixing the timescale.

This is necessary if an sc_time object is constructed globally, either
directly or indirectly, before python is available to fix the
timescale. The call will be deferred until the interpretter is up and
ready.

Change-Id: I486c0a90d44a0e0f0ad8c530b7148e1cff04a5cc
Reviewed-on: https://gem5-review.googlesource.com/12070
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Generalize working with the systemc python module from C++.
Gabe Black [Tue, 7 Aug 2018 10:51:18 +0000 (03:51 -0700)]
systemc: Generalize working with the systemc python module from C++.

This change pulls the systemc python module creation code out of
sc_main and puts it into a more general purpose python.hh and
python.cc which can be used by other code to add other entries into
that module without having to track that in a central place.

This change also adds a mechanism for notifying C++ code that the
embedded python interpretter is up and ready to interact with in case
it needs to call some python only functionality. An example of that is
the code which tracks and then fixes the timescale for the simulator.

Change-Id: I9afcd5a089b21d23ebc1b5fdb6f643ae2f7e5f11
Reviewed-on: https://gem5-review.googlesource.com/12069
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ignore a warning in the reference test outputs.
Gabe Black [Tue, 7 Aug 2018 08:29:29 +0000 (01:29 -0700)]
systemc: Ignore a warning in the reference test outputs.

The warning is about deprecated sc_module constructors which don't take
an sc_module_name.

Change-Id: I2ef864a5bdac93eb8104a842179ffe45a8335085
Reviewed-on: https://gem5-review.googlesource.com/12068
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fix the seed used with sc_gen_unique_name for sc_port.
Gabe Black [Tue, 7 Aug 2018 08:26:14 +0000 (01:26 -0700)]
systemc: Fix the seed used with sc_gen_unique_name for sc_port.

The seed should only be "port" not "sc_port".

Change-Id: Ia046103abc0a9ed283fcb7cf7d8069383a1e2b0d
Reviewed-on: https://gem5-review.googlesource.com/12067
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement sc_gen_unique_name.
Gabe Black [Tue, 7 Aug 2018 08:23:01 +0000 (01:23 -0700)]
systemc: Implement sc_gen_unique_name.

The Accellera implementation statically allocates the buffer it uses to
build the unique names and only allocates the name generator if it's
going to be used for a particular module. I assume that's to avoid
allocating a large buffer if it's not going to be used.

In this implementation, I use an std::string which manages its own
memory and so shouldn't need to be selectively allocated. I also use a
string stream to construct the name instead of sprintf.

Change-Id: If92c68586a85b5d27c067a75a6e9ebbf00d8c785
Reviewed-on: https://gem5-review.googlesource.com/12066
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Always set USE_SYSTEMC=1 when compiling with verify.py.
Gabe Black [Sat, 28 Jul 2018 08:49:52 +0000 (01:49 -0700)]
systemc: Always set USE_SYSTEMC=1 when compiling with verify.py.

It doesn't make sense not to have systemc enabled when building the
systemc regression tests.

Change-Id: I23b81fd4d7cbd0dbf5efbea773d816296d6492be
Reviewed-on: https://gem5-review.googlesource.com/12065
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py ignore an Info: message.
Gabe Black [Sat, 28 Jul 2018 08:13:23 +0000 (01:13 -0700)]
systemc: Make verify.py ignore an Info: message.

This message is about how to disable a warning about sc_bit being
deprecated.

Change-Id: I1a0b12e2ca5b58328e37605ba3f7e3e1a384e351
Reviewed-on: https://gem5-review.googlesource.com/12064
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Adjust a warning to match Accellera.
Gabe Black [Sat, 28 Jul 2018 08:07:15 +0000 (01:07 -0700)]
systemc: Adjust a warning to match Accellera.

This is to pass fix a diff in the regression tests.

Change-Id: Id1b963df647224d7a3589febe7986353a4a8e440
Reviewed-on: https://gem5-review.googlesource.com/12063
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosyscall_emul: implement dir-related syscalls
Brandon Potter [Wed, 18 Apr 2018 18:45:37 +0000 (14:45 -0400)]
syscall_emul: implement dir-related syscalls

Add getdents, rmdir, chdir, and mknod to SE mode for x86.

Change-Id: I387ea3066869e8999bc0064f74070f4e47c1e9a1
Reviewed-on: https://gem5-review.googlesource.com/12112
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

6 years agosyscall_emul: refactor FDEntry and children classes
Brandon Potter [Wed, 18 Apr 2018 18:44:10 +0000 (14:44 -0400)]
syscall_emul: refactor FDEntry and children classes

Strips off superfluous inline specifiers in header file.

Changes return types and parameters that deal with strings
to include the const& specifiers.

Change-Id: I570b1801abb059b91216f0223458d00963b9ca1c
Reviewed-on: https://gem5-review.googlesource.com/12111
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosyscall_emul: style changes and FDArray refactor
Brandon Potter [Wed, 18 Apr 2018 18:42:31 +0000 (14:42 -0400)]
syscall_emul: style changes and FDArray refactor

Some members were defined as public when they should have been
privately declared so these were moved to the appropriate spot.

The operator[] had inline specified for for an in-class
definition which is redundant since inline definitions are
always implicitly inline.

Private members had the leading underscore applied to them to
denote that they're private (consistent with style guide).

Changed static const defined class variable into a constexpr
with brace-list initialization.

Change-Id: If3054416b57827d1542e9ebab428d67d0e767723
Reviewed-on: https://gem5-review.googlesource.com/12110
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosyscall_emul: expand AuxVector class
Brandon Potter [Fri, 4 May 2018 21:55:24 +0000 (17:55 -0400)]
syscall_emul: expand AuxVector class

The AuxVector class is responsible for holding Process data.
The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is
to pass in information that the process will need for various
reasons. (Check out the enum in the header file for an idea of
what the AuxVector holds.)

The AuxVector struct was changed into a class and encapsulation
methods were added to protect access to the member variables.

The host ISA may have a different endianness than the simulated
ISA. Since data is passed between the process address space and
the simulator for auxiliary vectors, we need to worry about
maintaining endianness for the right context.

Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9
Reviewed-on: https://gem5-review.googlesource.com/12109
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

6 years agoscons: remove as version check
Ciro Santilli [Fri, 31 Aug 2018 10:39:19 +0000 (11:39 +0100)]
scons: remove as version check

GNU as 2.31.1 checks if the input and output files are the same:

Assembler messages:
Fatal error: The input and output files must be distinct

The check already does not work for llvm-as which has a different
output format.

Since it is too hard to maintain the check correctly for all possible
assemblers, it is better to just remove it completely.

Change-Id: I38a993ab83ca83d4a2f5e77820d2ca903f70c6ac
Reviewed-on: https://gem5-review.googlesource.com/12403
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem-cache: Fix non-bijective function in Skewed caches
Daniel R. Carvalho [Wed, 19 Sep 2018 08:19:06 +0000 (10:19 +0200)]
mem-cache: Fix non-bijective function in Skewed caches

The hash() function must be bijective for the skewed caches to work,
however when the hashing is done on top of a one-bit address, the
MSB and LSB refer to the same bit, and therefore their xor will
always be zero.

This patch adds a fatal error to not allow the user to set an invalid
value for the number of sets that would generate that bug.

As a side note, the missing header for the bitfields functions has
been added.

Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021
Reviewed-on: https://gem5-review.googlesource.com/12724
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agodev, arm: fix error class-memaccess with GCC >= 8.1
Maurice Becker [Tue, 18 Sep 2018 08:14:24 +0000 (10:14 +0200)]
dev, arm: fix error class-memaccess with GCC >= 8.1

From GCC 8.1 on GCC issues a warning when using memset et al on structs and
classes. With the way gem5 builds, this actually prevents successful
builds.

Instead of using a pointer with SCSIReply as type, we cast to a void
pointer to avoid the message. On the way we wrap the memset call into a
method of SCSIReply called reset for better code readability.

Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68
Reviewed-on: https://gem5-review.googlesource.com/12685
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoPl011: Added registers UART_RSR/UART_ECR
Maurice Becker [Tue, 18 Sep 2018 08:27:40 +0000 (10:27 +0200)]
Pl011: Added registers UART_RSR/UART_ECR

UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4).  As
these transmission errors never occur, they are implemented as RAZ/WI.

Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.

Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem: Implement QoS Proportional Fair policy
Giacomo Travaglini [Fri, 17 Aug 2018 09:17:59 +0000 (10:17 +0100)]
mem: Implement QoS Proportional Fair policy

Providing a configurable fair scheduling policy based on utilization;
utilization is directly proportional to a score which is inversely
proportional to the QoS priority. It is meant to avoid starvation of low
priority packets.

Users can tune the policy by adjusting the weight parameter (weight of
the following formula)

new_score = ((1.0 - weight) * old_score) + (weight * served_bytes)

Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12359
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

6 years agoconfig, arm, power: Example to report the power for the L2 Cache
Sherif Elhabbal [Fri, 14 Sep 2018 15:10:24 +0000 (17:10 +0200)]
config, arm, power: Example to report the power for the L2 Cache

This patch add an example to demonstrate how to report the power for the L2
Cache of the big cluster separately ,it decouples the L2 contributions from
the CPU power equation

Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58
Reviewed-on: https://gem5-review.googlesource.com/12684
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agopower: Add a clock_period variable to power expressions
Sherif Elhabbal [Thu, 13 Sep 2018 14:01:55 +0000 (16:01 +0200)]
power: Add a clock_period variable to power expressions

Currently 'Clock period in ticks' stat is not accessible in power equations .
This patch adds a variable 'clock_period' to be referenced to get the Clock period in
ticks

Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72
Reviewed-on: https://gem5-review.googlesource.com/12664
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoFix SConstruct for asan build
Earl Ou [Fri, 7 Sep 2018 07:16:53 +0000 (15:16 +0800)]
Fix SConstruct for asan build

Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes
some build error when using --with-asan.

Bug: None
Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug

Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7
Reviewed-on: https://gem5-review.googlesource.com/12511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

6 years agoarch-arm: Correction for address size in EL1&0 translation
Anouk Van Laer [Tue, 4 Sep 2018 10:44:42 +0000 (11:44 +0100)]
arch-arm: Correction for address size in EL1&0 translation

When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).

See D10.2.121 of the ARM ARM.

Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agoarch-arm: Correction to address size in EL2/EL3
Anouk Van Laer [Mon, 3 Sep 2018 10:18:31 +0000 (11:18 +0100)]
arch-arm: Correction to address size in EL2/EL3

This commit corrects how the address size is
determined in EL2/EL3.  Previously, TCR_ELx.ips
was used but this should be TCR_ELx.ps.

Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12551
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agomem-cache: Fix bug in handleAtomicReqMiss
Nikos Nikoleris [Sat, 1 Sep 2018 14:38:13 +0000 (15:38 +0100)]
mem-cache: Fix bug in handleAtomicReqMiss

"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.

Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agodev-arm: fix build to missing Pl390 to Gicv2 rename
Ciro Santilli [Wed, 12 Sep 2018 14:33:01 +0000 (15:33 +0100)]
dev-arm: fix build to missing Pl390 to Gicv2 rename

Change-Id: I6756f2c789aaca410d201aa64147443b66afee39
Reviewed-on: https://gem5-review.googlesource.com/12645
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoconfig, dev-arm: Fix UART handling baremetal mode
Ciro Santilli [Thu, 30 Aug 2018 09:58:10 +0000 (10:58 +0100)]
config, dev-arm: Fix UART handling baremetal mode

fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform
due to inconsistent UART naming with error message:

AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'

Consistently name keep all UARTs in the Arm platforms in a vector named
'uart' or as a single device named 'uart'. Update the configuration
scripts to reflect the fact that 'uart' can be a vector.

Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12473
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agodev-arm: rename Pl390 to GicV2
Ciro Santilli [Thu, 30 Aug 2018 13:50:31 +0000 (14:50 +0100)]
dev-arm: rename Pl390 to GicV2

The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.

GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.

Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agodev-arm: improve Pl390 parameters
Ciro Santilli [Thu, 30 Aug 2018 13:50:31 +0000 (14:50 +0100)]
dev-arm: improve Pl390 parameters

Remove default dist_addr and cpu_addr register addresses since those are
purely platform specific.

Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and
distributor base too close for the newer CPU size of 0x2000, leading to
overlap.

This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes
using RealViewPBX fail with:

fatal: system.membus has two ports responding within range
[0x1f000100 : 0x1f0020ff]:
        system.realview.gic.pio
        system.realview.gic.pio

Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agocpu: Replace the fastmem with a new CPU model
Andreas Sandberg [Tue, 15 Mar 2016 15:45:12 +0000 (15:45 +0000)]
cpu: Replace the fastmem with a new CPU model

The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.

The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.

This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.

Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosystemc: Adjust some whitespace in a print out.
Gabe Black [Sat, 28 Jul 2018 07:57:55 +0000 (00:57 -0700)]
systemc: Adjust some whitespace in a print out.

This makes a test output file diff successfully.

Change-Id: Ia269b4b33f719a2559197d9296f9acc601ec65f7
Reviewed-on: https://gem5-review.googlesource.com/12062
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py ignore another warning.
Gabe Black [Sat, 28 Jul 2018 07:14:41 +0000 (00:14 -0700)]
systemc: Make verify.py ignore another warning.

Also make warning filters more general and easier to add by writing a
function to generate them.

Change-Id: I8d813ded9ad8a9ccac4e48e5ea80a3c9c23959da
Reviewed-on: https://gem5-review.googlesource.com/12061
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py compare non output log reference files.
Gabe Black [Sat, 28 Jul 2018 06:39:10 +0000 (23:39 -0700)]
systemc: Make verify.py compare non output log reference files.

There are only a few of these which are vcd files. If there are
reference files which aren't the log and which aren't in the gem5
output directory, mark those tests as failed as well.

Change-Id: I2c880c13d0f90ccf16ac0439dbac68de9223cc90
Reviewed-on: https://gem5-review.googlesource.com/12060
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Delete empty/misnamed test reference file.
Gabe Black [Sat, 28 Jul 2018 06:06:47 +0000 (23:06 -0700)]
systemc: Delete empty/misnamed test reference file.

The name of the reference file doesn't match the name of the test, and
is empty. There's also a correctly named log file in the same directory
which will be used instead.

Change-Id: I6501b465b99af403ae4af6d43189280c4b45fc8f
Reviewed-on: https://gem5-review.googlesource.com/12059
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Remove some junk test reference files.
Gabe Black [Sat, 28 Jul 2018 06:01:55 +0000 (23:01 -0700)]
systemc: Remove some junk test reference files.

These files have truncated names, and are identical to correct versions
of the log files.

Change-Id: I1e5e3c8c489d41dea21f62b4664b05bf6a742117
Reviewed-on: https://gem5-review.googlesource.com/12058
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ensure the terminated event is notified in all cases.
Gabe Black [Fri, 27 Jul 2018 23:28:50 +0000 (16:28 -0700)]
systemc: Ensure the terminated event is notified in all cases.

The terminated event was being notified if a process was killed, but
not if it was terminated in other ways. This change moves the
notification into the helper which sets termination related state.

Change-Id: I10aa5ad25875db992c8408dc60f087efc76b336b
Reviewed-on: https://gem5-review.googlesource.com/12057
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py delete obsolete diff files.
Gabe Black [Fri, 27 Jul 2018 23:06:32 +0000 (16:06 -0700)]
systemc: Make verify.py delete obsolete diff files.

If diff file exists but the underlying diff has been fixed, delete the
diff file.

Change-Id: Icadc21a61c084198a8a246ab6d00a9b885647cde
Reviewed-on: https://gem5-review.googlesource.com/12056
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py ignore a warning.
Gabe Black [Fri, 27 Jul 2018 23:04:31 +0000 (16:04 -0700)]
systemc: Make verify.py ignore a warning.

Change-Id: Ia887b7195d84d0ba9e77370d7b928e201ca78731
Reviewed-on: https://gem5-review.googlesource.com/12055
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Teach verify.py to diff files when checking test results.
Gabe Black [Fri, 27 Jul 2018 10:32:22 +0000 (03:32 -0700)]
systemc: Teach verify.py to diff files when checking test results.

Currently it just diffs the stdout and ignores other reference files.
It also doesn't filter out noise in the diffs from non test related
simulator messages. These include startup messages, messages when the
simulator finishes executing, and some non-standard warnings, etc.

Change-Id: Idcb19edd893cd8818423c2c5ebb6cbfb278baffa
Reviewed-on: https://gem5-review.googlesource.com/12054
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Add return code verification to verify.py.
Gabe Black [Fri, 27 Jul 2018 00:53:01 +0000 (17:53 -0700)]
systemc: Add return code verification to verify.py.

This just checks whether gem5 exited of its own accord with a
successful error code, or in other words that it didn't hang or crash.
More checking will need to be added to verify the output against the
golden reference.

Change-Id: I1ddef56aa73b5f700743830bd6212804531c484f
Reviewed-on: https://gem5-review.googlesource.com/12053
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Record the test's return code in the output directory.
Gabe Black [Thu, 26 Jul 2018 23:37:56 +0000 (16:37 -0700)]
systemc: Record the test's return code in the output directory.

verify.py will be able to use that value later to determine whether a
test was successful.

Change-Id: Ib499a4b6f202ee46e66e5de1b61a7e6309df9886
Reviewed-on: https://gem5-review.googlesource.com/12052
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Extend the execute phase of verify.py.
Gabe Black [Thu, 26 Jul 2018 23:06:01 +0000 (16:06 -0700)]
systemc: Extend the execute phase of verify.py.

Add -j and --timeout options to the execute phase of verify.py.

The --timeout option is implemented using the timeout utility program
which is assumed to be available on the host system. Python 3.3 added
a timeout argument to the subprocess module which is an alternative
approach, but then we would be dependent on python 3.3.

-j is implemented using the standard multiprocess.pool.ThreadPool
class.

Change-Id: I15b92f2b14de6710e2027a6a19984b2644b2a8df
Reviewed-on: https://gem5-review.googlesource.com/12051
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Detect a process control corner case and report an error.
Gabe Black [Thu, 26 Jul 2018 22:15:20 +0000 (15:15 -0700)]
systemc: Detect a process control corner case and report an error.

This error reporting results in an exception being thrown, and one (or
more) of the tests depend on that behavior.

Change-Id: I858aa14fbb80b0648392179a6a8d2055c91aedf8
Reviewed-on: https://gem5-review.googlesource.com/12050
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Adjust process status tracking to improve kill/reset support.
Gabe Black [Thu, 26 Jul 2018 22:13:52 +0000 (15:13 -0700)]
systemc: Adjust process status tracking to improve kill/reset support.

This change rearranges how process status is tracked so that the kill
and reset mechanisms work in more circumstances and more like they're
supposed to according to the spec. This makes another test or two pass.

Change-Id: Ie2a683a796155a82092109d5bb45f07c84e06c76
Reviewed-on: https://gem5-review.googlesource.com/12049
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement most of the sc_report_handler mechanism.
Gabe Black [Thu, 26 Jul 2018 02:30:30 +0000 (19:30 -0700)]
systemc: Implement most of the sc_report_handler mechanism.

This doesn't include support for the deprecated integer message ids.

Change-Id: I309d58df1cdc464428189eb0b7180edf41ca4f67
Reviewed-on: https://gem5-review.googlesource.com/12048
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ignore direct requests to mark a process as ready.
Gabe Black [Tue, 24 Jul 2018 02:39:52 +0000 (19:39 -0700)]
systemc: Ignore direct requests to mark a process as ready.

That might happen when a process is being marked as ready at the start
of simulation.

Because the process might not end up on the ready list, displacing it
from the init list, excplicitly pop it off the init list as well.

Change-Id: Iebf972e3e1baedec17b9b99b4da9dd44cd8e6957
Reviewed-on: https://gem5-review.googlesource.com/12047
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fill out process handle kill and reset mechanisms.
Gabe Black [Sat, 21 Jul 2018 05:16:12 +0000 (22:16 -0700)]
systemc: Fill out process handle kill and reset mechanisms.

Some flags were being updated too early, making the functions think
what they were about to do had already been done. Also, actually check
for and throw the exception installed in a process when it's next
supposed to run, and when injecting an exception schedule that other
process to run immediately.

Change-Id: I0856b69903699b2c66f9dc7f44942bbfe3cfdcc4
Reviewed-on: https://gem5-review.googlesource.com/12046
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fix a "problem" with kill/reset exceptions.
Gabe Black [Sat, 21 Jul 2018 05:13:14 +0000 (22:13 -0700)]
systemc: Fix a "problem" with kill/reset exceptions.

Despite what it says in the spec, the proc_ctrl compliance test throws
a copy of the reset exception it catches, not the original. Because of
that, the code in the kernel which catches the exception gets the base
class, not the derived class with overridden virtual methods, etc.
This happens to work for the Accellera implementation because they
manipulate members of the base class itself which are preserved despite
this bug. To make the test work, we imitate their implementation, even
though it exposes more implementation details through the header files.

Change-Id: I7ed9818c0552869ec790cb7f7bfbe365ade5e49c
Reviewed-on: https://gem5-review.googlesource.com/12045
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement much of sc_spawn.
Gabe Black [Sat, 21 Jul 2018 02:27:27 +0000 (19:27 -0700)]
systemc: Implement much of sc_spawn.

This doesn't implement reset signals, although those aren't implemented
for static processes either yet.

Change-Id: I748a7f75b9b91774c91d969bc1ff5b07e1711aa3
Reviewed-on: https://gem5-review.googlesource.com/12044
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Promote some functions to sc_export_base.
Gabe Black [Sat, 21 Jul 2018 02:25:48 +0000 (19:25 -0700)]
systemc: Promote some functions to sc_export_base.

There are a few functions which return a generic sc_interface pointer
which were (in the spec) defined to be in the interface type specific
sc_export class. They don't need to be and aren't in the Accellera
implementation, and without having them in the base class there's no
good way to get at a generic interface pointer from an export.

Change-Id: Iba692c79bf1d4f7684f28447d8b22c88ef4b804d
Reviewed-on: https://gem5-review.googlesource.com/12043
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Add a sensitivity type for exports.
Gabe Black [Sat, 21 Jul 2018 02:24:58 +0000 (19:24 -0700)]
systemc: Add a sensitivity type for exports.

Dynamic processes can be sensitive to exports, so we need a pending
sensitivity to represent them.

Change-Id: I87952f8bbb7847ad1f1d98d35cd5dd488e7b28ab
Reviewed-on: https://gem5-review.googlesource.com/12042
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make some functions of the kernel static.
Gabe Black [Sat, 21 Jul 2018 02:23:58 +0000 (19:23 -0700)]
systemc: Make some functions of the kernel static.

This makes it possible to call them without having to have a kernel
instance available. The kernel is a singleton anyway, so there should
only ever be a single instance of any of these values.

Change-Id: I3610d60cc72e9f3114997fe63db94b96ccaac3cd
Reviewed-on: https://gem5-review.googlesource.com/12041
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement + and - for sc_time, and sc_max_time.
Gabe Black [Sat, 21 Jul 2018 00:36:04 +0000 (17:36 -0700)]
systemc: Implement + and - for sc_time, and sc_max_time.

Change-Id: I294b63840e42e2afdef198229adc60ddbb60b9a1
Reviewed-on: https://gem5-review.googlesource.com/12040
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fix a couple memory errors.
Gabe Black [Sat, 21 Jul 2018 00:18:22 +0000 (17:18 -0700)]
systemc: Fix a couple memory errors.

Because events are held in vectors, it doesn't make sense to keep an
iterator into the parent to keep track of where that event is for easy
removal since the iterator becomes invalid when the vector is changed.

The events need to be stored in a vector because systemc defines an
accessor which returns that vector, and building a vector on the fly
would be cumbersome.

Also, make sure the Event parent pointer is set to nullptr if there
isn't a parent.

Change-Id: I63a676190e7747e60baaca50009161d47bfc1c54
Reviewed-on: https://gem5-review.googlesource.com/12039
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement the SC_EXIT_ON_STARVATION exit mode.
Gabe Black [Fri, 20 Jul 2018 23:28:54 +0000 (16:28 -0700)]
systemc: Implement the SC_EXIT_ON_STARVATION exit mode.

This mode implies checking whether there's any activity left either
before starting a delta cycle, or processing delta or timed
notification or timeout.

Change-Id: I0780a1f720cf63f3d2907b8dd28685266b52d6b4
Reviewed-on: https://gem5-review.googlesource.com/12038
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Fix the time resolution when constructing an sc_time.
Gabe Black [Fri, 20 Jul 2018 22:46:49 +0000 (15:46 -0700)]
systemc: Fix the time resolution when constructing an sc_time.

This is (sort of) mandated by the spec. More specifically the spec says
that the systemc API for changing the time resolution can only be
called once, and can only be called before a non-zero sc_time is
constructed.

Because sc_time can be constructed during elaboration and the gem5
version of time resolution is generally not locked down until the
actual simulation starts (after elaboration), the sc_time constructor
needs to call the fixing function itself to ensure that, for instance,
the scaling factors for various real life time units within gem5 are
initialized.

Change-Id: Ied4b43659834761b55b5ae49ea62779af891d9e3
Reviewed-on: https://gem5-review.googlesource.com/12037
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Handle event notifications scheduled before sc_start.
Gabe Black [Fri, 20 Jul 2018 00:32:34 +0000 (17:32 -0700)]
systemc: Handle event notifications scheduled before sc_start.

After sc_start is called, gem5 has run far enough to have an event
queue to schedule the notification events on. Before then, it's still
legal to request a timed notification. The scheduler should keep track
of those requests, and once an event queue is available it should
add them to it.

Change-Id: Ie7445b1f2e616f4bd36044a09dbef9e1d12d7350
Reviewed-on: https://gem5-review.googlesource.com/12036
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make orphans top level objects instead of panic-ing.
Gabe Black [Fri, 20 Jul 2018 00:12:31 +0000 (17:12 -0700)]
systemc: Make orphans top level objects instead of panic-ing.

When a simulation ends, the sc_objects it contains are destroyed one
by one, not necessarily in hierarchy order. That means that a parent
object can legitimately be destroyed before its children. Instead of
panic-ing when that inevitably happens, this change makes gem5 turn
those children into top level objects.

Change-Id: Icad9c99310fbc3ddcadbbb4f8a990b4fbfe35bdf
Reviewed-on: https://gem5-review.googlesource.com/12035
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement some of the basics of sc_time.
Gabe Black [Thu, 19 Jul 2018 23:53:27 +0000 (16:53 -0700)]
systemc: Implement some of the basics of sc_time.

This is a very incomplete implementation, but is enough to unblock
implementing some other dependent features.

Change-Id: Ibd2f3476fe01389e277c6956d48337f551d14acd
Reviewed-on: https://gem5-review.googlesource.com/12034
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Implement the various sc_module stage callbacks.
Gabe Black [Thu, 19 Jul 2018 22:51:24 +0000 (15:51 -0700)]
systemc: Implement the various sc_module stage callbacks.

This change also gets rid of the SystemC namespace which was
deprecated in favor of sc_gem5.

A few utility functions which check whether certain callbacks have
finished were also implemented. status tracking moved from a global
variable in sc_main.cc to a member of the kernel simobject.

Change-Id: I50967fae9c576fbe45b1faff587aaa824857a289
Reviewed-on: https://gem5-review.googlesource.com/12033
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Avoid dividing by zero in Time::[gs]etTick.
Gabe Black [Tue, 11 Sep 2018 07:59:56 +0000 (00:59 -0700)]
base: Avoid dividing by zero in Time::[gs]etTick.

Those functions used the value SimClock::Int::ns which, if the time
resolution is larger than 1ns, can/will be zero. That will make
getTick always return zero, and setTick divide by zero. This change
modifies those functions so that the math they do avoids using any
integer Ticks per time unit value except for Frequency. It seems
unlikely that the Ticks will increment at less than 1Hz.

Change-Id: I5cc9db14699c00dcbff48e4593b98522b13b4ccd
Reviewed-on: https://gem5-review.googlesource.com/12573
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Correct a small typo in sim/core.(hh|cc).
Gabe Black [Tue, 11 Sep 2018 07:57:34 +0000 (00:57 -0700)]
base: Correct a small typo in sim/core.(hh|cc).

The value GHz with a small z was spelled GHZ with a large z, which was
inconsistent with the other frequency-like values in that namespace.

Change-Id: I55dfc447a5811ae584e46769cd9cadd08bd1e716
Reviewed-on: https://gem5-review.googlesource.com/12572
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agobase: Save and restore the width setting of streams used with cprintf.
Gabe Black [Tue, 11 Sep 2018 07:55:28 +0000 (00:55 -0700)]
base: Save and restore the width setting of streams used with cprintf.

The flags, precision, and fill character were all being saved and
restored, but cprintf might also change the width setting of the
stream, and that wasn't being saved or restored and could leak from
the cprintf statement.

This change adds the code to save and restore that value.

Change-Id: Ibedb26f7f538cd3be4fe0462d2ee4e5efd62bc59
Reviewed-on: https://gem5-review.googlesource.com/12571
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agonet: Fix a bug when receiving fragamented packets
Pin-Yen Lin [Tue, 14 Aug 2018 06:23:25 +0000 (14:23 +0800)]
net: Fix a bug when receiving fragamented packets

In the previous implementation, the function EtherTap::recvReal will only
read one packet when received some ``interrupt'' (explicitly, when async_IO
set to true). When someone tries to send a large message to the simulated
device, the message will be divided to several packets due to packet
fragmentation. In this situation recvReal will only read one packet and
left the other packets in the buffer. This significantly increases the
networking latency. So before reading from socket, I change the socket into
non-blocking mode and keep reading from it until there's no packet left.

Change-Id: Ieb94a8532cd3994862b6f3eb9474caf7ccf617da
Reviewed-on: https://gem5-review.googlesource.com/12338
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agobase: Fix isSubset() for addr ranges with interleaving
Nikos Nikoleris [Wed, 29 Aug 2018 10:36:22 +0000 (11:36 +0100)]
base: Fix isSubset() for addr ranges with interleaving

This change extends isSubset() which checks whether the range is a
subset of an input range to support address ranges with interleaving
and hashing.

Change-Id: I3dc9ceccb189b7c8665de0355f0555fc2c37d872
Reviewed-on: https://gem5-review.googlesource.com/12319
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoconfigs: Use the same address ranges for dir and mem_ctrls
Nikos Nikoleris [Thu, 30 Aug 2018 09:26:31 +0000 (10:26 +0100)]
configs: Use the same address ranges for dir and mem_ctrls

In Ruby, for every directory we create one memory controller for every
range in the memory ranges. Previously the memory controllers and the
directories created their address ranges independently and as a result
a mismatch was possible. In fact, we assinged an interleaved address
range with hasing for the memory controllers while the corresponding
directories would be assigned the same interleaved address range
without hashing.

This change uses the address range of the memory controllers to
populate the list of address ranges for the corresponding directory
and avoid bugs due to code duplication.

Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a
Reviewed-on: https://gem5-review.googlesource.com/12318
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agodev-arm: Make GenericTimer use standard ArmInterruptPin
Giacomo Travaglini [Thu, 30 Aug 2018 16:48:48 +0000 (17:48 +0100)]
dev-arm: Make GenericTimer use standard ArmInterruptPin

This patch is deleting the custom ArchTimer::Interrupt implementation in
favour of the standard ArmInterruptPin.

Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12402
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agodev-arm: Factory SimObject for generating ArmInterruptPin
Giacomo Travaglini [Thu, 30 Aug 2018 15:43:02 +0000 (16:43 +0100)]
dev-arm: Factory SimObject for generating ArmInterruptPin

With this patch the python ArmInterruptPin SimObject matches to the
C++ ArmInterruptPinGen. The latter is in charge of generating
the ArmInterruptPin (which is not a SimObject anymore).
This is meant to ease the generation of ArmInterruptPins: by
not being SimObjects we are not forced to instantiate them
in the configuration script; we can generate them dynamically
instead throughout simulation.

Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12401
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoarm: Use the interrupt adaptor in the PMU
Andreas Sandberg [Thu, 23 Mar 2017 18:54:56 +0000 (18:54 +0000)]
arm: Use the interrupt adaptor in the PMU

Rewrite interrupt handling in the PMU model to use the new interrupt
adaptor.

Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12400
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
6 years agoarm: Add support for tracking TCs in ISA devices
Andreas Sandberg [Thu, 23 Mar 2017 18:57:41 +0000 (18:57 +0000)]
arm: Add support for tracking TCs in ISA devices

ISA devices typically need to keep track of the thread context they
are associated with. Among other things, this is required for
interrupt delivery. Add a BaseISADevice:setThreadContext() method to
wire such models to the right thread context.

Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
6 years agodev, arm: Add misc reg tracing to the generic timer
Andreas Sandberg [Thu, 22 Mar 2018 17:58:59 +0000 (17:58 +0000)]
dev, arm: Add misc reg tracing to the generic timer

Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12398

6 years agodev-arm: Create a getter for ArmInterruptPin ID number
Giacomo Travaglini [Tue, 28 Aug 2018 14:34:34 +0000 (15:34 +0100)]
dev-arm: Create a getter for ArmInterruptPin ID number

A pin owner might want to know which is the irq number
associated with the pin.

Change-Id: I095393d4d25efe13eb2a75a0b0b055d386c2c126
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12298
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem: Make DRAMCtrl a QoS-aware Memory Controller
Matteo Andreozzi [Fri, 4 Aug 2017 10:11:53 +0000 (11:11 +0100)]
mem: Make DRAMCtrl a QoS-aware Memory Controller

This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no
policy" as a default policy.

Change-Id: I48163da8c8208498cf0398b07094cb840272507f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11973
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>