intel/isl: Add an enum for describing auxiliary compression state

This enum describes all of the states that a auxiliary compressed
surface can have.  All of the states as well as normative language for
referring to each of the compression operations is provided in the
truly colossal comment for the new isl_aux_state enum.  There is also
a diagram showing how surfaces move between the different states.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Combine render target resolve code

We have two different bits of resolve code for render targets: one in
brw_draw where it's always been and one in brw_context to deal with sRGB
on gen9.  Let's pull them together.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Be a bit more conservative about certain resolves

There are several places where we were resolving the entire miptree
when we really only needed to resolve a single slice.  Let's avoid the
unneeded resolving.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Move MCS allocation earlier for clears

This way it happens before we call get_aux_state.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Refactor do_single_blorp_clear

Previously, we had two checks for can_fast_clear and a tiny bit of
shared code in between.  This commit pulls all of the fast clear code
together and duplicates the tiny bit that declares some surface structs
and calls blorp_surf_for_miptree.  The duplication is no real loss and
we're about to change the two in slightly different ways.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Take an explicit fast clear op in resolve_color

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Move color resolve on map to intel_miptree_map

None of the other methods such as blit work with CCS either so we need
to do the resolve for all maps.  This change also makes us only resolve
the one slice we're mapping and not the entire image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Inline renderbuffer_att_set_needs_depth_resolve

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Get rid of intel_renderbuffer_resolve_*

There is exactly one caller so it's a bit pointless to have all of this
plumbing.  Just inline it at the one place it's used.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Refactor intel_miptree_resolve_color

The new version now takes a range of levels as well as a range of
layers.  It should also be a tiny bit faster because it only walks the
resolve_map list once instead of once per layer.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Clean up the depth resolve helpers a little

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/surface_state: Images can't handle CCS at all

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Mark depth surfaces as needing a HiZ resolve after blitting

Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

st_glsl_to_tgsi: cleanup variable storage search.

I forgot to put the cleanup in earlier.

Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/main: fix gl_buffer_index enum comparison

For clang, enums are unsigned by default and gives the following warning:

external/mesa3d/src/mesa/main/buffers.c:764:21: warning: comparison of constant -1 with expression of type 'gl_buffer_index' is always false [-Wtautological-constant-out-of-range-compare]
      if (srcBuffer == -1) {
          ~~~~~~~~~ ^  ~~

Replace -1 with an enum value to fix this.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

glsl: fix bounds check in blob_overwrite_bytes

clang gives a warning in blob_overwrite_bytes because offset type is
size_t which is unsigned:

src/compiler/glsl/blob.c:110:15: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare]
   if (offset < 0 || blob->size - offset < to_write)
       ~~~~~~ ^ ~

Remove the less than 0 check to fix this.

Additionally, if offset is greater than blob->size, the 2nd check would
be false due to unsigned math. Rewrite the check to avoid subtraction.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>

st_glsl_to_tgsi: replace variables tracking list with a hash table

This removes the linear search which is fail when number of variables
goes up to 30000 or so.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st_glsl_to_tgsi: rewrite rename registers to use array fully.

Instead of having to search the whole array, just use the whole
thing and store a valid bit in there with the rename.

Removes this from the profile on some of the fp64 tests

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st_glsl_to_tgsi: bump index back up to 32-bit

with some of the fp64 emulation, we are seeing shaders coming in with
> 32K temps, they go out with 40 or so used, but while doing register
renumber we need to store a lot of them.

So bump this fields back up to 32-bit.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

util/u_queue: fix a use-before-initialization race for queue->threads

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac/nir: remove another unused variable

Declared by each loop already.
Trivial.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>

radv/meta: remove an unused variable

Trivial.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: convert several ifs to a switch

Also solve "outinfo may be used uninitialized" warning by putting in an
unreachable().

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: mark some arguments const

Most functions are only inspecting nir, so nir related arguments can be
marked const. Some more can be done if/when some nir changes are
accepted.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: Use libdrm to get chipset name

v2: Add a func pointer to radeon_winsys to support radeon later.

Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

util: Add extern c to u_dynarray.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Delete nir_array.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Port to u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Remove unused include

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Port nir_array functionality to u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Remove unused includes and convert to lower-case memory ops

Also, prepare for the next commit by correcting some coding style
changes. This should be all non-functional changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Move u_dynarray to src/util

This will be used as the basis for unification

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium: Add missing includes

These will need to be in place to avoid regressions when
removing these includes from the u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

radeonsi: update clip_regs on shader state changes only when it's needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: precompute some fields for PA_CL_VS_OUT_CNTL in si_shader_selector

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add a new helper si_get_vs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: isolate real framebuffer changes from the decompression passes (v3)

When a stencil buffer is part of the framebuffer state, it is
decompressed but because it's bindless, all draw calls set
stencil_dirty_level_mask to 1.

v2: Marek - set the flags outside the loop
          - also clear and set framebuffer.do_update_surf_dirtiness there
          - do it in the DB->CB copy path too
v3: Marek - save and restore the do_update_surf_dirtiness flag

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: do EarlyCSEMemSSA LLVM pass

so that LLVM IR looks like CSE has been run on it. It's also recommended
by the instruction combining pass.

This also fixes:
- GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 (crash)
- piglit/spec/arb_shader_ballot/execution/fs-readFirstInvocation-uint-loop (fail)

The code size decrease is positive, the register usage isn't. There is
a decrease in VGPR spilling for Tomb Raider, but increase in DiRT Showdown
and GRID Autosport.

EarlyCSEMemSSA has a -0.01% change in code size compared EarlyCSE.

SGPRS: 1935420 -> 1938076 (0.14 %)
VGPRS: 1645504 -> 1645988 (0.03 %)
Spilled SGPRs: 2493 -> 2651 (6.34 %)
Spilled VGPRs: 107 -> 115 (7.48 %)
Private memory VGPRs: 1332 -> 1332 (0.00 %)
Scratch size: 1512 -> 1516 (0.26 %) dwords per thread
Code Size: 61981592 -> 61890012 (-0.15 %) bytes
Max Waves: 371847 -> 371798 (-0.01 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove 8 bytes from si_shader_key

We can use a union in si_shader_key::mono.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move PSIZE and CLIPDIST unique IO indices after GENERIC

Heaven LDS usage for LS+HS is below. The masks are "outputs_written"
for LS and HS. Note that 32K is the maximum size.

Before:
  heaven_x64: ls=1f1 tcs=1f1, lds=32K
  heaven_x64: ls=31 tcs=31, lds=24K
  heaven_x64: ls=71 tcs=71, lds=28K

After:
  heaven_x64: ls=3f tcs=3f, lds=24K
  heaven_x64: ls=7 tcs=7, lds=13K
  heaven_x64: ls=f tcs=f, lds=17K

All other apps have a similar decrease in LDS usage, because
the "outputs_written" masks are similar. Also, most apps don't write
POSITION in these shader stages, so there is room for improvement.
(tight per-component input/output packing might help even more)

It's unknown whether this improves performance.

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

svga: Always set the alpha value to 1 when sampling using an XRGB view

If the XRGB view is sampling from an ARGB svga format, change
PIPE_SWIZZLE_W to PIPE_SWIZZLE_1 for all channels.
Previously we unconditionally set PIPE_SWIZZLE_1 on the alpha channel which
could be both insufficient and incorrect.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Fix imported surface view creation

When deciding to create a view with or without an alpha channel we need to
look at the SVGA3D format and not the PIPE format.

This fixes the glx-tfp piglit test for dri3/xa.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Set alpha to 1 for non-alpha views

Gallium RGB textures may be backed by imported ARGB svga3d surfaces. In those
and similar cases we need to set the alpha value to 1 when sampling.

Fixes piglit glx::glx-tfp

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Allow format differences in 16-bit RGBA surface sharing

For the purpose of surface sharing, treat SVGA3D_R5G6B5 and
SVGA3D_B5G6R5_UNORM as identical formats.
This fixes the following piglit tests with dri3/xa:

glx@glx-visuals-depth -pixmap
glx@glx-visuals-stencil -pixmap

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Deepak Singh Rawat <drawat@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

dri/vmwgfx: Disable a couple of glx extensions also for Ubuntu unity / compiz

It appears like the GLX_EXT_buffer_age extension also prevents Compiz /
Ubuntu Unity from performing partial buffer swaps when it otherwise
feels like doing so. So try to get them back again. We also disable
GLX_OML_sync_control since it appears it had a favourable impact on
gnome-shell.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>

dri: Turn of a couple of glx extensions for gnome-shell on vmwgfx.

Increases performance on vmwgfx since we're avoiding full buffer damage and
since we can't sync to vertical retrace anyway.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/dri: Allow gallium drivers to turn off two GLX extensions

Allow gallium drivers to turn off GLX_EXT_buffer_age and
GLX_OML_sync_control if needed, using driconf.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

dri: Optionally turn off a couple of GLX extensions based on driconf options

With GLX_EXT_buffer_age turned on, gnome-shell will use full-screen damage
with GLX, which severely hurts performance with architectures that emulate
page-flips with copies. Like vmware. We would like to be able to turn off that
extension. Similarly, typically the GLX_OML_sync_control doesn't make much
sense on a virtual architecture since we don't really sync to the host's
vertical retrace. We'd like to be able to turn it off as well.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/dri: Allow dri users to query also driver options

There will be situations where we want to control, for example, the
GLX behaviour based on applications and drivers. So allow DRI users access
to the driver options.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: clean up decompress blend state names

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: clean up a misleading statement from the old days

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE

It's always good to have fewer decompress blits.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable TC-compatible stencil compression on VI

Most things are in place. Ideally we won't see decompress blits for stencil
anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: don't keep framebuffer state in st_context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: cache pipe_surface for GL_FRAMEBUFFER_SRGB changes

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: use gl_driver_flags::NewFramebufferSRGB

also call st_init_driver_flags when st_context is initialized.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add gl_driver_flags::NewFramebufferSRGB

_NEW_BUFFERS updates too much stuff.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: prevent a race when the previous shader's main part is missing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: wait for main part compilation of 1st shaders of merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix LS scratch buffer support without TCS for GFX9

LS is merged into TCS. If there is no TCS, LS is merged into fixed-func
TCS. The problem is the fixed-func TCS was ignored by scratch update
functions, so LS didn't have the scratch buffer set up.

Note that Mesa 17.1 doesn't have merged shaders.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move streamout state update out of si_update_shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove dead code in declare_input_fs

Colors are interpolated in the PS prolog. This was never used.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move handling of DBG_NO_OPT_VARIANT into si_shader_selector_key

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use a compiler queue with a low priority for optimized shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util/u_queue: add an option to set the minimum thread priority

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: decrease the number of compiler threads to num CPUs - 1

Reserve one core for other things (like draw calls).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: drop unfinished shader compilations when destroying shaders

If we enqueue too many jobs and destroy the GL context, it may take
several seconds before the jobs finish. Just drop them instead.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util/u_queue: add a way to remove a job when we just want to destroy it

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

freedreno/a5xx: set SP_BLEND_CONTROL properly

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: LRZ support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: drop timestamp field

unused.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: refactor out helper for LRZ flush

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: reshuffle FD_MESA_DEBUG bitmask

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium/u_blitter: use 2D_ARRAY for cubemap blits if possible

so that we can use TXF.

The cubemap blit pixel shader code size: 148 -> 92 bytes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/u_blitter: use TXF if possible

This fixes piglit:
    arb_texture_view-rendering-r32ui

TEX (image_sample) flushes denorms to 0 with FP32 textures on GCN, but such
a texture can contain integer data written using an integer render view.
If we do a transfer blit with TEX, denorms are flushed to 0. Luckily,
TXF (image_load) doesn't do that.

TXF also doesn't need to load the sampler state, so blit shaders don't have
to do s_load_dwordx4.

TXF doesn't do CLAMP_TO_EDGE, so it can only be used if the src box is
in bounds, or if we clamp manually (this commit doesn't).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/u_blitter: use TEX_LZ if it's supported

The sampler views always have first_level == last_level.
Now radeonsi doesn't have to use the WQM. (a few SALU removed)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/util: add _LZ and TXF options to simple shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/ureg: add TEX/TXF_LZ opcodes to ureg

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965: Use BLORP for all HiZ ops

BLORP has been capable of doing gen8-style HiZ ops for a while now.  We
might as well start using it.  The one downside is that this may cause a
bit more state emission since we still re-emit most things for BLORP.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

blorp: Use FullSurfaceDepthandStencilClear for blorp_hiz_op

The blorp_hiz_op entrypoint always acts on a full subresource of a HiZ
buffer so we can just set the flag unconditionally.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move the post-HiZ-clear flush/stall to intel_hiz_exec

This also changes it to be predicated so we only do the flush/stall on
clears and HiZ resolves.  The docs only say it's needed for clears but
empirical evidence says it's also needed for HiZ resolves.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Plumb through access to the workaround BO

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101283
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/blorp: Move the depth cache flush outside of BLORP

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp: Refactor the HiZ op interface

This commit does a few things:

 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix.
 2) Switch parameters to uint32_t to match the rest of blorp.
 3) Take a range of layers and loop internally.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Inline gen6_blorp_exec

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Perform HiZ flush/stall prior to HiZ resolves

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move the pre-depth-clear flush/stalls to intel_hiz_exec

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Take a layer range in intel_hiz_exec

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/miptree: Store fast clear colors in an isl_color_value

This commit, out of necessity, makes a number of changes at once:

 1) Changes intel_mipmap_tree to store the clear color for both color
    and depth as an isl_color_value.

 2) Changes the depth/stencil emit code to do the format conversion of
    the depth clear value on Haswell and earlier instead of pulling a
    uint32_t directly from the miptree.

 3) Changes ISL's depth/stencil emit code to perform the format
    conversion of the depth clear value on Haswell and earlier instead
    of assuming that the depth value in the float is pre-converted.

 4) Changes blorp to pass the depth value through as a float.

 5) Changes the Vulkan driver to pass the depth value to blorp as a
    float rather than a uint.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

dri3/GLX: Fix drawable invalidation v2

A number of internal VMware apitrace traces image comparisons fail with
dri3 because the viewport transformation becomes incorrect after an X
drawable resize. The incorrect viewport transformation sometimes persist
until the second draw-call after a swapBuffer.

Comparing with the dri2 glx code there are a couple of places where dri2
invalidates the drawable in the absence of server-triggered invalidation,
where dri3 doesn't do that. When these invalidation points are added to
dri3, the image comparisons become correct.

v2:
Addressed review comment by Michel Dänzer.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com>

i965: Fix alpha to one with dual color blending.

The BLEND_STATE documentation says that alpha to one must be disabled
when dual color blending is enabled.  However, it appears that it simply
fails to override src1 alpha to one.

We can work around this by leaving alpha to one enabled, but overriding
SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.  This appears to be
what the other driver does, and it looks like it works despite the
documentation saying not to do it.

Fixes spec/ext_framebuffer_multisample/alpha-to-one-dual-src-blend *
Piglit tests.

v2: Add UNUSED to shut up warning on generations which don't use this.

Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: add KHR_no_error support for glTexSubImage*D()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add texsubimage() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: make _mesa_texture_sub_image() static

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: rename texsubimage() to texsubimage_err()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add KHR_no_error support for glCopyImageSubData()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add copy_image_subdata() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: add prepare_target() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

mesa: rename prepare_target() to prepare_target_err()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>