intel/blorp: Use isl_get_interleaved_msaa_px_size_sa

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a helper for getting the size of an interleaved pixel

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Handle 3D surfaces in convert_to_single_slice

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Fix an assert in get_intratile_offset_sa

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Fix the early return condition in convert_to_single_slice

The convert_to_single_slice operation is *mostly* idempotent.  The only
non-repeatable thing it does is that, when it sets the intratile offset
fields, it just overwrites them instead of doing a += operation.  This is
supposed to be ok because we have an early return at the top that should
make it bail of the surface is already a single slice.  Unfortunately, the
if condition has been broken ever since it was first added in 96fa98c18.
This commit fixes the condition and adds an assert to ensure we don't stomp
any non-zero intratile offsets.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Use the surface format for computing offsets

If we use the view format, it may be an uncompressed view of a compressed
image which throws things off.  Since we're computing offsets of images, we
want the actual surface offset anyway.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Don't assume R8_UINT in convert_to_single_slice

We're going to use it for more than just stencil textures

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Take a destination swizzle in blorp_blit

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Take an isl_swizzle instead of a SWIZZLE

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles

This should be more compact than the enum isl_channel_select[4] that we
were using before.  It's also very convenient because we already had such a
structure in the Vulkan driver we just needed to pull it over.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

docs: Add OES_tessellation_shader to the release notes.

docs: Mark OES_tessellation_shader as done.

st/mesa: fix is_scissor_enabled when X/Y are negative

Similar to commit 49c24d8a24 ("i965: fix noop_scissor range issue on
width/height") - take the X/Y into account to determine whether the
scissor covers the whole area or not.

Fixes the recently-added gl-1.0-scissor-depth-clear-negative-xy piglit
test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>

android: add support for libmesa_amdgpu_addrlib

Android porting of the following commits:

f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"

This patch fixes android building errors

Reviewed-by: Dave Airlie <airlied@redhat.com>

u_endian: add android to glibc clause

Tested-by: Mauro Rossi <issor.oruam@gmail.com>

Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
was erroneous because GL has a separate limit, GL_MAX_FRAMEBUFFER_LAYERS
which guards the number of layers you are allowed to render into.

The GL 4.5 spec says:

   "The framebuffer attachment point attachment is said to be framebuffer
   attachment complete if [...] all of the following conditions are true:

      [...]

      If image is a three-dimensional, one- or two-dimensional array, or
      cube map array texture and the attachment is layered, the depth or
      layer count of the texture is less than or equal to the value of the
      implementation-dependent limit MAX_FRAMEBUFFER_LAYERS."

and goes on to say that "framebuffer complete" requires all attachments to
be "framebuffer attachment complete".

On Sandy Bridge, we set GL_MAX_FRAMEBUFFER_LAYERS to 512 so creating a 3D
texture bigger than 512 is fine; you just can't render into all of the
slices at once.

Fixes ES3-CTS.gtf.GL3Tests.npot_textures.npot_tex_image on Sandy Bridge

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

intel/blorp: Handle the 512 layers restriction on Sandy Bridge

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/isl: Treat 3-D textures as 2-D arrays for rendering

In particular, this means that isl_view::base_array_layer and
isl_view::array_len get applied to 3-D textures but only when rendering.
We were already applying isl_view::base_array_layer for rendering into 3-D
textures so this isn't a huge deviation.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

aubinator: Simplify gen_disasm_create()'s devinfo handling

Copy the whole devinfo structure instead of just few fields (Ken)

Earlier, copied only couple of fields which added more code. So,
simplify code by copying the whole structure.

Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

aubinator: Fix compiler warning

Add 'const' qualifier to gen_field_iterator::p pointer (Ken)

Signed-off-by: Sirisha Gandikota <Sirisha.Gandikota@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/va: also honors interlaced preference when providing a video format

This fixes a crash when using the prefered video format with vaapisink
on Nvidia hardwares.
Also caught by the following assert:
  nouveau_vp3_video.c:91: Assertion `templat->interlaced' failed.

TEST= gst-launch-1.0 videotestsrc ! video/x-raw, format=NV12 ! vaapisink

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Víctor Manuel Jáquez Leal <vjaquez@igalia.com>
Tested-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

tgsi: document semantics for compute shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: Enable OES/EXT_tessellation_shader for ES 3.1 + ARB_tess drivers.

Drivers which support ARB_tessellation_shader and ES 3.1 now will
expose OES_tessellation_shader and EXT_tessellation_shader as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

radeonsi: don't preload constants at the beginning of shaders

LLVM can CSE the loads, thus we can always re-load constants before each
use. The decrease in SGPR spilling is huge.

The best improvements are the dumbest ones.

26011 shaders in 14651 tests
Totals:
SGPRS: 1453346 -> 1251920 (-13.86 %)
VGPRS: 742576 -> 728421 (-1.91 %)
Spilled SGPRs: 52298 -> 16644 (-68.17 %)
Spilled VGPRs: 397 -> 369 (-7.05 %)
Scratch VGPRs: 1372 -> 1344 (-2.04 %) dwords per thread
Code Size: 36136488 -> 36001064 (-0.37 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 219315 -> 222221 (1.33 %)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel/blorp: Add a TODO file

This provides a nice little place to share notes on what still needs to be
done and/or would be nice to have in BLORP.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>

i965: check for GL_TEXTURE_EXTERNAL_OES at miptree_create_for_teximage

Forgotten on commit "i965: Fix calculation of the image height at start level".

Thanks to Ilia Mirkin for point it.

Fixes the following regressions on Haswell and Broadwell:
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimpleUnassociated (crash back to pass)
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimple (crash back to fail)
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestVertexShader (crash back to fail)

https://bugs.freedesktop.org/show_bug.cgi?id=97761

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gbm: fix potential NULL deref of mapImage/unmapImage.

The mapImage/unmapImage functions of DRIimage extension can be NULL,
so we should add additional check for them.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Chuanbo Weng <chuanbo.weng@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

Remove GL_GLEXT_PROTOTYPES guards from non-ext headers.

A earlier sync with the Khronos headers added _extension_ prototype
guards to all the GLES2/3/31/32 core entry points. Effectively breaking
all the applications that aim to be portable and do not set the define.

The issue has been reported to Khronos (internal bugzilla #14206) and is
being worked on. Until updated/fixed headers are released locally fix
the issue.

The following report is when building weston.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97773

Cc: Armin Krezović <krezovic.armin@gmail.com>
Cc: Emmanuel Gil Peyrot <emmanuel.peyrot@collabora.com>
Cc: Pekka Paalanen <ppaalanen@gmail.com>
Fixes: 6a5504de2fb ("Update Khronos-supplied headers to r33100")
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

aubinator: rework print_help()

Rather than using platform specific methods to retrieve the program
name pass it explicitly. The function is called directly from main().

Similarly - basename comes in two versions POSIX (can modify string,
always pass a copy) and GNU (never modifies the string).

Just printout the complete program name, esp. since the program is not
meant to be installed. Thus using $basename is unlikely to work, not to
mention it is misleading.

Reported-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>

docs: Note MESA_configless_context as superseded

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>

egl: Rename MESA_configless_context bit to KHR_no_config_context

Keep the old name in the extension string, but refer to the KHR
extension internally.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>

egl: QueryContext on a configless context returns zero

MESA_configless_context does not specify the interaction with
QueryContext at all, and the code to generate an error in this case
predates the Mesa extension. Since EGL_NO_CONFIG_{KHR,MESA} are
numerically identical there's no way to distinguish which one the
application asked for, so use the KHR behaviour.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Adam Jackson <ajax@redhat.com>

st/va: enable vbr rate control for vaapi encode

This patch enables variable bit-rate for vaapi encoding. According to va.h,
target bit-rate equals to maximum bit-rate multiplies by target_percentage.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl/rbsp: match initial escaped bits with valid in the buffer

Otherwise the check for the three byte will not make sense.

Signed-off-by: Leo Liu <leo.liu@amd.com>

egl: fix gcc warning braces around scalar initializer

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

winsys/radeon: rename nrelocs, crelocs to max_relocs, num_relocs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon: don't pre-allocate the relocations array

It's really not necessary. Switch to an exponential resizing strategy.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon: remove unused radeon_cs_context::priority_usage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: remove amdgpu_cs_lookup_buffer

The radeonsi driver doesn't and shouldn't care about the buffer index.
Only the virtual addresses matter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: remove unused field domains from amdgpu_cs_buffer

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: remove initial buffer list allocation

It's really not necessary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: extract adding a new buffer list entry into its own function

While at it, try to be a little more robust in the face of memory allocation
failure.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: use only one fence per BO

The fence that is added to the BO during flush is guaranteed to be
signaled after all the fences that were in the fences array of the BO
before the flush, because those fences are added as dependencies for the
submission (and all this happens atomically under the bo_fence_lock).

Therefore, keeping only the last fence around is sufficient.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: add do_winsys_deinit function

The idea is to have matching init/deinit functions so that deinit can be
re-used for cleanup in the error path of amdgpu_winsys_create.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: clean up error paths in amdgpu_winsys_create

No need to call pb_cache_deinit, because the cache hasn't been initialized
at that point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: page alignment for buffers is unnecessary

In some places (e.g. shader program pointers) we require 256 bytes alignment.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon/winsyses: remove #includes of pb_bufmgr.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/rbc: Clarify rational given for shader image resolves

Original commit added documentation explaining lossless compression
case:

commit 56f29911ec9da25c78fbd3d4945d499e65ca4b5a
Author: Topi Pohjolainen <topi.pohjolainen@intel.com>
Date:   Tue Feb 2 10:00:41 2016 +0200

    i965: Add a flag telling color resolve pass to ignore CCS_E

It, however, easily gives the impression that the sole purpose
of the intel_miptree_resolve_color() is to address lossless
compression. Original intention is to document the lack of
INTEL_MIPTREE_IGNORE_CCS_E flag given for the resolve call.

This patch fixes this along with a typo found spotted further
down.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp: Use hw generetad primitive copies for layered clears

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp: Sanity check all layers before actual clear

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp: Add plumbing for setting color clear layer count

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp: Allow multiple layers

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp: Instruct vertex fetcher to provide prim instance id

This will indicate target layer (Render Target Array Index) needed
for layered clears.

v2: Use 3DSTATE_VF_SGVS for gen8+

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/rbc: Allocate mcs directly

such as we do for compressed msaa. In case of non-compressed simgle
sampled buffers the allocation of mcs is deferred until there is
actually a clear operation that needs the mcs.
In case of render buffer compression the mcs buffer always needed
and there is no real reason to defer the allocation. By doing it
directly allows to drop quite a bit unnecessary complexity.

Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent
patches will re-use it and it seemed cleaner to leave it instead
of removing and re-introducing.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

isl/gen8+: Allow 1D and 3D auxiliary surfaces

Otherwise once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), assert starts to fire in
piglit case: tex3d. The test uses depth of one which is in fact
supported even now.

v2 (Jason): Allow also 1D case as there is nothing in the specs
            constraining it either.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Add sanity check for non-compressible texture views

v2: Fix missing inline declaration

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/rbc: Consult rb settings for texture surface setup

Once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), one gets regression in:

GL45-CTS.texture_barrier_ARB.same-texel-rw

Setting the auxiliary surface for both sampling engine and data
port seems to fix this. I haven't found any hardware documentation
backing this though.

v2 (Jason): Prepare also for the case where surface is sampled with
            non-compressible format forcing also rendering without
            compression.
v3: Split asserts and decision making.
v4: Detailed comment provided by Jason explaining the need for using
    auxiliary buffer for texturing when the same surface is also
    used as render target.
    Added check for existence of renderbuffer before considering if
    underlying miptree matches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Track non-compressible sampling of renderbuffers

v3:
   - Actually set the flags when needed instead of falsely
     overwriting them (Jason).
   - Use more generic name for flag (dropped RENDERBUFFER)
   - Consult also shader images
v4:
   - Consult only lossless compressd shader images

v5:
   - Check the existence of renderbuffer before considering
     if it matches the given miptree

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Replace boolean rb surface state setup argument with flags

And add plumbing to provide it all the way to surface state emitter.
This is not used yet but will be in subsequent patches to carry
additional constraints.

v2 (Jason): Use uint32_t instead of int as the type

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/rbc: Allow integer formats as advertised in isl_format.c

Blorp consults brw_is_color_fast_clear_compatible() to see if any
restrictions apply for fast clear in addition to the capablities
advertised in isl_format.c::format_info[]. On Gen8+ integer formats
are backlisted for plain old fast clear but there is no reason why
lossless compression shouldn't be supported. In fact, lossless
compression of integer formats is already supported for normal
render paths.

This patch prepares for dropping the delayed allocating of the mcs
buffer for lossless compression. Until now the skip of fast clear
also prevented the mcs being allocated and hence the lossless
compression being effectively turned off for integer formats.
Once the mcs buffer is allocated beforehand, the assertion addressed
here would start triggering.

v2: Drop the assert instead of relaxing it (Jason)
    Fix typo while at it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: remove unused variable at intel_miptree_create_for_teximage

After commit "i965: Fix calculation of the image height at start level", it is
not needed. This commit removes the "warning: unused variable ‘i’" warning.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa/glsl: Move string_to_uint_map into the util folder

This clears the last bits of the usecases of the hash table
located in mesa/program, allowing us to remove it.

V2: Rebase on top of changes to Makefile.sources

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert glcpp-parse to the util hash table

And change the include in glcpp.h accordingly.

V2: Whitespace fix

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert loop analysis to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: Convert symbol table to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert varying test to the util hash table

V2: remove now unused ht_count_callback() (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert output read lowering to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert interface block lowering to the util hash table

V2: move comment to correct location (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert if lowering to use a set

Also do some minor whitespace cleanups

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert linker to the util hash table

We are getting the util hash table through the include in
program/hash_table.h for the moment until we migrate the
string_to_uint_map to a separate file.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert link_varyings to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Change link_functions to use a set

The "locals" hash table is used as a set, so use a set to
avoid confusion and also spare some minor memory.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert recursion detection to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert constant_expression to the util hash table

V2: Fix incorrect ordering on hash table insert

V3: null check value returned by _mesa_hash_table_search()
    (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert ast_to_hir to the util hash table

V2: Rebase to the adaption of new hashing functions

V3: move previous_label declaration to where it is used
    (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert ir_clone to the util hash table

V2: add braces to multiline if (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: Convert function inlining to the util hash table

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: Convert string_to_uint_map to the util hash table

And remove the now unused hash_table_replace.

V2: Actually do the equivalent thing, and don't leak memory

V3: fix minor typo in comment (Timothy Arceri)

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

util: Move hash_table_call_foreach to util hash table

It is included through the util/hash_table include in
the program hash_table, so this should be safe.
This will be needed when we start converting each use of
the program_hash_table, as some places need this function.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: Remove prog_hash_table.c

Here we make the prog_hash_table functionally equivalent to
the one in util by wrapping the remaing functions that differ.

We also move the functions to the header so we can remove the c
file.

This enables us to do a step-by-step replacement of the table.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: Remove unused hash table includes

This should prevent us from rebuilding the world.

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

freedreno/a3xx: disable filtering for texture buffers and int textures

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/clover: Define __OPENCL_VERSION__ on the device side

This is required by the OpenCL standard.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>

gm107/ir: allow indirect inputs to be loaded by frag shader

Looks like the GM107 IPA op does not allow a separate offset when
using an indirect register. Instead we must use AL2P like we do for
indirect vertex operations on Kepler+.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gm107/ir: AL2P writes to a predicate register

We have to force it to write to predicate 7 (aka PT) in order for it not
to mess up another predicate. Unclear what would be returned in the
predicate, perhaps an error code for out-of-bounds requests. Blob
doesn't seem to check it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org

i965: Fix calculation of the image height at start level

- Fixes CTS tests:

* GL44-CTS.shader_image_size.advanced-nonMS-cs-float
* GL44-CTS.shader_image_size.advanced-nonMS-cs-int
* GL44-CTS.shader_image_size.advanced-nonMS-cs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-gs-float
* GL44-CTS.shader_image_size.advanced-nonMS-gs-int
* GL44-CTS.shader_image_size.advanced-nonMS-gs-uint
* GL44-CTS.shader_image_size.advanced-nonMS-tes-float
* GL44-CTS.shader_image_size.advanced-nonMS-tes-int
* GL44-CTS.shader_image_size.advanced-nonMS-tes-uint
* GL44-CTS.shader_image_size.advanced-nonMS-vs-float
* GL44-CTS.shader_image_size.advanced-nonMS-vs-int
* GL44-CTS.shader_image_size.advanced-nonMS-vs-uint

v1: (written by Dave Airlie) Always shift height images for levels.
Fixed the CTS test.

v2: Only shift height if the texture is not an 1D_ARRAY,
it fixes assertion in GL44-CTS.texture_view.gettexparameter
due to the original patch (Antia).

v3: Remove the loop. Do not shift height either for 1D textures.
Use an explicit switch and add an assertion (levels == 0) for
multisampled textures (Jason).

v4: Rectangle textures can not have levels either (Ilia Mirkin).

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Antia Puentes <apuentes@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: flush TC L2 before using a compute indirect buffer

There is no known test for this.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix the VGT performance tweak for small instances

Based on the VGT spec.

The Vulkan driver doesn't do it optimally and they plan to fix it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove the cache_flush atom

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: replace OUT_CS with radeon_emit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/radeon: replace OUT_CS with radeon_emit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

doc: document GALLIUM_DRIVER

v2: Add dot at end of sentence

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

egl/android: Set EGL_MAX_PBUFFER_WIDTH and EGL_MAX_PBUFFER_HEIGHT

Set config attributes EGL_MAX_PBUFFER_WIDTH and EGL_MAX_PBUFFER_HEIGHT to
hard-coded non-zero values. These two attributes are required on Android.

v2: use _EGL_MAX_PBUFFER_WIDTH/HEIGHT from egldefines.h
    (based on discussion on the first version)

Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

android: depend on libmesa_genxml from i965 Android.gen.mk

Static library dependency is required to pull the generated
XML headers into the generated C file.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: release GLSL IR in LinkShader after it's not needed

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

glsl: use hash instead of exec_list in copy propagation

This change makes copy propagation pass faster. Complete link time
spent in test case attached to bug 94477 goes down to ~400 secs from
over 500 secs on my HSW machine. Does not fix the actual issue but
brings down the total. No regressions seen in CI.

v2: do not leak hash_table structure

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Fail the shader compile instead of asserting when we can't spill

Blorp doesn't handle spilling so we set allow_spilling to false in that
case.  The blorp 16x MSAA resolve shader spills in 16-wide but not 8-wide.
This commit makes it so that we fail the 16-wide compile and successfully
fall back to 8-wide instead of just assert-failing when trying to compile
the 16-wide shader.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

nir/gcm: Add global value numbering support

Unlike the current CSE pass, global value numbering is capable of detecting
common values even if one does not dominate the other.  For instance, in
you have

if (...) {
   ssa_1 = ssa_0 + 7;
   /* use ssa_1 */
} else {
   ssa_2 = ssa_0 + 7;
   /* use ssa_2 */
}

Global value numbering doesn't care about dominance relationships so it
figures out that ssa_1 and ssa_2 are the same and converts this to

if (...) {
   ssa_1 = ssa_0 + 7;
   /* use ssa_1 */
} else {
   /* use ssa_1 */
}

Obviously, we just broke SSA form which is bad.  Global code motion,
however, will repair this for us by turning this into

ssa_1 = ssa_0 + 7;
if (...) {
   /* use ssa_1 */
} else {
   /* use ssa_1 */
}

This intended to eventually mostly replace CSE.  However, conventional CSE
may still be useful because it's less of a scorched-earth approach and
doesn't require GCM.  This makes it a bit more appropriate for use as a
clean-up in a late optimization run.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/gcm: Call nir_metadata_preserve

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r300g: Set R300_VAP_CNTL on RSxxx to avoid triangle flickering

On the RSxxx chip series, HW TCL is missing and r300_emit_vs_state()
is never called.

However, if R300_VAP_CNTL is never set, the hardware (at least the
RS690 I tested this on) comes up with rendering artifacts, and
parts that are uploaded before this "fix" remain broken in VRAM.
This causes artifacts as in fdo#69076 ("triangle flickering").

It seems like this setup needs to happen at least once after power on
for 3D rendering to work properly. In the DDX with EXA, this happens in
RADEON_SWITCH_TO_3D() when processing an XRENDER Composite or an
Xv request. So playing back a video or starting a GTK+2 application
fixes 3D rendering for the rest of the session. However, this auto-fix
doesn't happen when EXA is not used, such as with GLAMOR or Wayland.

This patch ensures the register is configured even in absence of
the DDX's EXA module.

The register setting is taken from:
  xf86-video-ati  --  RADEONInit3DEngineInternal()
  mesa/src/mesa/drivers/dri/r300  --  r300EmitClearState()

Tested on RS690.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Max Staudt <mstaudt@suse.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>