mesa.git
9 years agonir: Add algebraic opt for no-op iand.
Eric Anholt [Fri, 31 Jul 2015 16:12:48 +0000 (09:12 -0700)]
nir: Add algebraic opt for no-op iand.

I lazily generated some of these in VC4 NIR lowering.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agovc4: Don't bother saturating the dst color for blending.
Eric Anholt [Sat, 1 Aug 2015 00:08:46 +0000 (17:08 -0700)]
vc4: Don't bother saturating the dst color for blending.

Since we just pulled it out of the destination as 8-bit unorm, we know
it's in [0, 1] already.

shader-db:
total instructions in shared programs: 100040 -> 98208 (-1.83%)
instructions in affected programs:     14084 -> 12252 (-13.01%)

9 years agovc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.
Eric Anholt [Fri, 31 Jul 2015 18:46:56 +0000 (11:46 -0700)]
vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.

Previously, SFU values always moved to a temporary, and TLB color reads
and texture reads always lived in r4.  Instead, we can have these results
just be normal temporaries, and the register allocator can leave the
values in r4 when they don't interfere with anything else using r4.

shader-db results:
total instructions in shared programs: 100809 -> 100040 (-0.76%)
instructions in affected programs:     42383 -> 41614 (-1.81%)

9 years agovc4: Drop a dead prototype.
Eric Anholt [Fri, 31 Jul 2015 17:02:45 +0000 (10:02 -0700)]
vc4: Drop a dead prototype.

9 years agoRevert "nir: Use a single bit for the dual-source blend index"
Eric Anholt [Wed, 5 Aug 2015 00:18:43 +0000 (17:18 -0700)]
Revert "nir: Use a single bit for the dual-source blend index"

This reverts commit ab5b7a0fe659ff6f9c1885d5cb047b6531959506.  We use more
than one bit of value in tgsi_to_nir.

9 years agofreedreno/a4xx: add independent blend function support
Rob Clark [Sat, 1 Aug 2015 20:17:49 +0000 (16:17 -0400)]
freedreno/a4xx: add independent blend function support

needed for MRT

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno/a4xx: MRT support
Rob Clark [Fri, 31 Jul 2015 19:32:58 +0000 (15:32 -0400)]
freedreno/a4xx: MRT support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: move the half-precision logic into core
Rob Clark [Fri, 31 Jul 2015 18:34:19 +0000 (14:34 -0400)]
freedreno: move the half-precision logic into core

Both a3xx and a4xx need the same logic to decide if half-precision can
be used for blit shaders.  So move it to core and simplify things a bit
with a helper that considers all render targets.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: simplify/cleanup resource status tracking
Rob Clark [Fri, 31 Jul 2015 16:07:24 +0000 (12:07 -0400)]
freedreno: simplify/cleanup resource status tracking

Collapse dirty/reading bools into status bitmask (and drop writing which
should really be the same as dirty).  And use 'used_resources' list for
all tracking, including zsbuf/cbufs, rather than special casing the
color and depth/stencil buffers.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: fix stream-out caps vec4->components
Rob Clark [Fri, 31 Jul 2015 14:54:23 +0000 (10:54 -0400)]
freedreno: fix stream-out caps vec4->components

Should be in units of components, not vec4's

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agofreedreno: small bit of cleanup about max rendertargets
Rob Clark [Fri, 31 Jul 2015 13:36:31 +0000 (09:36 -0400)]
freedreno: small bit of cleanup about max rendertargets

We hard-coded 4 or 8 as the max in various places.  Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
9 years agoglx: Use _mesa_lroundevenf() in glPixelStoref().
Matt Turner [Mon, 13 Jul 2015 01:05:58 +0000 (18:05 -0700)]
glx: Use _mesa_lroundevenf() in glPixelStoref().

Functional change in which way half-way cases are rounded from towards
positive-infinity to even. The spec says "the passed value is rounded to
the nearest integer". Removes another case of bad half-up rounding.

9 years agoutil: Use SSE intrinsics in _mesa_lroundeven{f,}.
Matt Turner [Mon, 29 Jun 2015 16:38:34 +0000 (09:38 -0700)]
util: Use SSE intrinsics in _mesa_lroundeven{f,}.

gcc actually generates this for us now that we use -fno-math-errno
(which is weird, since lrintf()/lrint() don't set errno) but clang still
does not. Presumably helps MSVC as well.

Reduced .text size by 8.5k with gcc before -fno-math-errno.

   text     data      bss      dec      hex  filename
4935850   195136    26192  5157178   4eb13a  i965_dri.so before
4927225   195128    26192  5148545   4e8f81  i965_dri.so after

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agomesa: Use _mesa_lroundevenf() in some more places.
Matt Turner [Fri, 26 Jun 2015 04:43:30 +0000 (21:43 -0700)]
mesa: Use _mesa_lroundevenf() in some more places.

9 years agovl/mpeg12: Silence GCC unused-variable warning.
Vinson Lee [Thu, 30 Jul 2015 03:32:41 +0000 (20:32 -0700)]
vl/mpeg12: Silence GCC unused-variable warning.

vl/vl_mpeg12_bitstream.c: In function 'decode_slice':
vl/vl_mpeg12_bitstream.c:928:19: warning: unused variable 'extra' [-Wunused-variable]
          unsigned extra = vl_vlc_get_uimsbf(&bs->vlc, 1);
                   ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
9 years agoglsl: replace old hash table with new and faster one
Alejandro Seguí [Mon, 3 Aug 2015 00:15:20 +0000 (02:15 +0200)]
glsl: replace old hash table with new and faster one

The util/hash_table was intended to be a fast hash table
replacement for the program/hash_table see 35fd61bd99c1 and
72e55bb6888ff.

Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
9 years agoglsl: Add constuctors for the common cases of glsl_struct_field
Ian Romanick [Thu, 30 Jul 2015 13:00:56 +0000 (06:00 -0700)]
glsl: Add constuctors for the common cases of glsl_struct_field

Fixes a giant pile of GCC warnings:

builtin_types.cpp:60:1: warning: missing initializer for member 'glsl_struct_field::stream' [-Wmissing-field-initializers]

I had to add a default constructor because a non-default constructor
was added.  Otherwise the only constructor would be the one with
parameters, and all the plases like

    glsl_struct_field foo;

would fail to compile.

I wanted to do this in two patches.  All of the initializers of
glsl_struct_field structures had to be converted to use the
constructor because C++ apparently forces you to do one or the other:

builtin_types.cpp:61:1: error: could not convert '{glsl_type::float_type, "near", -1, 0, 0, 0, GLSL_MATRIX_LAYOUT_INHERITED, 0, -1}' from '<brace-enclosed initializer list>' to 'glsl_struct_field'

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Make gen7_upload_ps_state static
Ian Romanick [Thu, 25 Jun 2015 17:45:34 +0000 (10:45 -0700)]
i965: Make gen7_upload_ps_state static

It is only ever called from within the same file.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Remove extern declaration for nonexistent state atom
Ian Romanick [Thu, 25 Jun 2015 15:43:13 +0000 (08:43 -0700)]
i965: Remove extern declaration for nonexistent state atom

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in gen7_vs_state.c
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in gen7_vs_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in gen6_multisample_state.c
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in gen6_multisample_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in brw_misc_state.c
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in brw_misc_state.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in brw_draw_upload.c
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in brw_draw_upload.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in brw_draw.c
Ian Romanick [Fri, 19 Jun 2015 01:45:44 +0000 (18:45 -0700)]
i965: Trivial formatting changes in brw_draw.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965: Trivial formatting changes in brw_wm.c
Ian Romanick [Thu, 11 Jun 2015 00:09:16 +0000 (17:09 -0700)]
i965: Trivial formatting changes in brw_wm.c

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
9 years agoi965/nir: Do not scalarize phis in non-scalar setups
Iago Toral Quiroga [Wed, 15 Jul 2015 07:32:17 +0000 (09:32 +0200)]
i965/nir: Do not scalarize phis in non-scalar setups

Significantly reduces register pressure in some piglit tests.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Handle uniform and GRF array access on vertex programs (NIR)
Antia Puentes [Wed, 8 Jul 2015 14:08:17 +0000 (16:08 +0200)]
i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)

When the NIR-vec4 pass is enabled, handles uniform and GRF array access
on ARB_vertex_program like it is done on vertex shaders.

When the old IR-vec4 pass is used, emit_program_code() emits pull constant
loads directly instead of using relative addressing, hence to call to
move_uniform_array_access_to_pull_constants() is not needed and it is enough
to call to split_uniform_registers().

The patch also calls to move_grf_array_access_to_scratch() like it is
done for shaders, however I suspect this is a no-op for vertex programs and
we could remove it.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Handle uniforms on vertex programs
Antia Puentes [Mon, 29 Jun 2015 12:21:38 +0000 (14:21 +0200)]
i965/nir/vec4: Handle uniforms on vertex programs

The implementation takes into account that on ARB_vertex_program
only a single nir variable is generated to support all the uniform data.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Enable NIR-vec4 pass on ARB_vertex_programs
Antia Puentes [Wed, 8 Jul 2015 10:44:15 +0000 (12:44 +0200)]
i965/vec4: Enable NIR-vec4 pass on ARB_vertex_programs

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/gs: Implement support for gl_InvocationID system value
Iago Toral Quiroga [Wed, 1 Jul 2015 08:12:10 +0000 (10:12 +0200)]
i965/nir/gs: Implement support for gl_InvocationID system value

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6
Samuel Iglesias Gonsalvez [Mon, 13 Jul 2015 13:51:17 +0000 (15:51 +0200)]
i965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6

So the implementation is independent of GLSL IR and the visit methods of the
gen6 GS visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/gs: Implement EmitVertex and EndPrimitive
Iago Toral Quiroga [Mon, 29 Jun 2015 12:08:11 +0000 (14:08 +0200)]
i965/nir/gs: Implement EmitVertex and EndPrimitive

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/gs: Handle geometry shaders inputs
Iago Toral Quiroga [Mon, 29 Jun 2015 11:52:30 +0000 (13:52 +0200)]
i965/nir/gs: Handle geometry shaders inputs

Outputs from the vertex shader become array inputs in the geomtry shader,
but the arrays are interleaved, so we need to map our inputs accordingly.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/gs: Refactor ir_emit_vertex and ir_end_primitive
Iago Toral Quiroga [Mon, 29 Jun 2015 11:37:31 +0000 (13:37 +0200)]
i965/gs: Refactor ir_emit_vertex and ir_end_primitive

So the implementation is independent of GLSL IR and the visit methods of the
vec4 visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Enable NIR-vec4 pass on geometry shaders
Iago Toral Quiroga [Wed, 1 Jul 2015 07:51:25 +0000 (09:51 +0200)]
i965/nir: Enable NIR-vec4 pass on geometry shaders

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Fix output swizzle in get_mul_for_src
Samuel Iglesias Gonsalvez [Thu, 11 Jun 2015 10:32:26 +0000 (12:32 +0200)]
nir: Fix output swizzle in get_mul_for_src

Avoid copying an overwritten swizzle, use the original values.

Example:

   Former swizzle[] = xyzw
   src->swizzle[] = zyxx

The expected output swizzle = zyxx but if we reuse swizzle in the loop,
then output swizzle would be zyzz.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add implementation of nir_emit_texture()
Alejandro Piñeiro [Mon, 6 Jul 2015 13:08:15 +0000 (15:08 +0200)]
i965/nir/vec4: Add implementation of nir_emit_texture()

Uses the nir structure to get all the info needed (sources,
dest reg, etc), and then it uses the common
vec4_visitor::emit_texture to emit the final code.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/ir/vec4: Refactor visit(ir_texture *ir)
Alejandro Piñeiro [Mon, 6 Jul 2015 12:33:21 +0000 (14:33 +0200)]
i965/ir/vec4: Refactor visit(ir_texture *ir)

Splitted in two. The emission is moved to a new vec4_visitor
method, vec4_visitor::emit_texture, ir order to be reused
on the nir path.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Add a new dst_reg constructor accepting a brw_reg_type
Alejandro Piñeiro [Sat, 23 May 2015 21:42:58 +0000 (23:42 +0200)]
i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type

This is useful for the upcoming texture support in NIR->vec4 pass,
as we found several cases where the brw_type is available, but not
the glsl_type.

Without this new constructor, the alternative would be:
dst_reg reg(MRF, <reg>)
reg.type = <brw_type>
reg.writemask = <mask>

Adding a new constructor makes code easier to read.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Change vec4_visitor::swizzle_result() method to allow reuse
Alejandro Piñeiro [Mon, 6 Jul 2015 11:31:05 +0000 (13:31 +0200)]
i965/vec4: Change vec4_visitor::swizzle_result() method to allow reuse

This patch changes the signature of swizzle_result() to accept lower
level arguments. The purpose is to reuse it in the upcoming NIR->vec4
pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Change vec4_visitor::gather_channel() method to allow reuse
Eduardo Lima Mitev [Thu, 18 Jun 2015 10:12:21 +0000 (12:12 +0200)]
i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse

This patch changes the signature of gather_channel() to accept the gather
component directly instead of fetching it internally from ir_texture.
This will allow reuse in the upcoming NIR->vec4 pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse
Eduardo Lima Mitev [Thu, 18 Jun 2015 09:31:54 +0000 (11:31 +0200)]
i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse

This patch changes the signature of emit_mcs_fetch() to accept lower level
arguments. The purpose is to reuse it in the upcoming NIR->vec4 pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Move is_high_sample() method to vec4_visitor class
Eduardo Lima Mitev [Thu, 18 Jun 2015 07:37:33 +0000 (09:37 +0200)]
i965/vec4: Move is_high_sample() method to vec4_visitor class

The is_high_sample() method is currently accessible only in the implementation of
vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make
it a method of the class instead.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Add new utility method brw_glsl_base_type_for_nir_type()
Eduardo Lima Mitev [Wed, 17 Jun 2015 08:59:10 +0000 (10:59 +0200)]
i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()

This method returns the glsl_base_type corresponding to a nir_alu_type.
It will factorize code currently present in fs_nir, that can be reused
in vec4_nir on its upcoming emit_texture support.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement nir_emit_jump
Eduardo Lima Mitev [Wed, 17 Jun 2015 08:20:19 +0000 (10:20 +0200)]
i965/nir/vec4: Implement nir_emit_jump

This implementation is taken as-is from fs_nir.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Mark as unreachable ops that should be already lowered
Antia Puentes [Wed, 17 Jun 2015 08:10:44 +0000 (10:10 +0200)]
i965/nir/vec4: Mark as unreachable ops that should be already lowered

NIR ALU operations:
   * nir_op_fabs
   * nir_op_iabs
   * nir_op_fneg
   * nir_op_ineg
   * nir_op_fsat
        should be lowered by lower_source mods

   * nir_op_fdiv
        should be lowered in the compiler by DIV_TO_MUL_RCP.

   * nir_op_fmod
        should be lowered in the compiler by MOD_TO_FLOOR.

   * nir_op_fsub
   * nir_op_isub
        should be handled by ir_sub_to_add_neg.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement vector "any" operation
Antia Puentes [Wed, 17 Jun 2015 08:08:27 +0000 (10:08 +0200)]
i965/nir/vec4: Implement vector "any" operation

Adds NIR ALU operations:
   * nir_op_bany2
   * nir_op_bany3
   * nir_op_bany4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement the dot product operation
Antia Puentes [Wed, 17 Jun 2015 08:06:44 +0000 (10:06 +0200)]
i965/nir/vec4: Implement the dot product operation

Adds NIR ALU operations:
   * nir_op_fdot2
   * nir_op_fdot3
   * nir_op_fdot4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement conditional select
Antia Puentes [Wed, 17 Jun 2015 08:05:29 +0000 (10:05 +0200)]
i965/nir/vec4: Implement conditional select

Adds NIR ALU operations:
   * nir_op_bcsel

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement linear interpolation
Antia Puentes [Wed, 17 Jun 2015 07:52:43 +0000 (09:52 +0200)]
i965/nir/vec4: Implement linear interpolation

Adds NIR ALU operation:
   * nir_op_flrp

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Return the emitted instruction in emit_lrp()
Antia Puentes [Wed, 17 Jun 2015 08:01:07 +0000 (10:01 +0200)]
i965/vec4: Return the emitted instruction in emit_lrp()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement floating-point fused multiply-add
Antia Puentes [Wed, 17 Jun 2015 07:51:10 +0000 (09:51 +0200)]
i965/nir/vec4: Implement floating-point fused multiply-add

Adds NIR ALU operation:
   * nir_op_ffma

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement "shift" operations
Antia Puentes [Wed, 17 Jun 2015 07:49:31 +0000 (09:49 +0200)]
i965/nir/vec4: Implement "shift" operations

Adds NIR ALU operations:
   * nir_op_ishl
   * nir_op_ishr
   * nir_op_ushr

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement the "sign" operation
Antia Puentes [Wed, 17 Jun 2015 07:47:41 +0000 (09:47 +0200)]
i965/nir/vec4: Implement the "sign" operation

Follows the vec4_visitor IR implementation but
sets the saturate value in addition.

Adds NIR ALU operations:
   * nir_op_fsign
   * nir_op_isign

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement bit operations
Antia Puentes [Wed, 17 Jun 2015 07:44:25 +0000 (09:44 +0200)]
i965/nir/vec4: Implement bit operations

Same implementation than the IR case.

Adds NIR ALU operations:
   * nir_op_bitfield_reverse
   * nir_op_bit_count
   * nir_op_ufind_msb
   * nir_op_ifind_msb
   * nir_op_find_lsb
   * nir_op_ubitfield_extract
   * nir_op_ibitfield_extract
   * nir_op_bfm
   * nir_op_bfi
   * nir_op_bitfield_insert

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement pack/unpack operations
Antia Puentes [Wed, 17 Jun 2015 07:29:04 +0000 (09:29 +0200)]
i965/nir/vec4: Implement pack/unpack operations

* Lowered floating-point pack and unpack operations are not valid in VS.

* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.

* Adds NIR ALU operations:
   * nir_op_pack_half_2x16
   * nir_op_unpack_half_2x16
   * nir_op_unpack_unorm_4x8
   * nir_op_unpack_snorm_4x8
   * nir_op_pack_unorm_4x8
   * nir_op_pack_snorm_4x8

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: "noise" ops should already be lowered
Antia Puentes [Wed, 17 Jun 2015 07:23:10 +0000 (09:23 +0200)]
i965/nir/vec4: "noise" ops should already be lowered

Marked them as unreachable.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement "bool<->int,float" format conversion
Antia Puentes [Wed, 17 Jun 2015 07:21:30 +0000 (09:21 +0200)]
i965/nir/vec4: Implement "bool<->int,float" format conversion

Used the same implementation than the vec4_visitor NIR.

Adds NIR ALU operations:
   * nir_op_b2i
   * nir_op_b2f
   * nir_op_f2b
   * nir_op_i2b

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement logical operators
Antia Puentes [Wed, 17 Jun 2015 07:07:20 +0000 (09:07 +0200)]
i965/nir/vec4: Implement logical operators

Adds NIR ALU operations:
   * nir_op_inot
   * nir_op_ixor
   * nir_op_ior
   * nir_op_iand

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement non-equality ops on vectors
Antia Puentes [Wed, 17 Jun 2015 07:01:28 +0000 (09:01 +0200)]
i965/nir/vec4: Implement non-equality ops on vectors

Adds NIR ALU operations:
   * nir_op_bany_fnequal2
   * nir_op_bany_inequal2
   * nir_op_bany_fnequal3
   * nir_op_bany_inequal3
   * nir_op_bany_fnequal4
   * nir_op_bany_inequal4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement equality ops on vectors
Antia Puentes [Tue, 16 Jun 2015 22:55:24 +0000 (00:55 +0200)]
i965/nir/vec4: Implement equality ops on vectors

Adds NIR ALU operations:
   * nir_op_ball_fequal2
   * nir_op_ball_iequal2
   * nir_op_ball_fequal3
   * nir_op_ball_iequal3
   * nir_op_ball_fequal4
   * nir_op_ball_iequal4

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement non-vector comparison ops
Antia Puentes [Tue, 16 Jun 2015 22:49:42 +0000 (00:49 +0200)]
i965/nir/vec4: Implement non-vector comparison ops

Adds NIR ALU operations:
   * nir_op_flt
   * nir_op_ilt
   * nir_op_ult
   * nir_op_fge
   * nir_op_ige
   * nir_op_uge
   * nir_op_feq
   * nir_op_ieq
   * nir_op_fne
   * nir_op_ine

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Add utility method for comparisons
Antia Puentes [Fri, 17 Apr 2015 15:58:35 +0000 (17:58 +0200)]
i965/nir: Add utility method for comparisons

This method returns the brw_conditional_mod value used when emitting
comparative ALU operations.

It could be moved to brw_nir in the future to reuse it in fs_nir backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Derivatives are not allowed in VS
Antia Puentes [Tue, 14 Apr 2015 10:04:24 +0000 (12:04 +0200)]
i965/nir/vec4: Derivatives are not allowed in VS

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement min/max operations
Antia Puentes [Tue, 16 Jun 2015 22:34:57 +0000 (00:34 +0200)]
i965/nir/vec4: Implement min/max operations

Adds NIR ALU operations:
   * nir_op_fmin
   * nir_op_imin
   * nir_op_umin
   * nir_op_fmax
   * nir_op_imax
   * nir_op_umax

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Return the emitted instruction in emit_minmax()
Antia Puentes [Tue, 16 Jun 2015 22:32:58 +0000 (00:32 +0200)]
i965/vec4: Return the emitted instruction in emit_minmax()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement various rounding functions
Antia Puentes [Tue, 16 Jun 2015 22:25:02 +0000 (00:25 +0200)]
i965/nir/vec4: Implement various rounding functions

Adds NIR ALU operations:
   * nir_op_ftrunc
   * nir_op_fceil
   * nir_op_ffloor
   * nir_op_ffrac
   * nir_op_fround_even

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement carry/borrow for addition/subtraction
Antia Puentes [Tue, 16 Jun 2015 22:22:14 +0000 (00:22 +0200)]
i965/nir/vec4: Implement carry/borrow for addition/subtraction

Adds NIR ALU operations:
   * nir_op_uadd_carry
   * nir_op_usub_borrow

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement more math operations
Antia Puentes [Tue, 16 Jun 2015 22:10:18 +0000 (00:10 +0200)]
i965/nir/vec4: Implement more math operations

Adds NIR ALU operations:
   * nir_op_frcp
   * nir_op_fexp2
   * nir_op_flog2
   * nir_op_fexp
   * nir_op_flog
   * nir_op_fsin
   * nir_op_fcos
   * nir_op_idiv
   * nir_op_udiv
   * nir_op_umod
   * nir_op_ldexp
   * nir_op_fsqrt
   * nir_op_frsq
   * nir_op_fpow

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Return the last emitted instruction in emit_math()
Antia Puentes [Tue, 16 Jun 2015 22:04:09 +0000 (00:04 +0200)]
i965/vec4: Return the last emitted instruction in emit_math()

Needed in the NIR backend to set the "saturate" value of the
instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement multiplication
Antia Puentes [Tue, 16 Jun 2015 21:50:46 +0000 (23:50 +0200)]
i965/nir/vec4: Implement multiplication

Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.

Adds NIR ALU operations:
   * nir_op_fmul
   * nir_op_imul
   * nir_op_imul_high
   * nir_op_umul_high

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement the addition operation
Antia Puentes [Tue, 16 Jun 2015 21:48:46 +0000 (23:48 +0200)]
i965/nir/vec4: Implement the addition operation

Adds NIR ALU operations:
   * nir_op_fadd
   * nir_op_iadd

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement int<->float format conversion ops
Antia Puentes [Tue, 16 Jun 2015 21:04:32 +0000 (23:04 +0200)]
i965/nir/vec4: Implement int<->float format conversion ops

Adds NIR ALU operations:
   * nir_op_f2i
   * nir_op_f2u
   * nir_op_i2f
   * nir_op_u2f

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Lower "vecN" instructions and mark them unreachable
Antia Puentes [Tue, 16 Jun 2015 20:58:15 +0000 (22:58 +0200)]
i965/nir/vec4: Lower "vecN" instructions and mark them unreachable

This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement single-element "mov" operations
Antia Puentes [Tue, 16 Jun 2015 20:52:29 +0000 (22:52 +0200)]
i965/nir/vec4: Implement single-element "mov" operations

Adds NIR ALU operations:
   * nir_op_imov
   * nir_op_fmov

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Disable alu_to_scalar pass on non-scalar shaders
Alejandro Piñeiro [Thu, 25 Jun 2015 07:52:35 +0000 (09:52 +0200)]
i965/nir: Disable alu_to_scalar pass on non-scalar shaders

Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Prepare source and destination registers for ALU operations
Antia Puentes [Tue, 16 Jun 2015 20:30:16 +0000 (22:30 +0200)]
i965/nir/vec4: Prepare source and destination registers for ALU operations

This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement loading values from an UBO
Antia Puentes [Tue, 16 Jun 2015 20:10:32 +0000 (22:10 +0200)]
i965/nir/vec4: Implement loading values from an UBO

Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).

Adds NIR instrinsics:

   * nir_intrinsic_load_ubo_indirect
   * nir_intrinsic_load_ubo

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)
Alejandro Piñeiro [Tue, 16 Jun 2015 20:03:17 +0000 (22:03 +0200)]
i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)

The implementation is based on its fs_nir counterpart.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement load_uniform intrinsic
Iago Toral Quiroga [Tue, 16 Jun 2015 19:55:14 +0000 (21:55 +0200)]
i965/nir/vec4: Implement load_uniform intrinsic

For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement intrinsics that load system values
Alejandro Piñeiro [Tue, 16 Jun 2015 19:36:49 +0000 (21:36 +0200)]
i965/nir/vec4: Implement intrinsics that load system values

These include:

nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id

The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement store_output intrinsic
Eduardo Lima Mitev [Tue, 16 Jun 2015 19:31:49 +0000 (21:31 +0200)]
i965/nir/vec4: Implement store_output intrinsic

This implementation is based on the current URB setup in vec4_visitor, which
requires the output register to be stored in the output_reg array at variable's
original shader location index. But since nir_lower_io() pass uses the value
in var->data.driver_location, we need to put there var->data.location instead,
prior to calling nir_lower_io(), so that we end up with the correct index
in const_index[0].

The driver_location is not used at all, so this patch also disables the
nir_assign_var_locations pass on non-scalar shaders.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Make sure that register types always match during emit_urb_slot()
Eduardo Lima Mitev [Tue, 21 Jul 2015 18:21:21 +0000 (20:21 +0200)]
i965/vec4: Make sure that register types always match during emit_urb_slot()

Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to
store registers in output_reg with the correct type, this patch makes sure
that the common code in emit_urb_slot() always emit MOVs from output registers
using the same type on source and destination.

Since the actual type is not important, only that they match, we default to
float.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement load_input intrinsic
Eduardo Lima Mitev [Tue, 16 Jun 2015 19:24:21 +0000 (21:24 +0200)]
i965/nir/vec4: Implement load_input intrinsic

The source register is fetched from the nir_inputs map built during
nir_setup_inputs stage.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement loop statements (nir_cf_node_loop)
Eduardo Lima Mitev [Tue, 16 Jun 2015 18:25:55 +0000 (20:25 +0200)]
i965/nir/vec4: Implement loop statements (nir_cf_node_loop)

This is taken as-is from fs_nir.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement conditional statements (nir_cf_node_if)
Iago Toral Quiroga [Tue, 16 Jun 2015 18:16:15 +0000 (20:16 +0200)]
i965/nir/vec4: Implement conditional statements (nir_cf_node_if)

The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add get_nir_dst() and get_nir_src() methods
Eduardo Lima Mitev [Tue, 16 Jun 2015 15:43:02 +0000 (17:43 +0200)]
i965/nir/vec4: Add get_nir_dst() and get_nir_src() methods

These methods are essential for the implementation of the NIR->vec4 pass. They
work similar to their fs_nir counter-parts.

When processing instructions, these methods are invoked to resolve the
brw registers (source or destination) corresponding to the NIR sources
or destination. It uses the map of NIR register index to brw register for
all registers locally allocated in a block.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse
Eduardo Lima Mitev [Fri, 17 Apr 2015 16:10:50 +0000 (18:10 +0200)]
i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse

Upcoming NIR->vec4 pass can benefit from this method, so lets move it up.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Implement load_const intrinsic
Eduardo Lima Mitev [Wed, 1 Jul 2015 14:10:49 +0000 (16:10 +0200)]
i965/nir/vec4: Implement load_const intrinsic

Similar to fs_nir backend, a nir_local_values map will be filled with
newly allocated registers as the load_const instrinsic instructions are
processed. Later, get_nir_src() will fetch the registers from this map
for sources that are ssa.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Add auxiliary func to build a writemask from a component size
Eduardo Lima Mitev [Tue, 16 Jun 2015 18:53:28 +0000 (20:53 +0200)]
i965/vec4: Add auxiliary func to build a writemask from a component size

New method brw_writemask_for_size() will return a writemask with the first
'size' components activated.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Dot not assign direct uniform locations first for vec4-based shaders
Iago Toral Quiroga [Fri, 3 Jul 2015 06:23:33 +0000 (08:23 +0200)]
i965/nir: Dot not assign direct uniform locations first for vec4-based shaders

In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir/nir_lower_io: Add vec4 support
Iago Toral Quiroga [Thu, 18 Jun 2015 11:52:21 +0000 (13:52 +0200)]
nir/nir_lower_io: Add vec4 support

The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.

This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir: Pass a is_scalar boolean to brw_create_nir()
Eduardo Lima Mitev [Wed, 22 Jul 2015 07:35:28 +0000 (09:35 +0200)]
i965/nir: Pass a is_scalar boolean to brw_create_nir()

The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).

With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add shader function implementation
Eduardo Lima Mitev [Wed, 22 Jul 2015 07:34:35 +0000 (09:34 +0200)]
i965/nir/vec4: Add shader function implementation

It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add setup for system values
Alejandro Piñeiro [Tue, 16 Jun 2015 15:08:04 +0000 (17:08 +0200)]
i965/nir/vec4: Add setup for system values

Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass
Alejandro Piñeiro [Tue, 16 Jun 2015 15:01:29 +0000 (17:01 +0200)]
i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass

The new virtual method is more flexible, it has a signature:

dst_reg *make_reg_for_system_value(int location, const glsl_type *type);

v2 (Jason Ekstrand):
   Use the new version in unit tests so make check passes again

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add setup of uniform variables
Iago Toral Quiroga [Tue, 16 Jun 2015 12:30:31 +0000 (14:30 +0200)]
i965/nir/vec4: Add setup of uniform variables

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Add setup of input variables in NIR->vec4 pass
Eduardo Lima Mitev [Tue, 16 Jun 2015 11:50:43 +0000 (13:50 +0200)]
i965/nir/vec4: Add setup of input variables in NIR->vec4 pass

This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.

This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will be loaded.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Move type_size() method to brw_vec4_visitor class
Eduardo Lima Mitev [Tue, 16 Jun 2015 11:39:48 +0000 (13:39 +0200)]
i965/vec4: Move type_size() method to brw_vec4_visitor class

The type_size() method is currently accessible only in the implementation
of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass,
lets make it a method of the class instead.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths
Eduardo Lima Mitev [Tue, 16 Jun 2015 10:26:39 +0000 (12:26 +0200)]
i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths

The NIR->vec4 pass will be activated if both the following conditions are met:

* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader (support for geometry shaders and
  ARB_vertex_program will be added later).

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>