nir: add a pass for lowering (un)pack_double_2x32

v2: Undo unintended change to the signature of
    nir_normalize_cubemap_coords (Iago).

v3: Move to compiler/nir (Iago)

v4: Remove Authors from copyright header (Michael Schellenberger)

v5 (Sam):
- Use nir_channel() and nir_ssa_for_alu_src() helpers (Jason)
- Inline lower_double_pack_instr() code into lower_double_pack_block()
  (Jason).
- Initialize nir_builder at lower_double_pack_impl() (Jason).

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add split versions of (un)pack_double_2x32

v2 (Sam):
- Use uint64 instead of float64 for sources and destinations. (Connor)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: don't try to scalarize unpack_double_2x32

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add support for (un)pack_double_2x32

v2 (Sam):
- Use uint64 instead of float64 for sources and destinations. (Connor)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add i2d and u2d opcodes

v2:
- Assert supports_int and don't fallback to nir_fmov (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add d2i, d2u, d2b opcodes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add support for d2f and f2d

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: set bit_size on ssbo_load result

v2 (Sam):
- Add missing bit_size assignment when ssbo_load destination is a boolean.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: add bit-size info to add_instr()

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/split_var_copies: handle doubles

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/instr_set: handle 64-bit bit-sizes

v2: Revert spurious change in nir_opt_cse.c (Iago)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: handle doubles in nir_deref_get_const_initializer_load()

v2 (Sam):
- Use proper bitsize value when calling to nir_load_const_instr_create()
  (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/print: add support for printing doubles and bitsize

v2:
- Squash the printing doubles related patches into one patch (Sam).

v3:
- Print using PRIx64 format: long is 32-bit on some 32-bit platforms but long
long is basically always 64-bit (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: support doubles

v2:
- Don't set sized types to the destination of texture related opcodes.
  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_load_const_to_scalar: support doubles and multiple bit sizes

v2 (Sam):
- Add assert to detect bitsizes differents than 32 and 64 (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_to_source_mods: Handle different bit sizes

v2 (Sam):
- Use helper to get base type from nir_alu_type.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add bit_size info to nir_load_const_instr_create()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_vec: adapt to different bit sizes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add bit_size info to nir_ssa_undef_instr_create()

v2:
- Make the users to give the right bit_sizes as arguments (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/locals_to_regs: adapt to different bit sizes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/from_ssa: adapt to different bit sizes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: fix struct type in comment

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

nir: Add a pass for gathering various bits of shader info

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: enable OES_texture_buffer on gen7+

It will only end up getting exposed on gen8+ since it requires GL ES
3.1, but it should be ready to go on gen7 when support for GL ES 3.1 is
completed there.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>

docs: add some missing softpipe entries.

I just forgot these when I added this stuff.

Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl: Don't remove XFB-only varyings.

Consider the case of linking a program with both a vertex and fragment
shader.  The VS may compute output varyings that are intended for
transform feedback, and not read by the fragment shader.

In this case, var->data.is_unmatched_generic_inout will be true,
but we still cannot eliminate the varyings.  We need to also check
!var->data.is_xfb_only.

Fixes failures in ES31-CTS.gpu_shader5.fma_precision_*, which happen
to use transform feedback in a way we apparently hadn't seen before.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965/disasm: Decode per-slot offsets.

We just never bothered to decode this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/disasm: Decode "channel mask present" bit correctly.

Bit 15 means "interleave" for most messages, but for SIMD8 messages it
means "use channel masks".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/disasm: Simplify the URB opcode printing with ?:.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

glsl: allow usage of the keyword buffer before GLSL 430 / ESSL 310

The GLSL 4.20 and ESSL 3.00 specs don't list 'buffer' as a reserved
keyword. Make the parser ignore it unless GLSL 4.30 / ESSL 3.10 are
used, or ARB_shader_storage_buffer_objects is enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: mesa-stable@lists.freedesktop.org

nvc0: handle the case where there are no framebuffer attachments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50,nvc0: support sending string markers down into the command stream

This should hopefully make it a little easier to debug with GL
applications like glretrace and looking at command streams.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50,nvc0: add invalidate_resource support for buffer resources

Provide a callback to reallocate the underlying storage of a resource so
that it is not bound to any existing fences.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

vc4: Move FRAG_X/Y/REV_FLAG to a QFILE like VPM or TLB color writes.

This gives us one less set of special instruction generation cases, and
instead just the case for returning the correct register to read.

vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.

This lets us write the Z directly from the FTOI for computed Z, and may
let us coalesce color writes in the future.

No change in my shader-db, but clearly drops an instruction in piglit's
early-z test.

vc4: Add a helper function for the construction of qregs.

The separate declaration of the struct is not helping clarity, and I was
going to be writing a whole lot more of these in the upcoming patches.

vc4: Add missing scheduling dependency for MS color writes.

vc4: Drop the multi_instruction distinction for QIR instructions.

It wasn't correctly flagged everywhere, and QPU generation now handles the
only remaining case that was paying attention to it.

No change on shader-db.

vc4: Handle SF on instructions that write r4.

Normal SFU writes couldn't have SF because they were marked as
multi_instruction, but tex_result and tlb_color_read weren't.  This ended
up not being a problem according to anything in shader-db, but it seems
possible.

vc4: Allow multi-instruction QIR nodes to get VPM optimization.

There used to be multi-instruction operations that would use src[] twice,
which is why we couldn't do some optimizations on them.  This is no longer
the case.

total instructions in shared programs: 77973 -> 77969 (-0.01%)
instructions in affected programs:     84 -> 80 (-4.76%)
total estimated cycles in shared programs: 234165 -> 234157 (-0.00%)
estimated cycles in affected programs:     92 -> 84 (-8.70%)

vc4: Switch to using NIR_PASS macros.

This gets us better validation of our NIR transformations.

vc4: Handle nir_intrinsic_load_user_clip_plane as a vec4.

I liked having all my NIR be scalar, but nir_validate() complains that the
intrinsic writes 4 components but the destination we set up was only 1
component.  I could generate a new scalar variant, but it's a lot easier
to just leave it as a vec4.  This doesn't hurt codegen since we GC unused
uniforms, and UCP dot products use all the components anyway.

vc4: Emit a warning and proceed for handling loops in NIR.

We don't really suppor control flow yet, but it's a lot nicer to render
something and warn on stderr than to crash.

Fixes the following piglit tests:
- shaders/complex-loop-analysis-bug
- shaders/glsl-fs-discard-04

Converts the following piglit tests from crash to fail:
- shaders/glsl-fs-continue-inside-do-while
- shaders/glsl-fs-loop
- shaders/glsl-fs-loop-continue
- shaders/glsl-fs-loop-nested
- shaders/glsl-texcoord-array
- shaders/glsl-vs-continue-inside-do-while
- shaders/glsl-vs-loop
- shaders/glsl-vs-loop-continue
- shaders/glsl-vs-loop-nested

No piglit regressions.

v2 (Eric): Add stronger stderr warning.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Add a stub for NIR->QIR of control flow function nodes

We shouldn't have any NIR functions present since all GLSL functions get
inlined, but this would be a more informative error if it does happen.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Add better debug of NIR->QIR control flow graph failure

Ensure NIR control flow graph nodes that are unhandled in QIR
are reported with sufficient verbosity to aid debugging.

This improves piglit outputs, amongst other tools.

There are no other remaining uses of assert(0) as a blunt tool
within vc4.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

vc4: Remove unused include from vc4_program.c

Found with grep and inspection. Test compiled on RPi hw.
Assists any future effort to remove TGSI as an intermediate stage.

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: handle unsigned int wraparound in link_shaders()

v2: change check_explicit_uniform_locations() to return an
    unsigned 0 (Timothy Arceri)

We were storing the int result of check_explicit_uniform_locations()
in num_explicit_uniform_locs as an unsigned int which caused it to
be 4294967295 when a -1 was returned.

This in turn would cause the following error during linking:
error: count of uniform locations > MAX_UNIFORM_LOCATIONS(4294967295 > 98304)

Results from running piglit tests/all with this patch
and when ARB_explicit_uniform_location disabled:

changes:     178
fixes:       176
regressions: 2

The two regressions are for the following tests:
glean@glsl1-matrix column check (1)
glean@glsl1-matrix column check (2)
which regress from FAIL to CRASH.

The regressions are acceptable because the tests are currently failing due to
the aforementioned linker error.

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965/tiled_memcopy: Get rid of the direction parameter to get_memcpy

Now that we can use the much simpler rgba8_copy function, we don't need to
hand different functions out based on direction.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/tiled_memcpy: Rework the RGBA -> BGRA mem_copy functions

This splits the two copy functions into three: One for unaligned copies,
one for aligned sources, and one for aligned destinations.  Thanks to the
previous commit, we are now guaranteed that the aligned ones will *only*
operate on aligned memory so they should be safe.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93962
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965/tiled_memcopy: Add aligned mem_copy parameters to the [de]tiling functions

Each of the [de]tiling functions has three mem_copy calls:

 1) Left edge to tile boundary
 2) Tile boundary to tile boundary in a loop
 3) Tile boundary to right edge

Copies 2 and 3 start at a tile edge so the pointer to tiled memory is
guaranteed to be at least 16-byte aligned.  Copy 1, on the other hand,
starts at some arbitrary place in the tile so it doesn't have any such
alignment guarantees.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965: Check eu/subslices are > 0

Now that the check is restricted to gen8+, we should always get back a non-zero
positive value for the EU and subslice counts.

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix eu/subslice warning

Older gen platforms do not actually return a value for sublice and eu total
(IMO, confusingly) they return -ENODEV. This patch defers the SSEU setup until
we have the actual GPU generation to avoid useless warnings when running on
older platforms with older kernels.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Extract SSEU configuration info

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/mesa: fix glReadBuffer() assertion failure

If the first call in a GL app is glReadPixels(GL_FRONT) we'd fail the
assert(st->ctx->FragmentProgram._Current) at st_atom_shader.c:114 in
update_fp().

This is because we were calling st_validate_state() without first
updating Mesa state with _mesa_update_state().

The regression came from commit 83b589301f4a150f4 "st/mesa: fix
frontbuffer glReadPixels regressions".

The new piglit gl-1.0-simple-readbuffer test exercises this.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/va: avoid dereference after free in vlVaDestroyImage

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>

radeonsi: do per-pixel clipping based on viewport states

In other words, vport scissors are derived from viewport states.
If the scissor test is enabled, the intersection of both is used.

The guard band will disable clipping, so we have to clip per-pixel.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nv50/ir: do not try to attach JOIN ops to ATOM

This might result in an INVALID_OPCODE dmesg error in case a join is
attached to an atomic operation.

Spotted with arb_shader_image_load_store-host-mem-barrier on GK104.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

radeonsi: raise number of samplers per shader to 32

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94835
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: expand the compressed color and depth texture masks to 64 bits

This is in preparation of raising the number of exposed sampler views to 32
bits, which will raise the total number of sampler views to 33 for the
polygon stipple texture. That texture should never be compressed (and it's
certainly not a depth texture), but this approach seems cleaner to me than
special-casing the last slot in all affected code paths.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: replace magic 16 by SI_NUM_USER_SAMPLERS

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: raise PIPE_MAX_SAMPLERS to 32

The previous value of 18 was motivated by having drivers that want to expose
16 samplers but also use some additional samplers for internal use. Raising
the value even higher isn't going to hurt that case.

On the other hand, some drivers actually use PIPE_MAX_SAMPLERS as the number
of samplers they expose externally, so raising this number above 32 is fragile
(because several places in the code use bitfields, and tracking down and
widening all of them is prone to miss some case).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: make samplers_used an uint32_t (v2)

It is used as a bitfield, so it seems cleaner to keep it unsigned.

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

v2: add an assert for bitfield size and use 1u << idx

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)

tgsi/scan: add an assert for the size of the samplers_declared bitfield

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

Reviewed-by: Brian Paul <brianp@vmware.com>

draw/aaline: stronger guard against no free samplers (v2)

Line anti-aliasing will fail when there is no free sampler available. Make
the corresponding guard more robust in preparation of raising
PIPE_MAX_SAMPLERS to 32.

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

v2: add an assert for bitfield size and use 1u << idx

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)

util/pstipple: stronger guard against no free samplers (v2)

When hasFixedUnit is false, polygon stippling will fail when there is no free
sampler available. Make the corresponding guard more robust in preparation
of raising PIPE_MAX_SAMPLERS to 32.

The literal 1 is a (signed) int, and shifting into the sign bit is undefined
in C, so change occurences of 1 to 1u.

v2: add an assert for bitfield size and use 1u << idx

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)

svga: new SVGA_MSAA env var to disable/enable MSAA pixel formats

On by default.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: add some trivial null pointer checks

These small mallocs will probably never fail, but static analysis tools
may complain about the missing checks.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

trace: add missing set_shader_images()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: disable perfect ZPASS counts for PIPE_QUERY_OCCLUSION_PREDICATE

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't use the real barrier instruction in tess ctrl shaders

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Revert "clover: Fix build against clang SVN >= r265359"

This reverts commit 0daab9878d2b96356cf667591a2c877d912be52d.

The corresponding clang change was reverted.

Trivial.

nir/types: Add a wrapper for count_attribute_slots

Reviewed-by: Rob Clark <robdclark@gmail.com>

r600: use radeon_emit in a few more places in evergreen_compute

This is just a cleanup of the code.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: make compute global buffer functions static.

This moves things around so that the global buffer handling
functions in evergreen_compute.c are static.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: make two compute functions static.

These aren't used outside evergreen_compute.c

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: using pipe_grid_info more in evergreen_compute.

No reason to pull the pieces apart here, also make
one of the functions static as it's unused outside this.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: in evergreen_compute use ctx consistently instead of ctx_

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: use rctx consistently in evergreen_compute.c

Another step towards cleaning this up.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: cleanup whitespace in evergreen_compute.c

This aligns the code with the style of the rest of the driver.

Makes editing it a lot less painful.

Acked-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

GL3.txt: Mark ARB_framebuffer_no_attachments as done

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g: Enable ARB_framebuffer_no_attachments

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Enable ARB_framebuffer_no_attachments

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Improve assert info out of si_set_framebuffer_state()

Lets give the developer a little hand if we are going to assert
on a zero literal at the end of a branch.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Allow 16 samples MSAA mode for PIPE_FORMAT_NONE

For ARB_framebuffer_no_attachment; A is_format_supported() query
with 'PIPE_FORMAT_NONE' passed implies a query of the number of
samples supported from the framebuffer with no attachment.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

softpipe: Set samples and layers in set_framebuffer_state() cb

Carries across the number of samples and layers state in the
'softpipe_set_framebuffer_state()' callback. This state is
part of 'ARB_framebuffer_no_attachments' support.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/st: Update framebuffer state with no.of samples,layers

Handle the case of ARB_framebuffer_no_attachment.
Also, kill off a dead debug printf() call while we are here.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/trace: Dump no.of samples and layers in fb state

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: Put no.of {samples,layers} into pipe_framebuffer_state

Here we store the number of samples and layers directly in the
pipe_framebuffer_state so that in the case of
ARB_framebuffer_no_attachment we may make use of them directly.

Further, we adjust various gallium/auxiliary helper functions
accordingly.

V2:
  Convert branches in util_framebuffer_get_num_layers() and
  util_framebuffer_get_num_samples() to their canonical form.

V3:
  'git stash pop' the typo fix of 'cbufs' which should be
  'nr_cbufs' that was missing in V2, woops! Thanks Marek for
  pointing this out yet again.

V4:
  Squash in the following patch:

  'gallium/util: Ensure util_framebuffer_get_num_samples() is valid'

   Upon context creation, internal driver structures are malloc()'ed
   and memset() to zero them. This results in a invalid number of
   samples 'by default'. Handle this in the simplest way to avoid
   elaborate and probably equally sub-optimial solutions.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/st: Set _NumSamples in update_framebuffer_state()

Using PIPE_FORMAT_NONE to indicate what MSAA modes are supported
with a framebuffer using no attachment.

V.2:
 Rewrite MSAA mode loop to be more general.
V.3:
 Move comment to right place after loop was rewritten.
V.4: [airlied]
 remove unneeded variable, and assert, and unneeded pipe assignment

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

gallium: Obtain ARB_framebuffer_no_attachment constants

Set default values for the constants required in
ARB_framebuffer_no_attachments and obtained the number
of layers from ``PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS``.

We also obtain the MaxFramebufferSamples value using
a query back to the driver for PIPE_FORMAT_NONE.

V.1:
 Merge if branch predicates into one branch.
 Move const init into st_init_limits()

[airlied: whitespace fixup]
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium: Add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT

Add PIPE_CAP to determine if the GL extension
'GL_ARB_framebuffer_no_attachments' shall be
supported.

The driver is required to support 'PIPE_FORMAT_NONE'
via its 'is_format_supported()' callback in order
to determine the MSAA modes the hardware supports so
that values requested from the application using
'GL_ARB_framebuffer_no_attachments' may be quantized
to what the hardware expects.

V.2:
 Fix doc for a more detailed description of the PIPE_CAP
 and the corresponding GL constant.

V.3:
 Renamed and repurposed once again.

V.4:
 Remove CAP from cap_mapping array.

[airlied: fix damaged whitespace]

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/st: Use _mesa_geometric_ functions appropriately

Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometric_ convenience functions
for those places where the geometry of the gl_framebuffer is needed.
This is in contrast to the geometry of the intersection of the
attachments of the gl_framebuffer.

This patch paves the way to enable GL_ARB_framebuffer_no_attachements
for all gallium drivers.

V.2:
 Remove itermeditate variable state.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: Add comment to framebuffer_parameteri()

V.2:
 Change 'N.B.,' to 'NOTE:'.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965/sf_state: Pull flat_enables out of prog_data

Previously, we were walking over the shader source to figure out which
inputs should be marked flat.  Now, we can just pull it out of prog_data.
This is needed for properly setting up 3DSTATE_SF/SBE for Vulkan and it
also means that it will get properly cached.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add a flat_inputs field to prog_data

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

brw/device_info: Add a helper for getting a device name

This is needed by the Vulkan driver

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs_surface_builder: Mask signed integers after conversion

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: Make the repclear shader support either a uniform or a flat input

In the Vulkan driver we use a single flat input instead of a uniform
because setting up push constants is more disruptive to the pipeline than
setting up another vertex input.  This uses the number of uniforms as a key
to keep it working for the GL driver.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move get_hw_prim_for_gl_prim to brw_util.c

It's used by brw_compile_gs in brw_vec4_gs_visitor.cpp so it needs to be in
a file that's linked into libi965_compiler.la.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: set shader calling conventions

Note that old mesa + new LLVM or new mesa + old LLVM breaks
with this change and the corresponding LLVM change (D18559).

For LLVM version <= 3.8 we use the old method, but we can't detect
people using a post 3.8 svn version that is still too old.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>