glsl/es3.1: Allow interger mix built-ins in GLSL ES 3.10

v2: Add missing lexer support.  Noticed by Tapani.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> [v1]

glsl/es3.1: Allow separate shader objects in GLSL ES 3.10

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl/es3.1: Allow explicit uniform locations in GLSL ES 3.10

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl/es3.1: Allow 3.10 ES shaders in a GLES 3.1 context

Currently no 3.10 ES features (beyond 3.00 ES) are enabled.  That will
come later.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa/es3.1: Add _mesa_is_gles31 helper

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

docs/GL3: Update GLES 3.1 dependencies

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: Add glsl_parser_state::has_atomic_counters helper

v2: Change GL version from 400 to 420.  Noticed by Tapani and Ilia.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Use bool in _mesa_is_ helpers instead of GLboolean

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Trivial coding standards cleanups

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Use bool instead of GLboolean

v2: Squash in whitespace fixes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

glsl: Silence unused parameter warnings

I opted to comment out "last_field" because it was not obvious what the
meaning of the dangling bool would be.  For the other parameters, the
meaning was more intuitive without the name.

link_uniform_blocks.cpp:70:65: warning: unused parameter 'name' [-Wunused-parameter]
    virtual void enter_record(const glsl_type *type, const char *name,
                                                                 ^
link_uniform_blocks.cpp:77:65: warning: unused parameter 'name' [-Wunused-parameter]
    virtual void leave_record(const glsl_type *type, const char *name,
                                                                 ^
link_uniform_blocks.cpp:93:62: warning: unused parameter 'record_type' [-Wunused-parameter]
                             bool row_major, const glsl_type *record_type,
                                                              ^
link_uniform_blocks.cpp:94:34: warning: unused parameter 'last_field' [-Wunused-parameter]
                             bool last_field)
                                  ^
link_uniforms.cpp:547:65: warning: unused parameter 'name' [-Wunused-parameter]
    virtual void enter_record(const glsl_type *type, const char *name,
                                                                 ^
link_uniforms.cpp:556:65: warning: unused parameter 'name' [-Wunused-parameter]
    virtual void leave_record(const glsl_type *type, const char *name,
                                                                 ^
link_uniforms.cpp:567:34: warning: unused parameter 'last_field' [-Wunused-parameter]
                             bool last_field)
                                  ^

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

mesa: Restore functionality to dispatch sanity test

Along with a couple secondary goals, the dispatch sanity test had two
major, primary goals.

1. Ensure that all functions part of an API version are set in the
   dispatch table.

2. Ensure that functions that cannot be part of an API version are not
   set in the dispatch table.

Commit 4bdbb58 removed the tests ability to fulfill either of its
primary goals by removing anything that used _mesa_generic_nop().  It
seems like the problem on Windows could have been resolved by adding the
NULL context pointer check from nop_handler to _mesa_generic_nop().
There is, however, some debugging benefit to actually getting the
(supposed) function name logged in the "unsupported function called"
message.

The preceding commit added a function, _glapi_new_nop_table, that
allocates a table of per-entry point no-op functions.  Restore the
ability to actually validate the sanity of the dispatch table by using
_glapi_new_nop_table.

Previous to this commit removing a function from one of the
*_functions_possible lists would not cause the test to fail.  With this
commit removing such a function will result in failure, as is expected.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965: Fix variable indexing of sampler arrays under non-uniform control flow.

ARB_gpu_shader5 requires sampler array indexing expressions to be
dynamically uniform, this however doesn't have any implications on the
control flow that leads to the evaluation of that expression being
uniform.  Use emit_uniformize() to obtain an arbitrary live value from
the binding table index calculation instead of assuming that the first
channel is always live.

Fixes the following Piglit test cases:
  arb_gpu_shader5/execution/sampler_array_indexing/fs-nonuniform-control-flow.shader_test
  arb_gpu_shader5/execution/sampler_array_indexing/vs-nonuniform-control-flow.shader_test

part of the series:
  http://lists.freedesktop.org/archives/piglit/2015-February/014615.html

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Fix variable indexing of UBO arrays under non-uniform control flow.

ARB_gpu_shader5 requires UBO array indexing expressions to be
dynamically uniform, this however doesn't have any implications on the
control flow that leads to the evaluation of that expression being
uniform.  Use emit_uniformize() to obtain an arbitrary live value from
the binding table index calculation instead of assuming that the first
channel is always live.

Fixes the following Piglit tests:
  arb_gpu_shader5/execution/ubo_array_indexing/fs-nonuniform-control-flow.shader_test
  arb_gpu_shader5/execution/ubo_array_indexing/vs-nonuniform-control-flow.shader_test

part of the series:
  http://lists.freedesktop.org/archives/piglit/2015-February/014616.html

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Define helper function to copy an arbitrary live component from some register.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Perform basic optimizations on the FIND_LIVE_CHANNEL opcode.

v2: Save some CPU cycles by doing 'return progress' rather than
    'depth++' in the discard jump special case.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.

This instruction calculates the index of an arbitrary channel enabled
in the current execution mask.  It's expected to be used as input for
the BROADCAST opcode, but it's implemented as a separate instruction
rather than being baked into BROADCAST because FIND_LIVE_CHANNEL has
no dependencies so it can always be CSE'ed with other instances of the
same instruction within a basic block.

v2: Whitespace fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Perform basic optimizations on the BROADCAST opcode.

v2: Style fixes.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Introduce the BROADCAST pseudo-opcode.

The BROADCAST instruction picks the channel from its first source
given by an index passed in as second source.  This will be used in
situations where all channels from the same SIMD thread have to agree
on the value of something, e.g. a surface binding table index.

This is in particular the case for UBO, sampler and image arrays,
which can be indexed dynamically with the restriction that all active
SIMD channels access the same index, provided to the shared unit as
part of a single scalar field of the message descriptor.  Simply
taking the index value from the first channel as we were doing until
now is incorrect, because it might contain an uninitialized value if
the channel had previously been disabled by non-uniform control flow.

v2: Minor style fixes.  Improve commit message.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Keep track of the early_fragment_tests flag in gl_shader.

And rename _mesa_glsl_parse_state::early_fragment_tests to
fs_early_fragment_tests for consistency with other FS-specific flags in the
same struct.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Error out on invalid uses of the early_fragment_tests layout qualifier.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Forbid use of image qualifiers in declarations of type other than image.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Split off memory qualifiers from storage qualifiers.

Image memory qualifiers (coherent, volatile, restrict, readonly and writeonly)
follow slightly different rules from storage qualifiers, e.g. the uniqueness
rule doesn't apply.  Make them a separate non-terminal.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Forbid opaque variables as operands of the ternary operator.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Update image unit state when glBindImageTexture is called with texture=0.

There's no indication in the spec that the image unit state other than the
bound texture object shouldn't be updated when glBindImageTexture() is called
passing the zero texture as argument.  It's very unlikely that any application
would ever have relied on this, but it's easy to get right, and it fixes the
"state" ARB_shader_image_load_store piglit test.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Initialize image units to default state on context creation.

This is the required initial image unit state according to "Table 23.45. Image
State (state per image unit)" of the OpenGL 4.3 specification.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Implement image uniform queries.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Validate original image internal format rather than derived mesa format.

This matches what _mesa_BindImageTextures() does.  The derived image format
(gl_texture_image::TexFormat) isn't necessarily equivalent to the internal
format of the texture image.  If a forbidden internal format has been
specified we need to mark the image unit as invalid as required by the spec,
regardless of the derived format.  Fixes the "invalid"
ARB_shader_image_load_store piglit test.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Call _mesa_test_texobj_completeness() before using _MaxLevel in image validation.

gl_texture_object::_MaxLevel doesn't have any meaningful value until
_mesa_test_texobj_completeness() has been run.  Fixes the "level"
ARB_shader_image_load_store piglit test.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Add support for binding a buffer texture to a shader image unit.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Add extern "C" guards to shaderimage.h to allow inclusion from C++ code.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: Export shader image format to mesa format conversion function.

This function will be useful for back-ends to translate an image internal
format as specified in GLSL code into a mesa format.

Reviewed-by: Matt Turner <mattst88@gmail.com>

swrast: Fix rgba_draw_pixels with GL_COLOR_INDEX

When we implemented the format conversion rewrite we forgot to handle
GL_COLOR_INDEX here, which needs special handling.

Fixes the following piglit test:
bin/gl-1.0-drawpixels-color-index -auto -fbo

Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90213

Tested-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Add memory fence opcode.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add typed surface access opcodes.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Add untyped surface write opcode.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Reorder sources of the untyped atomic opcode.

This is consistent with the untyped surface read opcode.  From now on
all typed and untyped surface access opcodes will follow the same
pattern: src[0] will be the message payload, src[1] will be the
surface index and src[2] will be a control immediate (atomic operation
for atomic opcodes and number of vector components for surface read
and write opcodes).

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass the number of components as a source of the untyped surface read opcode.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Add support for untyped surface message sends from GRF.

This doesn't actually enable untyped surface message sends from GRF
yet, the upcoming atomic counter and image intrinsic lowering code
will.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't request untyped atomic writeback message if the destination is null.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Simplify generator code for untyped surface messages.

The generate_untyped_*() methods do nothing useful other than calling
the corresponding function from brw_eu_emit.c.  The calls to
brw_mark_surface_used() will go away too in a future commit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix the untyped surface opcodes to deal with indirect surface access.

Change brw_untyped_atomic() and brw_untyped_surface_read() to take the
surface index as a register instead of a constant and to use
brw_send_indirect_message() to emit the indirect variant of send with
a dynamically calculated message descriptor.  This will be required to
support variable indexing of image arrays for
ARB_shader_image_load_store.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

ilo: use ilo_image exclusively in core

Initialize ilo_view_surface and ilo_zs_surface from ilo_image instead of
ilo_texture.

ilo: add ilo_image_can_enable_aux()

It replaces ilo_texture_can_enable_hiz().

ilo: make ilo_image more self-contained

Add depth0, sample_count, and scanout to ilo_image.

ilo: add ilo_image_init_for_imported()

It replaces ilo_image_update_for_imported_bo() and enables more error
checkings for imported textures.

ilo: prepare for image init for imported bo

Refactoring in prepraration for ilo_image_init_for_imported().

ilo: constify ilo_image_params

Make ilo_image_params const in functions that do not modify it.

ilo: improve readability of ilo_image

Improve docs, rename struct fields, and reorder walk types.  No real changes.

ilo: move command builder to core

ilo: move ilo_state_3d* to core

ilo state structs (struct ilo_xxx_state) are moved as well.

ilo: add ilo_buffer.h to core

Rename the original ilo_buffer to ilo_buffer_resource to avoid name conflict.

ilo: move BOs from ilo_texture to ilo_image

We want to work with ilo_image instead of ilo_texture in core.

ilo: move ilo_layout.[ch] to core as ilo_image.[ch]

Move files and s/layout/image/.

ilo: add ilo_format.[ch] to core

The original ilo_format.[ch] are removed.

ilo: add ilo_fence.h to core

Implement pipe_fence_handle on top of ilo_fence.

ilo: add ilo_dev_init() to core

Move init_dev() from ilo_screen.c to core.

ilo: rename ilo_dev_info to ilo_dev

With intel_winsys being embedded in it, drop the "_info" suffix.

ilo: move intel_winsys to ilo_dev_info

We want to use ilo_dev_info instead of ilo_screen in core.

ilo: add ilo_dev.h to core

Move what are remaining in ilo_common.h (that is, ilo_dev_*) to ilo_dev.h.

ilo: add ilo_debug.[ch] to core

They consist of the debug helpers that used to live in ilo_common.h and
ilo_screen.c.

ilo: add ilo_core.h to core

ilo_core.h includes the common gallium headers that were included in
ilo_common.h.

ilo: move intel_winsys.h to core

Add a new subdirectory and start moving files that do not depend on
ilo_screen/ilo_context to it.

i965: Upload atomic buffer state for compute shaders

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit MEDIA_STATE_FLUSH after WALKER

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Implement brw_emit_gpgpu_walker

Tested on Ivybridge, Haswell and Broadwell.

v2:
 * Use SET_FIELD. (Ken)
 * Use simd_size / 16 to support SIMD8/16/32. Ken suggested
   that we might be able to do it arithmetically rather than just
   supporting SIMD8 and SIMD16 with a conditional.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/state: Emit pipeline select when changing pipelines

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Implement DispatchCompute() back-end

brw_emit_gpgpu_walker will be implemented in a subsequent patch.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

main/cs: Implement front end code for glDispatchCompute().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add DispatchCompute() to driver function table.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit state base address

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add CS shader time support

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Upload brw_cs_state

v3:
 * Add defines. Misc cleanup suggestions. (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Support CS program precompile

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.

Suggested-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Emit compute shader code and upload programs

v2:
 * Don't bother checking for 'gen > 5' (krh)
 * Populate sampler data in key (krh)

v3:
 * Drop no8 support, and simplify code in several places (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Set invocation counts based on max_cs_threads

For ES, we set the max counts based on SIMD8, which is currently
accurate.

For desktop GL, we set the max counts based on SIMD16, which can fail
in some cases where a SIMD16 program is not currently supported.
Therefore, this value is not currently accurate, but will work fine in
many cases, and lets us run more test cases. Eventually we want to
always be able to generate a SIMD16 program.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add max_cs_threads

Add values for gen7 & gen8. These are the number threads in a
subslice.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove comment about chv device numbers being preliminary

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Support compute programs in fs_visitor

v2:
 * Clean out some unneeded code copied from run_fs (krh)
 * Always use NIR
 * Split shader time out into a separate commit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cache: Add support for CS in program state cache

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.

jordan.l.justen@intel.com:
 * Added brw_cs_prog_key structure
 * Added brw_cs_prog_data::dispatch_grf_start_reg_16
 * Added brw_cs_prog_data::local_size
 * Added brw_cs_prog_data::simd_size

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE

v2:
 * Don't rely on brw_eu* to generate the send instruction. We now
   generate the send here, and drop the "i965/cs: Add support for the
   SEND message that terminates a CS thread" brw_eu* patch.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE

v2:
 * Do more work at the visitor level. g0 is loaded and sent to the
   generator now.

v3:
 * Use Ken's comment explaining g0 usage

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add CS_OPCODE_CS_TERMINATE

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROG

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add an INTEL_DEBUG=cs option.

At the moment it's not wired up to anything.  Later patches will hook
it up to the compute shader back-end.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add compute support to update_program().

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Update program.c for compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/cs: Add inline functions for dealing with compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.

Also add code to brw_upload_state to set it when the compute program
changes.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Strip trailing constant zeroes in sample messages

If a send message is emitted with a message length that is less than
required for the message then the remaining parameters default to
zero. We can take advantage of this to save a register when a shader
passes constant zeroes as the final coordinates to the sample
function.

I think this might be useful for GLES applications that are using 2D
textures to simulate 1D textures.

On Skylake it will be useful for shaders that do
texelFetch(tex,something,0) which I think is fairly common. This helps
more on Skylake because in that case the order of the instruction
operands are u,v,lod,r which is good for 2D textures whereas before
they were u,lod,v,r which is only good for 1D textures.

On Haswell:
total instructions in shared programs: 8535730 -> 8533261 (-0.03%)
instructions in affected programs:     236968 -> 234499 (-1.04%)
helped:                                1174

On Skylake:
total instructions in shared programs: 10345646 -> 10341237 (-0.04%)
instructions in affected programs:     293011 -> 288602 (-1.50%)
helped:                                1218

Reviewed-by: Matt Turner <mattst88@gmail.com>
v2: Applied suggestions by Kenneth Graunke:
    - Only apply on Gen5+
    - Apply to all texture opcodes, not just TEX and TXF.
    Moved the optimisation into the loop as suggested by Matt Turner.
    Fix the array index when there is a header.

i965/skl: Force the exec size to 8 when initing header for SIMD4x2

On Gen9+ there needs to be a header when sampling using SIMD4x2. The
header is set up by copying from the g0 register. Commit 07c571a39f
tried to fix this mov instruction to always use an exec size of 8
because previously it was incorrectly using 4. It did this by casting
the type of the destination register to vec8. This was done because
there is code in brw_set_dest to guess the exec size based on the
width of the dest register. However I misunderstood how this works
because it is actually only used when the width is less than 8. That
means the patch actually changed it to use the default exec size which
on SIMD16 would be 16 and the MOV would clobber over the first
register in the send message. This patch makes it additionally set the
default exec size to 8. This is similar to how the message is set up
in fs_generator::generate_tex.

I think this wasn't picked up by any Piglit tests because we don't
have any fragment shaders that hit this code path so nothing was using
SIMD16. However the patch caused failures in deqp tests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>

i965: Unhardcode a few more stage names and abbreviations.

The stage_abbrev and stage_name fields in backend_visitor provide what
we need without any additional effort.  It also means we'll get the
right names for compute shaders, SIMD8 geometry shaders, and both kinds
of tessellation shaders.

This does unfortunately change the capitalization of the stage
abbreviation in the INTEL_DEBUG=optimizer output filenames.  It doesn't
seem worth adding code to handle, though.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

docs/relnotes: document the new EGL sync extensions

st/dri: implement the fence interface for CL events

gallium,clover: add OpenCL interoperability support for CL events

v2: - move interop.cpp to clover/api
    - change intptr_t to void* in the interface
    - add a virtual function fence() to simplify some code

v3: - use bool in the interface
v4: - enclose the last two interop functions in try..catch

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

st/dri: implement the fence interface

egl/dri2: return the latest sync status in eglGetSyncAttribKHR