git.libre-soc.org Git - gem5.git/log

scons: fix --gold-linker build after --as-needed

The build was failing with:

/usr/bin/ld: unrecognized option '--as-needed -fuse-ld=gold'

and --verbose confirms that a single quoted CLI parameter was being
executed:

"-Wl,--as-needed -fuse-ld=gold"

This happened because at Ifb001786a66b0dd9b29865e39a5740313002f250
--as-needed was added, and because it is the second option to happen before
the following main.subst, it exposed the fact that the existing main.subst
was wrong, because it returns a string instead of the expected array.

Change-Id: I619d242d60fe9d27438638ac11c2b92512881f26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24624
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: add Watchdog Module SP805 model

This provides a model of the Arm Watchdog Module SP805. This is based
on the public TRM rev. r1p0 (ARM DDI 0270B). Integration test harness
is not supported. Auto-generation of device tree entries is provided.

Change-Id: I6157cec2212d0a1d2685bcfa983d2acbae1f3377
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24205
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: VExpress_GEM5_Base, add refclock 32KHz

This patch adds the reference 32KHz clock to VExpress_GEM5_Base derived
platforms. This is in preparation for supporting the SP805 Watchdog.
I/O voltage domain and platform clock domain coupling is transferred
to the __init__ method for correctness.

Change-Id: Ic743fd986793f1e43b75fa60260c9b43b2737763
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24204
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Fix python line break in m5_exit test

A bug has been introduced with the new test url.
The line break should have used a backslash or (this is the recommended
way by PEP8) the implied line continuation via parenthesis.
This error was preventing the test to be loaded with the error message:

Exception thrown while loading
"/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/m5_util/test_exit.py"
Ignoring all tests in this file.

and was not producing a failure (the test was not run: it was jus
ignored).

Change-Id: I0afe252d66d2f6546caaf5e7be811f34f88df82c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24625
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement CC reg accessors.

Change-Id: I4d8a7eaa097446b6aa3483880c2a7ed1a2e0d97c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23790
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Remove checkpointing from the ARM TLBs.

All of the state being checkpointed would either be provided by the
config directly, or would be brought into the TLB through normal fill
operations. Having this state in the checkpoint complicates the
checkpoint and significantly decreases compatibility with other TLB
implementations, or even variations of the same TLB, for instance if
the size was changed.

Change-Id: I4ea079dd01ff18fbc458b3aaaf88519dbcfdd869
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24389
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Get rid of the unused (and mostly undefined) zeroRegisters.

Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated CONTRIBUTING.md to discuss branches

There are some circumstances in which branches may be beneficial.
Though, in general, they should be discouraged. Therefore,
CONTRIBUTING.md has been enhanced to outline under what circumstances
creation of new branches is allowed and how they may be created and
used.

Change-Id: I2df8b38868e5c8146b068d9e7e957abbe3cf3b38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24263
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Add a timeout to getremotetime

The helper is meant to check if the local binary is younger than the
remote binary (on gem5.org). If the call fails it is giving up and
it is just using the local regression (producing a warning).
The code is not handling the blocking behaviour of the connection:
simulaton might stall indefinitely
The patch is addressing this by providing a 10 seconds timeout.

Change-Id: I8f9c2e555c9a55d850a66d02f8e55f56ceda2ca3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24531
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: add FixedClock SimObject

This patch adds a simple fixed-rate clock implementation based on
SrcClockDomain. This provides RealView-derived platform users with
a convenient way for auto-generating their platform clocks in the DTB.

Change-Id: Ifade0cc8ed1b9e3423745698442cac5d8b99ab63
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24223
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Adding --bin-path option to select tests bin directory

So far lots of tests will download binaries inside the gem5 directory.
The path is also specific to the test being run.
This doesn't play well with an environment where gem5 is cloned from
scratch for every build, or if several gem5 are cloned in a single
machine.
Binaries will be automatically downloaded every time this happens.

This patch is adding a --bin-path option, so that it's possible to
setup a fixed directory with all pre-downloaded binaries.
By default it is set to None to preserve original behaviour.

Change-Id: I42fb25e3ce0a495c73672b15a097b1bd2607795c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24525
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: fs/linux/arm passing M5_PATH via commandline

This will make it configurable from the testing framework

Change-Id: If82d5e44927c67a1eaecf41505d1d55a6469a4cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24524
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fix invalidation of prefetchers

Add an invalidation function to the AssociativeSet, so that entries
can be properly invalidated by also invalidating their replacement
data.

Both setInvalid and reset have been merged into invalidate to
indicate users that they are using an incorrect approach by
generating compilation errors, and to match CacheBlk's naming
convention.

Change-Id: I568076a3b5adda8b1311d9498b086c0dab457a14
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24529
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix EL2 target exception level for SP alignment fault.

This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.

Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Updated tests to download from dist.gem5.org

Previously some tests, and test resources, downloaded content from
http://gem5.org . This is being migrated to http://dist.gem5.org.
http://dist.gem5.org should be used to store and retrieve resources
going forward.

Change-Id: I7162c76b9b8dc07657a6ba50d643fc93c9824fdf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24548
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add print function to ReplaceableEntry

Add a basic print function to acquire and display information about
replaceable entries.

Change-Id: I9640113d305fbe086c5bfaf8928a911bfcac50bb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23567
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Add getter for the number of valid sub-blks

Add a getter function so that the number of valid sub-blocks can be
retrieved. As a side effect, make the respective counter private.

Change-Id: Icef8b51164c8e165872dcaebc65f5c330f16cb29
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22605
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add multiple eviction stats

Add stats to inform how many blocks were evicted due to a sector
replacement/eviction.

Change-Id: I886365506016d0888f835d182b3b65a808a9dccd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22606
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Make findVictim non-const

In order to acquire stats when a victim is found,
findVictim must be made const.

Change-Id: I493c7849f07625c90b2b95fd220f50751f4d0f52
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22604
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Add more compression stats

Add stats to calculate the total number of compressions, decompressions
and the average compression size, in number of bits.

Change-Id: I5eb563856c1ff54216e1edcd2886332b7481cbfe
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22609
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Factor out multiple block eviction

Create a function to try to evict multiple blocks while checking for
transient state.

Change-Id: I6a879fa5e793cd92c4bdf4a258a133de4c865012
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22607
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: MESI_Three_level python parameters

Allow specifying the L0 cache parameters via command line in
MESI_Three_Level.

Change-Id: Ie2a7f74790ed4c81c408857eccc2b439c60627f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24255
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: add Arm build_opts for MESI_Three_Level and MOESI_hammer

Change-Id: I0d1c5671efdd3cb2041805ab615cdff76d3a5e8a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

util: Add fastmodel in valid tag list

The "fastmodel" tag has been used since 2019-08-22 so it should be an
valid tag in commit header.

Change-Id: I0032deaabc94e5896851da9afc28e1b1a699fed3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23923
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: A couple small fixes for the arm64 bootloader makefile.

First, remove a deprecated flag that gcc no longer recognizes.

Second, disable suffix based implicit makefile rules. These, in
combination with the %.o: boot.S rule, were tricking make into deleting
it's own makefile. How, you might ask?

make wants to update its makefile, since that's a thing it does
automatically. This is useful if you, for instance, have computed
header dependencies.

make decides it can make a file called "makefile" from a file called
"makefile.o" by doing a linking step.

make decides it can make makefile.o from boot.S from the %.o: boot.S
rule, which it does.

It then attempts to link makefile.o into makefile, but that fails
because it lacks a "main" function since it's using a built in rule
which doesn't know not to expect main. The makefile is clobbered in the
process.

make then deletes makefile.o because it was an implicit target,
eliminating all the evidence.

Change-Id: Ib0dfc333dc554caf5772dd8468dba6ba821f98ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24329
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Renaming tests to include dash between words

In `gem/hello_se/test_hello_se.py`, test suites were being generated
with no space between the word "test" and the test name. A dash has now
been added to make this a more readable.

Change-Id: I9d115a5941cc28af5476175fcbf2bd6940920291
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23025
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Migrated old quick/se/00.hello tests

Migrated old quick/se/00.hello tests over to the new testing frame work
(i.e., that executed via `./tests/main.py run`). These fail, so they are
currently being ignored.

These tests now pull from the http://dist.gem5.org cloud storage.

Change-Id: Iff94cce53655bc629a3deb1e11d8d194824751d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23024
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-arm: ELIsInHost, check VHE and SecEL2

This patch modifies ELIsInHost to correctly check for VHE
and Secure EL2 implementation.

Change-Id: I947dddfc6761794493fef3d59b3b35754d07ed6b
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24046
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Virtualization Host Extensions checking

This patch adds Armv8.1-VHE checking. This is based on the bit
ID_AA64MMFR1_EL1.VH being 0b1.

Change-Id: Ia3f278c63fe1b5448a686db87a46853fc8b6bea5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24045
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: bigLITTLE with VExpress_GEM5_V2 in dtb

This patch adds targets in the device tree Makefile for using
bigLITTLE DTS with VExpress_GEM5_V2 platform.

Change-Id: I7a424a36c78a24b96224526aa112ac5d060f790b
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24083
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use smart pointers for CrossbarSwitch's members

Use smart pointers for the pointers managed by CrossbarSwitch.

Change-Id: I71958c72cde5981d730aa3f68bba0ffbe4c2506f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24244
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Stop clearing RAX for BIST in initCPU.

This doesn't actually change any behavior since RAX was being zeroed
anyway, but since we don't and almost certainly never will have a BIST
and the BIST is optional even in real hardware, we can drop it and
simplify initCPU a little further.

This reduces x86's initCPU function to just an invocation of
InitInterrupt's invoke.

Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24187
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

x86: Move local APIC initialization out of initCPU.

The APIC can (and probably should) set its version register on its
own. Also it already configures its CPUID register when associated
with a CPU and doesn't need initCPU to do that.

Change-Id: I4611563668d197c48caf2f23fcde9ec2ec101fe7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24186
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

x86: Move miscreg initialization to the ISA class.

The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.

Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove check for kernel in fs.py.

It is *not* true that a kernel is required in FS mode. For example,
in SPARC, gem5 is set up to run actual system firmware which will load
a kernel from the disk image. Other systems can run in a bare metal
mode where they also have no kernel.

If a configuration requires a kernel, it should check for it in C++
where there context lives, not globally in fs.py.

Change-Id: Ib094c29474c248f866bd08d4f975648a2c707a19
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24284
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a dumpSimcall mechanism to GuestABI.

This dumps a signature for a simcall as if it was going to be invoked,
and can be used for debugging.

Change-Id: I6262b94ad4186bac8dc5a1469e9bb3b8ae9d34e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23460
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a unit test for the GuestABI mechanism.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I76934d94b4c61570a4ca603388012c65280e2b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23197
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Implement a varargs like mechanism for GuestABI system.

This will let a function called with a GuestABI emulate the ...
mechanism available in C. To make that possible without the functions
knowing anything about the ABI and to follow C++'s (sensible)
templating and virtual function rules, you have to tell VarArgs what
types you might want to extract from it, unlike the pure ... varargs
style mechanism.

Also unlike ..., there is no mechanism in place to force the varargs
to appear last in the argument list. It will pick up the progress
through the arguments at the point it's reached, and will ignore any
later arguments. It would be possible to be more rigorous about this
by changing the callFrom templates, but the overhead in complexity
is probably not worth it.

Also, retrieving arguments through a VarArgs happens live, meaning at
the point that the argument is asked for. If the ThreadContext or
memory the argument lives in is modified before that point, the
retrieved value will reflect that modification and not what the
function was originally called with. Care should be taken so that this
doesn't cause corrupted arguments.

Finally, this mechansim (and the Guest ABI mechanism in general) is
complex and should have tests written for it. That should be possible
since ThreadContext is forward declared and so the test can say it
works however it wants or even ignore it completely. If that changes
in the future, we may need a mock ThreadContext implementation.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I37484b50a3e8c0d259d9590e32fecbb5f76670c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23195
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: keep SC_CONCAT* macro

Call of TLM_DECLARE_EXTENDED_PHASE requires SC_CONCAT* macros. This change
keeps those macros to avoid compile errors.

Change-Id: I573c4c126a350ef1a752d1c50658e7d9cedaaeae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24123
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Make the generic micropc enabled PCState set nupc to 1.

The default constructor of the micropc enabled generic PCState class
set the next micropc to 0, when the non-default constructor and at
least the x86 initCPU utility function set it to 1. This makes more
sense since either the micropc doesn't matter as a concept if the
instruction isn't microcoded, or, unless redirected by a micropc
branch, you're going to want to execute the next microop and not just
repeat the first one.

Change-Id: I418ea986a071453563c4c8aad4fc4eb4f7beb641
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24184
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: VExpress_GEM5_Base, fix daughterboard reference

VExpress_GEM5_Base states that its memory map is based on
CoreTile Express A15x2 A7x3, while the model used for the
Daughterboard Configuration Controller (DCC) is based on
Coretile Express A15x2.
These two daughterboard specifications differ in both on-chip
memory map and DCC clocks as of the TRMs.

This patch makes the reference consistent to Coretile Express
A15x2 and adds several non-confidential references to aid in
understanding the platform and adding new peripherals.

Change-Id: Ia55e7362bdc9ed6509f8eff4cbd7eb38e538d774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24203
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,base: Added GTest for base/socket.cc

It should be noted that some features of this class have not been fully
tested due to interaction with system-calls.

Change-Id: I8315188327e022ac4c98aa9ce4bd38243266ab17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23984
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Updated gtest/logging.cc to print log rather than fail.

Previously the `GTestExitLogger.log` function utilized GTest's
`ADD_FAILURE_AT` macro. This meant, whenever `GTestExitLogger.log` were
called, the calling test would be fail. This is problematic when
trying to test code we expect to fail (i.e., when testing the error
handling code is working correctly). Therefore, the `log` function now
writes to stderr.

The `GTestExitLogger` class is used by the `panic` and `fatal` loggers
when running GTests. Instead of callnig `exit(1)` they throw a GTest
exception, which can be captured in a test using
`EXPECT_ANY_THROW(expection_thrower())`. Catching and verifying error
logs can be done via:

```
testing::internal::CaptureStderr();
/*
* "exception_thrower()" is a method we'd expect to call `fatal` or
* `panic`, and therefore exit the simulation with a non-zero exit
* code. When running via GTest, an exception is thrown instead.
*/
EXPECT_ANY_THROW(exception_thrower());
EXPECT_EQ("<error message>", testing::internal::GetCapturedStderr()));
```

Change-Id: I84a5f86bc573668d3dd5b40f626b43108dddb8e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23983
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Include some required headers in amo.hh.

amo.hh was using several non-default definitions including
std::function, uint8_t, and std::array without including any headers
at all, and instead apparently relying on those having already been
brought in by an earlier include.

This change adds those includes explicitly.

Change-Id: I92166ff581e74bd705e10fd4fa454df179ae1a97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24183
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base, gpu-compute: Move gpu AMOs into the generic header

Change-Id: I10d8aeaae83c232141ddd2fd21ee43bed8712539
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23565
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added functionality to allow the ignoring of test suites

Previously, when `tests/main.py run` was executed all the tests found
were run. It is now necessary to ignore some test suites as they fail.
Therefore, `gem5/suite.py` has been updated to read from `gem5/.testignore`
(if present). This file contains a list of all the test suites which are to
be ignored.

Change-Id: I699ea662b701d82199980084261496f24b13d340
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23023
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base: Move arm AtomicOpFunctor into the generic header

These AtomicGenericxOp functors are not arm specific:
They just define a set of different functors depending
on the number of operands they are using.

Change-Id: Ida75066823c7718aee05717194cdb8225b700c5d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23564
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Move AtomicOpFunctors to a dedicated header

src/base/types.hh file definition is:

/**
* @file
* Defines global host-dependent types:
* Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
*/

I feel AtomicOpFunctor doesn't fall in this cathegory so I am
moving those into a dedicated header: base/amo.hh

Change-Id: I8f05fb0944c03e4053cfaf2ffe65cac803df1d93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23563
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add '-Wl,--as-needed' to default LINKFLAGS

In current build flow, EXTRAS flag is evaluated before building gem5
tools and binaries. Such that, unneeded libraries may be linked into
gem5 binaries. Adding '-Wl,--as-needed' can fix this problem also
shrinks binaries.

Change-Id: Ifb001786a66b0dd9b29865e39a5740313002f250
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24003
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Promote the m5ops_base param to the System base class.

This mechanism is shared between ARM and x86, even if x86 has a typical
address range it choses to use. By moving this to the base class, it's
now possible for anybody to find out where the m5 ops are, and no ISA
specific assumptions need to be made.

Because the x86 address is well known, it's set in the x86 System
subclass as the default.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ifdb9f5cd1ce38b3c4dafa7566c50f245f14cf790
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23180
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Disable O3CPU value forwarding with write strobes

https://gem5-review.googlesource.com/c/public/gem5/+/19173 did the same
for MinorCPU

Change-Id: I22d631a3d2032570f6e84b0f5eb018d1f84414ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23952
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Use enums for O3CPU store value forwarding

This is aligning with MinorCPU, where an enum is tagging a Full, Partial
and No address coverage.

Change-Id: I0e0ba9b88c6f08c04430859e88135c61c56e6884
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23951
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: GICv2/GICv3 have different Distributor addresses

https://gem5-review.googlesource.com/c/public/gem5/+/22823 didn't
take into consideration that GICv3's Distributor is placed at a
different address than GICv2's one.
This is reflected by the value in VExpress_GEM5_V2 and in the
FDT in system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi

Change-Id: Ie7661d4e9d3db0c5fe9eb9cea3a24a5e7c266676
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23953
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Rename ARM bootloader source

The AArch32 assembly source has been renamed from simple.S to boot.S,
and the Makefile has been renamed to makefile (lowercase) to match
the AArch64 convention

Change-Id: Ia4581fe0223c156460edcc558622b5d7962258dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23949
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Rename ARM bootloader directories

The patch is renaming:

system/arm/simple_bootloader -> system/arm/bootloader/arm
system/arm/aarch64_bootloader -> system/arm/bootloader/arm64

Change-Id: Ia7380be3914e277624060f1c96361a0f16dbea9d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23948
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Reflect changes of arm bootloader name

With https://gem5-review.googlesource.com/c/public/gem5/+/22687 the
VExpress_GEM5_Base platform is changing the required bootloader name
by removing the _emm suffix.
While this had been changed in the prebuilt binaries in gem5.org, it
hadn't in the bootloader makefiles or in other utility functions.

The patch is not completely removing the _emm bootloaders since those
are still used by VExpress_EMM and VExpress_EMM64 platforms.

Change-Id: Iea3148eab313ab06cf2e74660e11708e1a22ce5f
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23947
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Cleanup code that enables asan and ubsan

Change-Id: Ie29efc99067dac051536bb099a89f29c940192ec
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23883
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Forward snoops when the cache is not responding

When the MSHR is handling a request that will make the block dirty the
current cache commits respond. When that's not the case the cache
should forward any snoops. This CL fixes MSHR::handleSnoop() to
implement this behavior.

Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23668
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

mem-cache: Ensure that responses get data from the right source

This CL makes sure that we use the right source for data for
responses after a response from the cache below.

Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23667
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: fix gem5_to_tlm bridge

The original implementation doesn't set trans and phase correctly when
scheduling PayloadEvent, and causes unexpected behavior after the event started.

This change fixes the wrong event triggering by directly applying
tlm_utils::peq instead of creating another one.

Change-Id: I207567b57f4b49c3c4ebe117d624e5cc9915c12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23823
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement the vecPredReg accessor functions.

Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Stop decoding the pseudo inst subfunc value.

This isn't used by anything any more. The func field is left in place
to ensure compatability, but there's no reason to decode a value
nobody is going to use.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Use the guest ABI mechanism with pseudo instructions.

Right now, there are only two places which call the pseudoInst function
directly, the ARM KVM CPU and the generic mmapped IPR. These two
callers currently use the generic "PseudoInstABI" which is just a
wrapper around the existing getArgument function.

In the future, this getArgument function will be disolved, and the
PseudoInstABI will be defined for each ABI. Since it currently mimics
the Linux ABI since gem5 can only handle one ABI at a time right now,
this implementation will probably be shared by linux system calls,
except that the pseudo inst implementation will eat return values since
those are returned through other means when the pseudo inst is based on
magic address ranges.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Semihosting, specify files root dir

This patch adds an option to "ArmSemihosting" which allows for
specifying an optional search path for host files.
Previously, behaviour was fixed to search in the directory from where
the gem5 binary was run from.

Change-Id: I57b932b38d022f132af78857104633d7bfdd1442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23903
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix SMMUv3 walkMasks in page table ops

The masks did not include the high bits above the active addressing
bits.
This could cause overlapping issues when using high addresses.
(Translated with TTBR1)

Change-Id: Ib705558aac456c1b3f069e1bd3ccdd9229a1c1d2
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix SMMUv3 16KB next-level table address masking

The next-level table address for a granule size of 16KB is retrieved
from the 47:14 bits of the current table descriptor (instead of
47:12, which is the valid masking for a 4KB granule)

Change-Id: I570138a34003dc034d8e67dc1209316157d57205
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23763
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour

Architecture states write accesses to GICR_ICFGR0 are WI. This patch
implements handling of this behaviour instead of crashing as an invalid
offset. This is required to support certain software behaviour.

Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Avoid write merging if there are reads in between

This CL reworks the logic in the MSHR to make sure we do not coalesce
requests unless there is a series of write requests for the whole
cache block without any other incompatible requests (e.g., read) in
between.

Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23666
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

configs-arm: enable PMU instantiation in CpuCluster

This patch adds a new method to the CpuCluster object
which allows passing the PMU interrupt numbers and events
to record for each core.
This lets users create CPU clusters with PMUs.

Change-Id: Id49fd0aee50f49e4c6fca95e4ee673da3dca73cd
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22848
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move destructor of Port to public

To preventing from instantiating an abstract class, hiding its
constructor is enough. Moving destructor to public doesn't break this
intention. This also makes us can use smart pointer to manage derived
Port class.

Change-Id: Ic9cf97e90a6c26108d359eb459df48cd23eaf15c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23925
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix issue with MinorCPU predicated-false mem. accesses

The code block was relying on passed_predicate only (conditional
execution). This was not covering the case where the instruction
gets executed, but the predicate register is false. Using the inLSQ
variable is covering both cases and it makes more sense in terms of
readibility.

Change-Id: Ie1954f37968379a5bda9d0dc9f824a68304cc229
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23280
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Disable MinorCPU value forwarding with write strobes

Change-Id: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19173
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added 'fastmodel' to MAINTAINERS

Gabe Black added as the maintainer.

Change-Id: I69273d090bf17da4e54f50340a33a589fdc63c51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23963
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix compilation errors

This changes fixes two compilation errors when compiling with
FastModels. One is that CurrentMsn should be Iris::CurrentMsn and the
other is that currEL() function needs arch/arm/utility.hh header file.

Test by compiling GEM5 with FastModels:
scons -j64 build/ARM/gem5.opt \
  USE_ARM_FASTMODEL=1     \
  PVLIB_HOME=...          \
  MAXCORE_HOME=...        \
  ARMLMD_LICENSE_FILE=... \

Change-Id: Iabe0a5f25246591f99b57219428b8f87ecd3363c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23924
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.

Now that the IRIS thread context can be specific to ARM, some things
which had been pushed to a different level of abstraction can be mvoed
back. This will hopefully allow more code sharing in the future when
other types of CPUs are supported.

Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Move the ARM IRIS threadcontext into CortexA76.

This specialization will correspond specifically with the CortexA76,
instead of specializing the ThreadContext for ARM in general. Some
aspects of this class may need to move into the base IRIS thread
context class, but I'll leave that for a later change.

Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.

Fast models are in practice only ARM, so it's not that helpful to have
the ARM-ness factored out. It is, however, helpful to have aspects
which control how gem5 concepts like registers are mapped to fast model
concepts like resources, especially since these mappings may vary from
fast model to fast model.

For instance, it looks like the CortexA76 does not have predicate
vector registers. Rather than make all fast models support or not
support those registers, that can be done on a model by model basis.

Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.

The generic thread context checkpointing code can be used which calls
into the ThreadContext methods to read the required state.

Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Handle "special" vector regs without calling into IRIS.

These registers don't have an architectural equivalent, but they may
need to be accessed by generic code, for instance the code that
checkpoints a thread context.

Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement readVecRegFlat for ArmThreadContext.

This just calls readVecReg after constructing a RegId.

Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Determine what space to use for breakpoints dynamically.

This was hardcoded as 5, but should be determined based on the memory
space IDs the fast model returns. What we do now is have a specific
override for ARM (perhaps conceptually the A76) which looks for an
address space called "Current" which seems to work well.

It's possible that the appropriate address space for a different model
might have a different number, or even a different name. This may need
to be further specialized/parameterized in those cases.

Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement PC based events.

These use the IRIS breakpoint API to stop the models at the appropriate
points. There seems to be a slightly wonky interaction between
breakpoints and stepping, where if you stop at a breakpoint and then
step, you might end up moving forward more than the number of requested
instructions.

Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Always print stderr in gem5 Fixtures

At the moment is impossible when observing an upstream kokoro failure
to understand what went wrong.
This is because the only thing that gets printed is the exception
traceback and the command line generating it.

Most of the time it will be something like

Traceback (most recent call last):
  File
"/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/runner.py", line
195, in setup
    fixture.setup(testitem)
  File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line
115, in setup
    self._setup(testitem)
  File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line
160, in _setup
    log_call(log.test_log, command)
  File
"/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/helper.py", line
103, in log_call
    raise subprocess.CalledProcessError(retval, cmdstr)

With this patch we dump the stderr so that the fail reason is exposed
to the viewer.

Change-Id: Ic3d0fe75ec4d0543d95e9624dc5287afb4af3b8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23843
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Fix negative op-assign of SatCounter

The value of the add and subtract assignment operations can be negative,
and this was not being handled properly previously. Regarding shift
assignment, the standard says it is undefined behaviour if a negative
number is given, so add assertions for these cases.

Change-Id: I2f1e4143c6385caa80fb25f84ca8edb0ca7e62b7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23664
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: arm realview(64) regressions using VExpress_GEM5_V1

This patch is updating the arm regression configs so that the newer
VExpress_GEM_V1 platform is used instead of the older VExpress_EMM and
VExpress_EMM64.
A new optional kernel_mode argument has been added in order to
distinguish between realview and realview64 platforms. If not provided
the config will assume the machine is running a AArch64 kernel.

Other notable additions:
- DTB autogeneration in regressions
- Using minimal m5exit.squashfs disk image

Change-Id: Ia230565f072fe3eb7756c41876dba4657583f4df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22687
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

systemc: Fix tlm2 socket integration

This change will make the systemc extension in gem5 more compatible to
the reference implementation by Accellera.

* Remove the alias of sc_port's bind in initiator socket.
* Ignore -Woverloaded-virtual in initiator socket.

Change-Id: I229e4d493e01d26174c5662ad71d4859d546d307
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23864
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Fix clang warnings

Fix some warnings reported by clang.

* missing override in {freebsd,linux}/process.hh

Change-Id: I67c36a0785ac90614211d640fd58d3ffe187c17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23863
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix decoding of LDFF1x scalar plus scalar

First-faulting loads do allow Rm == 0x1f.

Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Semihosting, fix SYS_FLEN

SYS_FLEN was incorrectly handled as SYS_ISTTY. This patch fixes this
behaviour.

Change-Id: I66e0b97d8b44d2cb78e0b1bb940fd6f4b52c658f
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23752
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: kernelExtras optional load addresses

This patch provides a new "System" parameter named "kernel_extras_addrs".
This allows to optionally specify fixed load addresses for the
additional kernel objects. This is useful to load arbitrary blobs into
memory.

Change-Id: I4725763b86c29f72282d1c184d4284d90f9d3016
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23566
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: fix "fatal" usage in fdthelper

"fatal" was not correctly imported in the fdthelper module,
which caused a crash when reporting errors.

Change-Id: I7ee9dcde1f0288e11e56dba67ead4aa2d6d67e02
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23753
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Secure EL2 checking

This patch adds Armv8.4-SecEL2 checking. Helpers implementing
EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following
the architecture pseudocode are provided. These are intended
to be used for checking register access permissions.

Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: AArch64 trap check, arbitrary ECs/Imms

This patch generalises trap checking when accessing system registers
in AArch64. Depending on the accessed register, a different Exception
Class (EC) and immediate value may be set.
Previously this only took SIMD traps into account.

Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix some bugs with KVM in SE mode on Intel machines.

The granularity bit should be set since the segment limit should be
interpreted as a number of pages, not bytes.

A comment indicates that NX support is enabled, but the bit wasn't
being set. That's now set to be consistent with FS mode.

The SVME bit is now turned off, since Intel CPUs don't have SVME, and
enabling it apparently makes them upset.

Also disable CR4 bits which enable features neither gem5 nor apparently
my workstation support.

Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Include some required headers in the syscall debug macros header.

Everything that includes syscall_debug_macros.hh and uses the macro in
it will need these headers, so they should be included through
syscall_debug_macros.hh. The consumer shouldn't have to know what the
macros use internally and to include extra headers to support them.

Change-Id: I9bfa932368daec0772d552357ecad8790b4cfead
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23459
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

fastmodel: Tell fast model not to shutdown when time stops.

Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement port proxies.

This plumbing is simple and largely copied from other implementations
within gem5. This mechanism should be refactored so that the
duplication is unnecessary.

Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Create a TLB model which uses IRIS to do translations.

Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Add an address translation mechanism to the ThreadContext.

This will be used by the TLB to do the actual translation.
Unfortunately there isn't a great way to tell what translation type to
use, so we just go through all of them for now. The ARM subclass might
specialize and figure out which address spaces to use based on control
register state.

Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>