panfrost: Take into account texture layers in SFBD

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Rework format encoding on SFBD

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Set 0x10 bit on mali_shader_meta.unknown2_4 on T720

Testing shows that it's needed.

Also remove ctx->is_t6xx as it was the last use of it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Add checksum fields to SFBD descriptor

During tests on T720, these fields were discovered.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

zink: do advertize integer support in shaders

This is supported, so let's correct this.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

zink/spirv: implement ball_fequal[2-4]

zink/spirv: implement ball_iequal[2-4]

zink/spirv: implement bany_inequal[2-4]

zink/spirv: implement bany_fnequal[2-4]

zink/spirv: support loading bool constants

Seems I missed this before; let's add support for this.

zink/spirv: drop temp-array for component-count

gitlab-ci: Don't build libdrm for ARM

The Debian packages work fine. Saves a little bit of time and disk
space.

Reviewed-by: Eric Anholt <eric@anholt.net>

gitlab-ci: Use separate arm64 build/test docker images

The image used for test jobs is only about 1/6 as big as before, which
may help avoid some issues with some of the test boards.

Inspired by https://gitlab.freedesktop.org/mesa/mesa/issues/2046 .

v2:
* Leave LIBDRM_VERSION at 2.4.99 (Daniel Stone)
* Delete more build artifacts from dEQP tree (Daniel Stone)
v3:
* Set LD_LIBRARY_PATH for ldd

Acked-by: Daniel Stone <daniels@collabora.com> # v2
Reviewed-by: Eric Anholt <eric@anholt.net> # Except for the ldd line

zink: use u_blitter when format-reinterpreting

zink: always allow sampling of images

This is required if we're going to blit from/to it using u_blitter.

zink: transition resources before resolving

zink: disable fragment-shader texture-lod

We don't support nir_texop_txd, which is required by this cap. So let's
disable it for now.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16e ("zink: introduce opengl over vulkan")

zink: make sure src image is transfer-src-optimal

Fixes: d2bb63c8d4c ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")

zink: do not advertize coherent mapping

We do not support them yet, so let's not pretend.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16e ("zink: introduce opengl over vulkan")

zink: always allow mutating the format

There's no good way to know if a texture-view will be created, so we
just have to accept it for all resources.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16e ("zink: introduce opengl over vulkan")

zink: use actual format for render-pass

We should use the format derived from the image-view here, not from the
image itselt. Otherwise, we'll end up with incompatible render-passes.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 8d46e35d16e ("zink: introduce opengl over vulkan")

radeonsi: fix shader disk cache key

Use unsigned values otherwise signed extension will produce a 64 bits value where
the 32 left-most bits are 1.

Fixes: 2afeed30101 ("radeonsi: tell the shader disk cache what IR is used")

radv: implement VK_EXT_subgroup_size_control

This extension allows to control the subgroup size by allowing a
varying subgroup size and also specifying a required subgroup size.

This implementation only allows to specify a required subgroup
size for compute shaders because there is some caveats with
other shader stages (eg. NGG with geometry shader). This
basically allows apps to use Wave32 for compute shaders.

This extension is enabled for all chips but only GFX10 supports
Wave32. ACO doesn't support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: rely on shader's wavesize when computing NGG info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: determine shaders wavesize at pipeline level

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: hardcode the number of waves for the GFX6 LS-HS bug

It's always 64.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv/gfx10: enable wave32 for compute based on shader's wavesize

This will allow to change wavesize on-demand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir: fix packing of nir_variable

The maximum number of descriptor sets is indeed 32 but without
the sign bit.

The maximum number of bindings for RADV is way larger, keep it
as 32-bit.

Fixes: 96e6ef80d93 ("nir: pack the rest of nir_variable::data")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>

radv: fix 32-bit compiler warnings

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2031
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add a note about perftest/debug options

Now that all environment variables are documented, it would be
appreciated if we can keep this up-to-date.

[skip ci]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

docs: document all RADV environment variables

Requested by https://gitlab.freedesktop.org/mesa/mesa/issues/2022

[skip ci]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

nir/serialize: pack nir_variable flags

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/serialize: store 32-bit object IDs instead of 64-bit

That means we have only 30 bits for object IDs, because 2 bits are
sometimes used for something else.

This decrease the uncompressed shader size for the biggest Borderlands 2
shader from 33.6 KB to 23.2 KB. (31% decrease)

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/serialize: don't expand 16-bit variable state slots to 32 bits

the swizzle also needs only 16 bits

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: pack the rest of nir_variable::data

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

radeonsi: keep serialized NIR instead of nir_shader in si_shader_selector

This decreases memory usage, because serialized NIR is more compact.

The main shader part is compiled from nir_shader.
Monolithic shader variants are compiled from nir_binary.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: don't keep compute shader IR after compilation

not needed. We also need to free TGSI in the destroy function for the case
when an app is terminated and si_create_compute_state_async is never
executed because of util_queue_drop_job.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: use IR SHA1 as the cache key for the in-memory shader cache

instead of using whole IR binaries. This saves some memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

lima: add support for gl_PointSize

GP handles gl_PointSize similar to gl_Position, i.e. it needs
separate buffer and it has special type in varying descriptors, also
for indexed draw we need to emit special PLBU command to pass
address of gl_PointSize buffer.

Blob also clamps gl_PointSize to 1 .. 100 (as well as line width),
so let's do the same.

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

mesa/imports: let the build system detect strtok_r()

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2013
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Prodea Alexandru-Liviu <liviuprodea@yahoo.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

meson: require `nm` again on Unix systems

This was made optional in ff9bf223c24143260a97 ("meson: make nm binary optional")
for Windows, but proper windows has been added and `nm` is now only used
on Unix systems.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>

meson: add windows support to symbols checks

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>

meson: move the generic symbols check arguments to a common variable

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>

meson: add variable to control the symbols checks

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviwed-by: Dylan Baker <dylan@pnwbakers>

mesa: fix call to _mesa_lookup_vao_err

Fixes: 3e842a0b0ea ("mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2055
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meson: Add dep_glvnd to egl deps when building with glvnd

Otherwise if glvnd is not installed systemwide, but only in a prefix,
it's headers wont be found. This happens because if it's headers are in
/usr/include/ then another dependence will provide the necessary -I
arguments and compilation will work.

Fixes: 035ec7a2bb2d5e413ac945b8f012185a0e187d5e
       ("meson: Add support for EGL glvnd")
Acked-by: Eric Engestrom <eric@engestrom.ch>

util/u_endian: Add error checks

As suggested by Eric Engestrom and Michel Dänzer.

util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIAN

As requested by Tim.

This was generated with:
grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g

v2: - add this patch

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

gallium/osmesa: Use PIPE_ARCH_*_ENDIAN instead of little_endian function

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

mesa/main: delete now unused _mesa_little_endian

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

mesa/swrast: replace instances of _mesa_little_endian with preprocessor

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

mesa/main: replace uses of _mesa_little_endian with preprocessor

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util/u_endian: set PIPE_ARCH_*_ENDIAN to 1

This will allow it to be used as a drop in replacement for
_mesa_little_endian in a number of cases.

v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN,
      define the one that reflects the host system to 1 and the other to 0
    - replace all uses of #ifdef, #ifndef, and #if defined() with #if
      and #if ! with PIPE_ARCH_*_ENDIAN

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util/u_endian: Use _WIN32 instead of _MSC_VER

_WIN32 is defined by basically all windows compilers (MSVC, ICL, MinGW),
wereas _MSC_VER is not defined by MinGW. Without this change MinGW falls
through and doesn't define PIPE_ARCH at all, and is caught by some extra
code in gallium.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

dri/osmesa: use preprocessor for selecting endian code paths

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

r100: Use preprocessor to select big vs little endian paths

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

r200: use preprocessor for big vs little endian checks

Instead of using a function at runtime we can just build the right code
for the right platform.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

svga: check return value of define_query_vgpu{9,10}

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

gitlab-ci: Run only LAVA jobs in special-named branches

Run only jobs needed for testing on LAVA devices if a branch starts with
lava-ci-.

This allows developers to have faster test cycles as these pipelines
take only a bit above 8 minutes. Also has the advantage of conserving
resources.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

mesa: add EXT_dsa glGetVertexArray* 4 functions

The implementation doesn't share much with get.c because:
  * the refactoring needed for get.c to not depend on ctx->Array.VAO would
    be quite large
  * glGetVertexArray* would still need to filter pname to only accept the one
    specified by the spec
  * these functions are getter, the implementation is trivial (the complexity
    is in the correct filtering of pname input)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: extract helper function from _mesa_GetPointerv

Will be used by EXT_dsa gllGetVertexArrayPointervEXT implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add EXT_dsa EnableVertexArrayAttribEXT / DisableVertexArrayAttribEXT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add EXT_dsa glEnableVertexArrayEXT / glDisableVertexArrayEXT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add gl_vertex_array_object parameter to client state helpers

This will allow to use the same helper for the EXT_direct_state_access
implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add EXT_dsa glVertexArray* functions implementation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add vao/vbo lookup helper for EXT_dsa

Add a single helper dealing with the lookup of both the vao
and the vbo to avoid duplicating this code in all the
glVertexArray* functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: rework _mesa_lookup_vao_err to allow usage from EXT_dsa

ARB_dsa and EXT_dsa slightly differs when an uninitialized VAO
is requested.
In this case ARB_dsa fails while EXT_dsa requires to initialize
the object.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add EXT_dsa glVertexArray* functions declarations

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: pass vao as a function paramter

This change will allow reusing the same function for the
EXT_direct_state_access implementation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gitlab-ci: Set arm job CCACHE_DIR properly

$PWD doesn't work for variables:, it ended up as "/ccache", always
starting with an empty cache.

v2:
* Use relative path and realpath
v3:
* Use $CI_PROJECT_DIR (Eric Anholt)
* Clear ccache stats in before_script if the cache is in $CI_PROJECT_DIR

Fixes: c9df92bf795a "ci: Switch over to an autoscaling GKE cluster for
                     builds."
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

nir: Handle image arrays when setting variable data

Fixes a ton of regressions in image load store tests.

Fixes: 4319cc8c0f5 ("nir: pack nir_variable::data::xfb_*")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

intel/compiler: remove the operand restriction for src1 on GLK

Commit 5847de6e9afe implemented a restriction that applies to ICL, but
wrongly marked it as also applying to GLK. Reviewers or MR !1125
pointed this, and the commit history shows removal of GLK to parts of
the patch, but it turns there was still a left-over GLK check in the
code.

This code was breaking some of the i8vec2 tests on GLK, for example:
  dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

Removing the GLK check solves the issue for GLK. I don't see a reason
on why implementing this restriction would actually break GLK, so
there's still more to investigate here since this bug may be affecting
ICL+, but let's apply the real GLK fix while we analyze and discuss
the other possible issues.

Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1
on ICL")
BSpec: 3017
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

nir: pack nir_variable::data::xfb_*

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: pack nir_variable::data::stream

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/algebraic: Mark other comparison exact when removing a == a

This prevents some additional optimizations that would change the
original result.  This includes things like (b < a && b < c) => b <
min(a, c) and !(a < b) => b >= a.  Both of these optimizations were
specifically observed in the piglit tests added in piglit!160.

This was discovered while investigating
https://gitlab.freedesktop.org/mesa/mesa/issues/1958.  However, the
problem in that issue was Chrome or Angle is replacing calls to isnan()
with some stuff that we (correctly) optimize to false.  If they had left
the calls to isnan() alone, everything would have just worked.

No shader-db changes on any Intel platform.

I also tried marking the comparison generated by the isnan() function
precise.  The precise marker "infects" every computation involved in
calculating the parameter to the isnan() function, and this severely
hurt all of the (few) shaders in shader-db that use isnan().

I also considered adding a new ir_unop_isnan opcode that would implement
the functionality.  During GLSL IR-to-NIR translation, the resulting
comparison operation would be marked exact (and the samething would need
to happen in SPIR-V translation).

This approach taken by this patch seemed easier, but we may want to do
the ir_unop_isnan thing anyway.

Fixes: d55835b8bdf ("nir/algebraic: Add optimizations for "a == a && a CMP b"")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/algebraic: Add the ability to mark a replacement as exact

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

compiler: make variable::data::binding unsigned

Nothing seems to set a negative value.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

st/mesa: call nir_lower_flrp only once per shader

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

st/mesa: call nir_opt_access only once

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

ac: add missing Arcturus to the info of pc lines

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>

panfrost/ci: Update T760 expectations

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Extend default_phys_reg to !32-bit

We can pass through a size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Extend swizzle packing for vec4/16-bit

We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Extend offset_swizzle to non-32-bit

We take a size parameter; use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: offset_swizzle doesn't need dstsize

This argument should be omitted.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Add bizarre corner case

Someone really needs to look into this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Compute bundle interference

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Fix quadword_count handling

Spilling can mess with this considerably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Validate tags when branching

Midgard prefetches instructions based on tag (ALU, LD/ST, texture *
size). To do so, the shader descriptor specifies the tag of the first
instruction, all instructions specify the tag of the next linear
instruction is, and all branches explicitly specify the tag of the
branch target.

If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously
refers to this problem, but it's still annoying to try to work out all
the branch targets in your head to debug.

Instead, let's track the tags of various blocks over time, so we can
automatically validate tags of branch targets, to make
INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

aco: fix accidential reordering of instructions when scheduling

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: only use single-dword loads/stores for spilling

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix immediate offset for spills if scratch is used

Fixes: 86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

anv: Properly handle host query reset of performance queries

The host query reset entry point didn't use the availability offset
for performance queries.

To fix this, reorder the availability of performance queries to match
other queries.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

state_tracker: Handle texture view min level in st_generate_mipmap()

Signed-off-by: Paul Gofman <gofmanp@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

iris: try to set the specified tiling when importing a dmabuf

When importing a dmabuf with a specified tiling, the dmabuf user
should always try to set the tiling mode because: 1) the exporter
can set tiling AFTER exporting/importing. 2) a dmabuf could be
exported from a kernel driver other than i915, in this case the
dmabuf user and exporter need to set tiling separately.

This patch fixes a problem when running vkmark under weston with
iris on ICL, it crashed to console with the following assert. i965
doesn't have this problem as it always tries to set the specified
tiling mode.

weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

iris: Fix "Force Zero RTA Index Enable" setting again

In 2ca0d913ea8, we began updating cso_fb->layers to the actual layer
count, rather than 0.  This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering.  Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.

Fixes: 2ca0d913ea8 ("iris: Fix framebuffer layer count")

nir: correct use of identity check in python

Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.

Fixes: 96c4b135e34d0804e41bfbc28fc1b5050c49d71e
       ("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88@gmail.com>

panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASK

MALI_DEPTH_TEST should only be set when depth->writemask is true,
not when the depth test is enabled. Let's rename the flag and patch
panfrost_bind_depth_stencil_state() to do the right thing.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

vulkan: bump headers/registry to 1.1.127

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

radv: fix compute pipeline keys when optimizations are disabled

If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.

Fixes: ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>