i965: Enable shared local memory for CS shared variables

v3:
 * Check shared variable size at link time

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Handle nir shared variable store intrinsic

v4:
 * Apply similar optimization for shared variable stores as
   0cb7d7b4b7c32246d4c4225a1d17d7ff79a7526d. This was causing a
   OpenGLES 3.1 CTS failure, but
   867c436ca841b4196b4dde4786f5086c76b20dd7 fixes that.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Handle nir shared variable load intrinsic

v3:
 * Remove extra #includes (Iago)
 * Use recently added GEN7_BTI_SLM instead of BRW_SLM_SURFACE_INDEX (curro)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Disable vector splitting on shared variables

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

nir: Translate glsl shared var store intrinsic to nir intrinsic

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

nir: Translate glsl shared var load intrinsic to nir intrinsic

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl: Add lowering pass for shared variable references

In this lowering pass, shared variables are decomposed into intrinsic
calls.

v2:
 * Send mem_ctx as a parameter (Iago)

v3:
 * Shared variables don't have an associated interface block (Iago)
 * Always use 430 packing (Iago)
 * Comment / whitespace cleanup (Iago)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl: Don't assert on shared variable matrices with 'inherited' layout

We use column-major for shared variable matrices.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl: Don't lower_variable_index_to_cond_assign for shared variables

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl: Remove mem_ctx as member variable in lower_ubo_reference_visitor

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl ubo/ssbo: Move common code into lower_buffer_access::setup_buffer_access

This code will also be usable by the pass to lower shared variables.

Note, that *const_offset is adjusted by setup_buffer_access so it must
be initialized before calling setup_buffer_access.

v2:
 * Add comment for lower_buffer_access::setup_buffer_access

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl ubo/ssbo: Move is_dereferenced_thing_row_major into lower_buffer_access

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl ubo/ssbo: Add lower_buffer_access class

This class has code that will be shared by lower_ubo_reference and
lower_shared_reference. (lower_shared_reference will be used to
support compute shader shared variables.)

v2:
 * Add lower_buffer_access.h to makefile (Emil)
 * Remove static is_dereferenced_thing_row_major from
   lower_buffer_access.cpp. This will become a lower_buffer_access
   method in the next commit.
 * Pass mem_ctx as parameter rather than using a member variable (Iago)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl ubo/ssbo: Split buffer access to insert_buffer_access

This allows the code in emit_access to be generic enough to also be
for lowering shared variables.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl ubo/ssbo: Use enum to track current buffer access type

v2:
 * Rename ssbo_get_array_length to ssbo_unsized_array_length_access (Iago)
 * Use always use this-> when referencing buffer_access_type (Iago)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

glsl: do not loose always_active_io when packing varyings

Otherwise packed and inactive varyings get optimized away. This needs
to be prevented when using separate shader objects where interface
needs to be preserved.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa: invalidate pipeline status after glUseProgramStages

This will cause validation to run during next draw, this is done
because possible changes in used stages and programs can cause
invalid pipeline state.

This fixes a subtest in following CTS test:
ES31-CTS.sepshaderobjs.StateInteraction

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

mesa/varray: set double arrays to non-normalised.

Doesn't have any effect in practice I don't think, but
CTS reads back using GetVertexAttrib.

This fixes: GL41-CTS.vertex_attrib_64bit.get_vertex_attrib

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

clover: Fix build against LLVM 3.8 SVN >= r255078

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

mesa: fix ID usage for buffer warnings

We need a different ID pointer for each call site.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs: remove stray <ul> tag from 11.0.5.html file to fix indentation

freedreno: little clean up in fd_create_surface

in order to avoid returing invalid adress if CALLOC_STRUCT return NULL.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: change to goto fail

in fd_resource_transfer_map, like the others error cases

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: fix bind_sampler_states when hwcso is NULL

src/gallium/tests/trivial/compute.c expects samplers to be cleaned
when the samplers list is NULL.
Like in radeon, the function behave like when the number of samplers
parameter is set to 0.

[small s/hwsco/hwcso/ typo fix]
Signed-off-by: Rob Clark <robclark@freedesktop.org>

gallium/util: Make u_prims_for_vertices() safe

Let us avoid trapping in hardware from a SIGFPE and instead
assert on a zero divisor.

Hint: This can occur if a PIPE_PRIM_? is not handled in
      u_prim_vertex_count() that results in ' info ' not
      being initialized in the expected manner.

Further, we also fix a possibly NULL pointer dereference
from ' info ' being NULL from a u_prim_vertex_count() call.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

docs: add news item for mesa-demos 8.3.0 release

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>

nv50,nvc0: fix use-after-free when vertex buffers are unbound

Always reset the vertex bufctx to make sure there's no pointer to
an already freed pipe_resource left after unbinding buffers.
Fixes use after free crash in nvc0_bufctx_fence().

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
[imirkin: simplify nvc0 fix, apply to nv50]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

mesa: Fix a typo in a comment

s/suports/supports/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glx: Fix a typo in a comment

s/suports/supports/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/osmesa: Fix a typo in a comment

s/suport/support/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

meta: Fix a typo in a print message

s/Unkown/Unknown/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Fix typos in print messages

s/inconsistant/inconsistent/
s/occurences/occurrences/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: Fix a typo in a comment

s/suports/supports/

Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

svga: initialize pipe_driver_query_info entries with a macro

To be safe, set all the fields in case the enums ordering/values
ever change.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: detect inefficient buffer use and report through debug output

When a buffer is created with GL_STATIC_DRAW, its contents should not
be changed frequently.  But that's exactly what one application I'm
debugging does.  This patch adds code to try to detect inefficient
buffer use in a couple places.  The GL_ARB_debug_output mechanism is
used to report the issue.

NVIDIA's driver detects these sort of things too.

Other types of inefficient buffer use could also be detected in the
future.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

docs: add news item and link release notes for 11.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 11.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit f9715bc449d6b2cc5693e44bb82a9d5305a32ab5)

docs: add release notes for 11.0.7

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit bec983b738a7f149478ee692ba0e1d26fcc9fd8e)

i965: Resolve color and flush for all active shader images in intel_update_state().

Fixes arb_shader_image_load_store/execution/load-from-cleared-image.shader_test.

Couldn't reproduce any significant FPS regression in CPU-bound
benchmarks from the Finnish benchmarking system on neither VLV nor BSW
after 30 runs with 95% confidence level.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92849
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Document inconsistent units the URB size is represented in.

Every other gen the representation of the URB size was changed and
previous ones weren't updated.  I'd be willing to write a series
normalizing this to be KB on all generations if anybody else cares.

i965: Hook up L3 partitioning state atom.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Work around L3 state leaks during context switches.

This is going to require some rather intrusive kernel changes to fix
properly, in the meantime (and forever on at least pre-v4.1 kernels)
we'll have to restore the hardware defaults at the end of every batch
in which the L3 configuration was changed to avoid interfering with
the DDX and GL clients that use an older non-L3-aware version of Mesa.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
v2: Optimize look-up of the default configuration by assuming it's the
    first entry of the L3 config array in order to avoid an FPS
    regression in GpuTest Triangle and SynMark OglBatch2-7 on most
    affected platforms.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Add debug flag to print out the new L3 state during transitions.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Implement L3 state atom.

The L3 state atom calculates the target L3 partition weights when the
program bound to some shader stage is modified, and in case they are
far enough from the current partitioning it makes sure that the L3
state is re-emitted.

v2: Fix for inconsistent units the context URB size is expressed in.
    Clamp URB size to 1008 KB on SKL due to FF hardware limitation.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Calculate appropriate L3 partition weights for the current pipeline state.

This calculates a rather conservative partitioning of the L3 cache
based on the shaders currently bound to the pipeline and whether they
use SLM, atomics, images or scratch space.  The result is intended to
be fine-tuned later on based on other pipeline state.

Note that the L3 partitioning calculated for VLV in the non-SLM non-DC
case differs from the hardware defaults in that it doesn't include a
DC partition and has twice as much RO cache space -- This is an
intentional functional change that improves performance in several
bandwidth-bound benchmarks on VLV (5% significance): SynMark
OglTexFilterAniso by 14.18%, SynMark OglTexFilterTri by 7.15%, Unigine
Heaven by 4.91%, SynMark OglShMapPcf by 2.15%, GpuTest Fur by 1.83%,
SynMark OglDrvRes by 1.80%, SynMark OglVsTangent by 1.71%, and a few
other benchmarks from the Finnish system by less than 1%.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Implement selection of the closest L3 configuration based on a vector of weights.

The input of the L3 set-up code is a vector giving the approximate
desired relative size of each partition.  This implements logic to
compare the input vector against the table of validated configurations
for the device and pick the closest compatible one.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Define and use REG_MASK macro to make masked MMIO writes slightly more readable.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/hsw: Enable L3 atomics.

Improves performance of the arb_shader_image_load_store-atomicity
piglit test by over 25x (which isn't a real benchmark it's just heavy
on atomics -- the improvement in a microbenchmark I wrote a while ago
seemed to be even greater).  The drawback is one needs to be
extra-careful not to hang the GPU (in fact the whole system).  A DC
partition must have been allocated on L3, the "convert L3 cycle for DC
to UC" bit may not be set, the MOCS L3 cacheability bit must be set
for all surfaces accessed using DC atomics, and the SCRATCH1 and
ROW_CHICKEN3 bits must be kept in sync.

A fairly recent kernel is required for the command parser to allow
writes to these registers.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Implement programming of the L3 configuration.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Import tables enumerating the set of validated L3 configurations.

It should be possible to use additional L3 configurations other than
the ones listed in the tables of validated allocations ("BSpec »
3D-Media-GPGPU Engine » L3 Cache and URB [IVB+] » L3 Cache and URB [*]
» L3 Allocation and Programming"), but it seems sensible for now to
hard-code the tables in order to stick to the hardware docs.  Instead
of setting up the arbitrary L3 partitioning given as input, the
closest validated L3 configuration will be looked up in these tables
and used to program the hardware.

The included tables should work for Gen7-9.  Note that the quantities
are specified in ways rather than in KB, this is because the L3
control registers expect the value in ways, and because by doing that
we can re-use a single table for all GT variants of the same
generation (and in the case of IVB/HSW and CHV/SKL across different
generations) which generally have different L3 way sizes but allow the
same combinations of way allocations.

v2: Use slice count from the devinfo structure instead of the gt
    number to implement get_l3_way_size().

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Add slice count to the brw_device_info structure.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.

According to the hardware docs a DC flush is sufficient to make
CS_STALL happy, there's no need to add STALL_AT_SCOREBOARD whenever
it's present.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Define state flag to signal that the URB size has been altered.

This will make sure that we recalculate the URB layout anytime the URB
size is modified by the L3 partitioning code.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Keep track of whether LRI is allowed in the context struct.

This stores the result of can_do_pipelined_register_writes() in the
context struct so we can find out later whether LRI can be used to
program the L3 configuration.

v2:
 * Split change of gen check in can_do_pipelined_register_writes (jljusten)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Adjust gen check in can_do_pipelined_register_writes

Allow for pipelined register writes for gen < 7.

v2:
 * Split from another patch and adjust comment (jljusten)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Define symbolic constants for some useful L3 cache control registers.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

radeonsi: handle loading doubles as geometry shader inputs.

This adds the double code to the geometry shader input handling.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: handle doubles in lds load path.

This handles loading doubles from LDS properly.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "11.0 11.1" <mesa-stable@lists.fedoraproject.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: handle geometry dynamic input array index

This fixes:
glsl-1.50/execution/geometry/dynamic_input_array_index.shader_test
my profanity.

We need to load the AR register with the value from the index reg

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g: fix geom shader input indirect indexing.

This fixes:
gs-input-array-vec4-index-rd

The others run out of gprs unfortunately.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g: fix outputing to non-0 buffers for stream 0.

This fixes:
arb_transform_feedback3-ext_interleaved_two_bufs_gs
arb_transform_feedback3-ext_interleaved_two_bufs_gs_max
transform-feedback-builtins

If we are only emitting one ring, then emit all output
buffers on it.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600: Add ARB_copy_image support

[airlied: update relnotes]

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g: allow copying between compatible un/compressed formats

See: `commit e82c527f1fc2f8ddc64954ecd06b0de3cea92e93`

which is where a block in src maps to a pixel in dst and vice versa.
    e.g. DXT1 <-> R32G32_UINT
         DXT5 <-> R32G32B32A32_UINT

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nv50/ir: fix cutoff for using r63 vs r127 when replacing zero

The only effect here is a space savings - 822 programs in shader-db
affected with the following overall change:

total bytes used in shared programs   : 44154976 -> 44139880 (-0.03%)

Fixes: 641eda0c (nv50/ir: r63 is only 0 if we are using less than 63 registers)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>

nv50/ir: prefer to color mad def and src2 with the same color

This allows us to use the short encoding, and potentially fold
immediates in later on.

total instructions in shared programs : 6379731 -> 6367861 (-0.19%)
total gprs used in shared programs    : 728502 -> 728683 (0.02%)
total local used in shared programs   : 9904 -> 9904 (0.00%)
total bytes used in shared programs   : 44661008 -> 44154976 (-1.13%)

                local        gpr       inst      bytes
    helped           0          51        7267       20306
      hurt           0         232         125         274

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: reduce degree limit on ops that can't encode large reg dests

Operations that take immediates can only encode registers up to 64. This
fixes a shader in a "Powered by Unity" intro.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: only unspill once ahead of a group of instructions

We already semi-did this but the list of uses as unsorted, so it was
unreliable. Sort the uses by bb and serial, and don't unspill for each
instruction in a sequence. (And also don't unspill multiple times for a
single instruction that uses the value in question multiple times.)

This causes a minor reduction in generated instructions for shader-db
(as few programs spill) but more importantly it brings determinism to
each run's output.

On SM10:

total instructions in shared programs : 6387945 -> 6379359 (-0.13%)
total gprs used in shared programs    : 728544 -> 728544 (0.00%)
total local used in shared programs   : 9904 -> 9904 (0.00%)

                local        gpr       inst      bytes
    helped           0           0         322         322
      hurt           0           0           0           0

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: check if the target supports the new offset before inlining

Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93300
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

llvmpipe: fix fp64 inputs to geom shader.

This fixes the fetching of fp64 inputs to the geometry shader,

this fixes the recently posted piglit's
arb_gpu_shader_fp64/execution/gs-fs-vs-double-array.shader_test
arb_vertex_attrib_64bit/execution/gs-fs-vs-attrib-double-array.shader_test

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir: Optimize useless comparisons against true/false.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
v2: Move new rule to Boolean simplification section
    Add a a@bool != true simplification

Suggested-by: Neil Roberts <neil@linux.intel.com>

glsl: Switch opcode and avail parameters to binop().

To make it match unop().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl_to_tgsi: Skip useless comparison instructions.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Relax qualifier ordering restriction in ES 3.1.

... and allow the "binding" qualifier in ES 3.1 as well.

GLSL ES 3.1 incorporates only a few features from the extension
ARB_shading_language_420pack: the relaxed qualifier ordering
requirements and the binding qualifier.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Use has_420pack().

These features would not have been enabled with #version 420 otherwise.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Allow binding of image variables with 420pack.

This interaction was missed in the addition of ARB_image_load_store.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93266
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

appveyor: Cache winflexbison archive.

Unforunately the Appveyor -> SourceForge connection seems a bit
unreliable, causing frequent build failures while downloading
winflexbison (approx once every 2 days).

Fetching winflexbison archive into Appveyor's cache should eliminate
these.

Fetching Python modules from PyPI doesn't seem to be a problem, so they
are left alone for now, though they could eventually get the same
treatment.

vc4: Enable MSAA.

We still have several failures in the newly enabled tests in simulation:
sRGB downsampling is done as if it was just linear, stencil blits are not
supported on MSAA either, and derivatives are still not supported
(breaking some MSAA simulation shaders).  So, other than sRGB downsampling
quality, things seem to be in good shape.

vc4: Add support for mapping of MSAA resources.

The pipe_transfer_map API requires that we do an implicit
downsample/upsample and return a mapping of that.

vc4: Add support for texel fetches from MSAA resources.

This is the core of ARB_texture_multisample.  Most of the piglit tests for
GL_ARB_texture_multisample require GL 3.0, but exposing support for this
lets us use the gallium blitter for multisample resolves.  We can
sometimes multisample resolve using just the RCL, but that requires that
the blit is 1:1, unflipped, and aligned to tile boundaries.

vc4: Add support for multisample framebuffer operations.

This includes GL_SAMPLE_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, and
GL_SAMPLE_ALPHA_TO_COVAGE.

I haven't implemented a dithering function yet, and gallium doesn't give
me a good chance to do so for GL_SAMPLE_COVERAGE.

vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.

I only stumbled on this while experimenting due to reading about HW-2905.
I don't know if the EZ disable in the Z-clear is actually necessary, but
go with it for now.

vc4: Add support for drawing in MSAA.

vc4: Add kernel RCL support for MSAA rendering.

vc4: Rename color_ms_write to color_write.

I was thinking this was the only MSAA resolve thing, so it should be noted
separately, but actually load/store general also do MSAA resolve.

vc4: Allow RCL blits to the edge of the surface.

The recent unaligned fix successfully prevented RCL blits that weren't
aligned inside of the surface, but we also want to be able to do RCL blits
for the whole surface when the width or height of the surface aren't
aligned (we don't care what renders inside of the padding).

vc4: Add disabled debug printf for describing blits.

I keep typing variants of this while debugging RCL blits for MSAA.

vc4: Fix check for tile RCL blits with mismatched y.

This was a typo in 3a508a0d94d020d9cd95f8882e9393d83ffac377 that didn't
show up in testcases at that moment.

vc4: Fix compiler warning from size_t change.

I missed this when bringing over the kernel changes.

scons: support for LLVM 3.7.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

docs/GL3.txt: consolidate r600 GL4.1.

Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Make uniform offsets be in terms of bytes

This commit pushes makes uniform offsets be terms of bytes starting with
nir_lower_io.  They get converted to be in terms of vec4s or floats when we
cram them in the UNIFORM register file but reladdr remains in terms of
bytes all the way down to the point where we lower it to a pull constant
load.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/nir_uniforms: Replace comps_per_unit with an is_scalar boolean

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/nir: Remove unused indirect handling

The one and only place where the FS backend allows reladdr is on uniforms.
For locals, inputs, and outputs, we lower it away before the backend ever
sees it.  This commit gets rid of the dead indirect handling code.

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/state: Get rid of dword_pitch arguments to buffer functions

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Use a stride of 1 and byte offsets for UBOs

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use a stride of 1 and byte offsets for UBOs

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge

Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on
vec4-aligned byte offsets on Iron Lake and below and worked in terms of
vec4 offsets on Sandy Bridge.  On Ivy Bridge, we add a new *LOAD_GEN7
variant which works in terms of vec4s.  We're about to change the GEN7
version to work in terms of bytes, so this is a nice unification.

Cc: "11.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix texture views of 2d array surfaces

It is legal to have a texture view of a single layer from a 2D array texture;
you can sample from it, or render to it. Intel hardware needs to be made aware
when it is using a 2d array surface in the surface state. The texture view is
just a 2d surface with the backing miptree actually being a 2d array surface.
This caused the previous code would not set the right bit in the surface state
since it wasn't considered an array texture.

I spotted this early on in debug but brushed it off because it is clearly not
needed on other platforms (since they all pass). I have no idea how this works
properly on other platforms (I think gen7 introduced the bit in the state, but I
am too lazy to check). As such, I have opted not to modify gen7, though I
believe the current code is wrong there as well.

Thanks to Chris for helping me debug this.

v2: Just use the underlying mt's target type to make the array determination.
This replaces a bug in the first patch which was incorrectly relying only
on non-zero depth (not sure how that had no failures). (Ilia)

Cc: Chris Forbes <chrisf@ijw.co.nz>
Reported-by: Mark Janes <mark.a.janes@intel.com> (Jenkins)
References: https://www.opengl.org/registry/specs/ARB/texture_view.txt
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

radeonsi: last_gfx_fence is a winsys fence

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integers

For some reason this has been disabled for integers ever since codegen
was merged, despite there being emission code for IMAD. Seems to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>