Luke Kenneth Casson Leighton [Wed, 21 Aug 2019 05:08:15 +0000 (06:08 +0100)]
use reg_partition_points to create new Parts at final output
Luke Kenneth Casson Leighton [Wed, 21 Aug 2019 04:56:49 +0000 (05:56 +0100)]
add expanded parts to Part, use new Parts module
Luke Kenneth Casson Leighton [Wed, 21 Aug 2019 04:47:06 +0000 (05:47 +0100)]
add mul factor to PartitionPoints.like
Luke Kenneth Casson Leighton [Wed, 21 Aug 2019 04:45:43 +0000 (05:45 +0100)]
add new Parts class
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:53:58 +0000 (14:53 +0100)]
move expanded_part_pts further up
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:51:23 +0000 (14:51 +0100)]
move part_byte to PartitionPoints
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:15:43 +0000 (14:15 +0100)]
rename delayed_part_ops to part_ops
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:14:52 +0000 (14:14 +0100)]
remove delayed part ops, now inside AddReduceSingle
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:06:50 +0000 (14:06 +0100)]
add missing arg part_ops to unit test
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 13:05:19 +0000 (14:05 +0100)]
do not need delayed_part_ops
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 10:44:41 +0000 (11:44 +0100)]
pass in part_ops to AddReduce, so that it is syncd alongside the other data
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 09:57:54 +0000 (10:57 +0100)]
whitespace
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 09:34:26 +0000 (10:34 +0100)]
removing recursion from AddReduce
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 07:34:43 +0000 (08:34 +0100)]
update explanatory comments
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 06:53:46 +0000 (07:53 +0100)]
MaskedFullAdder performs ANDing in a group by pre-shifting the carry bits
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 06:13:47 +0000 (07:13 +0100)]
split "actionable" part of AddReduce out from "recursive" part
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:56:19 +0000 (06:56 +0100)]
update comments
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:53:25 +0000 (06:53 +0100)]
add to docstrings in PartitionedAdder
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:52:18 +0000 (06:52 +0100)]
add to docstrings in PartitionedAdder
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:43:07 +0000 (06:43 +0100)]
create a new "MaskedFullAdder" class, which performs the partition-carry mask
the FullAdder is always masked, so a derivative class is created.
cleans up the graphviz output a lot
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:31:27 +0000 (06:31 +0100)]
add docstrings / comments to PartitionedAdder
Luke Kenneth Casson Leighton [Tue, 20 Aug 2019 05:22:51 +0000 (06:22 +0100)]
spelling mistake $i instead of %i
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 14:29:30 +0000 (15:29 +0100)]
rename temporary value
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 14:28:21 +0000 (15:28 +0100)]
temporary ~pbs
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 11:25:38 +0000 (12:25 +0100)]
name LSBNotTerm submodules after bitwidth
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 11:22:09 +0000 (12:22 +0100)]
use new split-out LSBNotTerm module
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 11:00:41 +0000 (12:00 +0100)]
split out LSB and neg term to separate module
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 10:39:56 +0000 (11:39 +0100)]
docstrings, fix syntax
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 06:55:43 +0000 (07:55 +0100)]
explain Part module
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 06:34:36 +0000 (07:34 +0100)]
add module docstrings to (new) multiply classes
Luke Kenneth Casson Leighton [Mon, 19 Aug 2019 05:19:41 +0000 (06:19 +0100)]
rename fo submodule to "finalout"
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 16:25:36 +0000 (17:25 +0100)]
nope - yosys graph not efficient enough
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 16:12:04 +0000 (17:12 +0100)]
use switch instead of mux, more obvious what is happening
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 05:29:21 +0000 (06:29 +0100)]
add comment about simulation bugs
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 05:27:10 +0000 (06:27 +0100)]
Revert "make variables local"
This reverts commit
e8e8c93b4f3b07fce27558460021fa62b076d9ad.
horrible nmigen simulation bug
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 05:25:32 +0000 (06:25 +0100)]
add TODO code, needs sorting
Luke Kenneth Casson Leighton [Sun, 18 Aug 2019 05:02:05 +0000 (06:02 +0100)]
merge Term into ProductTerm
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 18:45:17 +0000 (19:45 +0100)]
make variables local
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 17:06:29 +0000 (18:06 +0100)]
argh horrible nmigen bug on use of sync involving modules
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 16:54:04 +0000 (17:54 +0100)]
weird bug - some rename experiments
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 16:26:01 +0000 (17:26 +0100)]
FinalOutput module
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 14:58:47 +0000 (15:58 +0100)]
rename variables
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 14:54:04 +0000 (15:54 +0100)]
put signs through Signs module
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 14:30:38 +0000 (15:30 +0100)]
move local variables
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 14:23:13 +0000 (15:23 +0100)]
remove redundant code
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 14:19:04 +0000 (15:19 +0100)]
or data together through a module (reduce top-level complexity)
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 13:57:02 +0000 (14:57 +0100)]
create array of ProductTerms - reduces graphviz MASSIVELY
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 13:29:22 +0000 (14:29 +0100)]
move intermediate output to new module
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 12:59:39 +0000 (13:59 +0100)]
delayed_part_ops is a local
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 12:56:19 +0000 (13:56 +0100)]
add name to Term output
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 12:51:10 +0000 (13:51 +0100)]
move bit selection into ProductTerms: simplifies graph
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 12:33:22 +0000 (13:33 +0100)]
split out "Parts" to separate module
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 11:17:33 +0000 (12:17 +0100)]
move remaining 4 terms, use Term class
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 11:05:04 +0000 (12:05 +0100)]
derive new class Term and ProductTerm
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:48:58 +0000 (11:48 +0100)]
use Cat (again) on intermediate values
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:32:15 +0000 (11:32 +0100)]
simplify sign/term bits using Cat
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 10:13:59 +0000 (11:13 +0100)]
move product terms to separate module (Term)
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 09:57:23 +0000 (10:57 +0100)]
add new Terms class, get part_pts into intermediary
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 09:11:34 +0000 (10:11 +0100)]
part replaced by bit_select
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:41:41 +0000 (09:41 +0100)]
whoops, a-enabled and b-enabled swapped
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:24:20 +0000 (09:24 +0100)]
stash intermediaries for output into temp signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:13:28 +0000 (09:13 +0100)]
assignment in Cat wrong way round
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:07:36 +0000 (09:07 +0100)]
use reset_less
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:02:32 +0000 (09:02 +0100)]
whoops use already-used list
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 08:00:18 +0000 (09:00 +0100)]
boolean logic inversion, x = ~a & ~b & ~c ==> ~(a | b | c) then use list
of terms, use bool(), and graph size is reduced
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:49:23 +0000 (08:49 +0100)]
concatenate parts using list then Cat() - again, simplifies output
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:40:34 +0000 (08:40 +0100)]
a_enabled and b_enabled into signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:31:24 +0000 (08:31 +0100)]
add intermediate values as signals
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:17:24 +0000 (08:17 +0100)]
move variable to pyi file
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:14:10 +0000 (08:14 +0100)]
store mask in intermediary
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 07:06:20 +0000 (08:06 +0100)]
use Cat instead of for-loops: cleans up the yosys graphviz massively
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 06:56:20 +0000 (07:56 +0100)]
move typing to multiplier.pyi
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 06:45:18 +0000 (07:45 +0100)]
add partitioned multiplier/adder
Luke Kenneth Casson Leighton [Sat, 17 Aug 2019 04:24:38 +0000 (05:24 +0100)]
rename fp div classes and submodule
Luke Kenneth Casson Leighton [Fri, 16 Aug 2019 10:24:40 +0000 (11:24 +0100)]
test flipping of latchable pipeline stage between sync and comb modes
Luke Kenneth Casson Leighton [Fri, 16 Aug 2019 03:38:00 +0000 (04:38 +0100)]
update comments
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 17:23:12 +0000 (18:23 +0100)]
set up data in temporaries correctly
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 16:57:05 +0000 (17:57 +0100)]
update MaskCancellable docstrings
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 16:51:20 +0000 (17:51 +0100)]
add dynamic comb/sync mode to MaskCancellable
Luke Kenneth Casson Leighton [Thu, 15 Aug 2019 14:26:32 +0000 (15:26 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 14 Aug 2019 13:39:10 +0000 (14:39 +0100)]
debugging feedback pipe
Luke Kenneth Casson Leighton [Mon, 12 Aug 2019 02:25:14 +0000 (03:25 +0100)]
fix syntax errors in fmac conversion
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 12:35:24 +0000 (13:35 +0100)]
increase number of fpmul operands to 3
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 12:34:54 +0000 (13:34 +0100)]
restore old Multi-in/out behaviour
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 07:42:47 +0000 (08:42 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sun, 11 Aug 2019 06:01:00 +0000 (07:01 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 11:59:48 +0000 (12:59 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 10:58:19 +0000 (11:58 +0100)]
{x}{y} in verilog means x occurrences of y
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 10:18:09 +0000 (11:18 +0100)]
{x}{y} in verilog means x occurrences of y
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 07:53:28 +0000 (08:53 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Sat, 10 Aug 2019 06:29:09 +0000 (07:29 +0100)]
start converting hardfloat-verilog fmac to nmigen
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 11:26:13 +0000 (12:26 +0100)]
route-back experimentation
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 02:20:56 +0000 (03:20 +0100)]
add experimental feedback pipe test
Luke Kenneth Casson Leighton [Wed, 7 Aug 2019 00:15:16 +0000 (01:15 +0100)]
respect Ready/Valid signalling (stall capability) in MaskCancellable
this will be needed for pipeline bypassing
Luke Kenneth Casson Leighton [Tue, 6 Aug 2019 11:19:33 +0000 (12:19 +0100)]
add mask cancellation to FPDIV and to fpmux unit test
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:37:13 +0000 (08:37 +0100)]
multiply mask width for concurrent pipeline
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:36:41 +0000 (08:36 +0100)]
hack to set predicate mask (if it exists)
Luke Kenneth Casson Leighton [Mon, 5 Aug 2019 07:36:11 +0000 (08:36 +0100)]
whoops inherit from MaskCancellable not SimpleHandshake
Luke Kenneth Casson Leighton [Sun, 4 Aug 2019 11:34:38 +0000 (12:34 +0100)]
added maskwidth and dynamic use of MaskCancellable, no "bugs", still to
confirm if it works
Luke Kenneth Casson Leighton [Sat, 3 Aug 2019 22:39:12 +0000 (23:39 +0100)]
only pass on the uncancelled mask bits