radeonsi: implement pipe_context::set_log_context

We'll add radeonsi-specific code to set_log_context in later patches,
but we may want to log from common code. Hence keep the log pointer
in r600_common_context.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

amd/common: split out ac_parse_ib_chunk from ac_parse_ib

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ddebug: add driver log to record dumps

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add pipe_context::set_log_context

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util/log: add auto logger facility

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util: add chunk logging module

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl/linker: Make several functions not static

copy_constant_to_storage, set_uniform_initializer,
populate_consumer_input_sets, and get_matching_input are all used by
tests in src/compiler/glsl/tests:

glsl/tests/varyings_test.o: In function `link_varyings_single_simple_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:131: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_gl_ClipDistance_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:159: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_gl_CullDistance_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:186: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_single_interface_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:208: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_one_interface_and_one_simple_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:241: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o:src/compiler/glsl/tests/varyings_test.cpp:272: more undefined references to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)' follow
glsl/tests/varyings_test.o: In function `link_varyings_interface_field_doesnt_match_noninterface_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:289: undefined reference to `linker::get_matching_input(void*, ir_variable const*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_interface_field_doesnt_match_noninterface_vice_versa_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:314: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
src/compiler/glsl/tests/varyings_test.cpp:328: undefined reference to `linker::get_matching_input(void*, ir_variable const*, hash_table*, hash_table*, ir_variable**)'

Fixes: ca73c3358c91 ("glsl: Mark functions static")
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/clear: Quantize the depth clear value based on the format

In f9fd976e8adba733b08d we changed the clear value to be stored as an
isl_color_value.  This had the side-effect same clear value check is now
happening directly between the f32[0] field of the isl_color_value and
ctx->Depth.Clear.  This isn't what we want for two reasons.  One is that
the comparison happens in floating point even for Z16 and Z24 formats.
Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float
formats, we were comparing as doubles and not floats.  This means that
the test basically always fails for anything other than 0.0f and 1.0f.
This caused a slight performance regression in Lightsmark 2008 because
it was using a depth clear value of 0.999 which can't be stored in a
32-bit float so we were doing unneeded resolves.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/101678
Cc: "17.2" <mesa-stable@lists.freedesktop.org>

mesa/st: simplify some UBO index logic

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: enable STD430 packing by default on IVB+

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: pass UseSTD430AsDefaultPacking to where it will be used

Here we also make use of the UseSTD430AsDefaultPacking constant
and call the new get_internal_ifc_packing() helper.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add get_internal_ifc_packing() type helper

This is used to avoid code duplication when selecting the
packing type for shared and packed layouts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add UseSTD430AsDefaultPacking constant

This will be used to enable the STD430 layout as the default for
UBOs and SSBOs with layouts of shared/packed rather than STD140.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

clover/device: Calculate CL_DEVICE_MEM_BASE_ADDR_ALIGN in device

The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and
then allocates user pointers aligned to that value for its tests.

The minimum value is defined as:
  the size (in bits) of the largest OpenCL built-in data type supported
  by the device (long16 in FULL profile, long16 or int16 in EMBEDDED
  profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM.

At the moment, all known devices that support user pointers require
CPU page alignment for buffers created from user pointers, so just
query that from sysconf.

v3: Use std::max instead of MAX2 (Francisco)
    Add missing unistd include
v2: Use system page size instead of a new pipe cap

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by (v2): Jan Vesely <jan.vesely@rutgers.edu>

mesa: optimize _mesa_attr_zero_aliases_vertex()

After the context is initialized, the API and context flags won't
change.  So, we can compute whether vertex attribute 0 aliases
vertex position just once.

This should make the glVertexAttrib*() functions a little quicker.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

vbo: use new _is_vertex_position() helper in vbo_attrib_tmp.h

Makes the code a bit more understandable.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

vbo: make vbo_bind_arrays() static

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

svga: replace gotos with conditionals in array drawing code

No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

llvmpipe: add some whitespace between functions in lp_texture.c

Trivial.

mesa: formatting clean-up in syncobj.c

Line wrap to 78 columns, etc.  Trivial.

svga: whitespace clean-up in svga_draw_private.h

Trivial.

docs: remove link to MissingFunctionality wiki page

Outdated, features.txt is used instead.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

docs: remove MSVC testing/building from help wanted

We are using appveyor for Windows continuous integration.

https://ci.appveyor.com/project/mesa3d/mesa

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs: remove automatic testing from help wanted

Intel has a Jenkins setup and has made the various scripts and
documentation open source.

https://github.com/janesma/mesa_jenkins

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

docs: rename TODOs to Legacy Driver TODOs

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

docs: remove link to i915g TODOs

This is an unoffical unmaintained driver, we don't really want
people wasting effort trying to improve it.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

docs: remove link to radeonsi TODO wiki page

This page is deprecated.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/docs: remove old llvmpipe TODO

Features are already covered by features.txt like all the other
drivers.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

mesa: fix ES only draw if we have vertex positions

This code was separated from the validation code so it could
use used with KHR_no_error paths. The return values were inverted
to reflect the name of the helper, but here the condtion was
mistakenly inverted rather than the return value.

Fixes: 4df2931a87fe (mesa/vbo: move some Draw checks out of validation)
Reported-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: Add prototype for udivmod64()

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: Mark functions static

Cuts 3224 bytes of .text

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Mark functions static

Cuts 300 bytes of .text

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/vec4: Use 'class' src_reg, rather than 'struct' src_reg

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/vec4: Return float from spill_cost_for_type()

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv: Move clamp_int64() inside the IVB check

It's only used in the gen7_cmd_buffer_emit_scissor() function.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl: Remove unused private fields

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: Don't compare unsigned for < 0

The INTEL_performance_query spec says

   "Performance counter id 0 is reserved as an invalid counter."

GLuint counterid_to_index(GLuint counterid) just returns counterid - 1,
so with unsigned overflow rules, it will generate 0xFFFFFFFF given an
input of 0. 0xFFFFFFFF will trigger the counterIndex >= queryNumCounters
check, so the code worked as is. It just contained a useless comparison.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

egl: Fix inclusion of egl.h+mesa_glinterop.h

Previously clang would warn about redefinition of typedef EGLDisplay. Avoid
this by adding preprocessor guards to mesa_glinterop.h and including it
after EGL.h is indirectly included.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

radeonsi: don't prefetch VBO descriptors if vertex elements == NULL

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: don't set up and don't call the fetch shader if there are no VS inputs

i965: Optimize reading the destination type

brw_hw_type_to_reg_type() needs to know only whether the file is
BRW_IMMEDIATE_VALUE or not, which is not a valid file for the
destination. gcc and clang will evaluate __builtin_strcmp() at compile
time, so we can use it to pass a constant file for the destination.

   text    data     bss     dec     hex filename
7816214  346248  420496 8582958  82f72e i965_dri.so before
7816070  346248  420496 8582814  82f69e i965_dri.so after

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Mark brw_hw_type_to_reg_type() as a pure function

   text    data     bss     dec     hex filename
7816886  346248  420496 8583630  82f9ce i965_dri.so before
7816214  346248  420496 8582958  82f72e i965_dri.so after

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Hide the register type hardware encodings

So we stop mixing them with the logical enum.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Stop using hardware register types directly

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Move brw_reg_type_letters() as well

And add "to_" to the name for consistency with the other functions in
this file.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Switch to using the logical register types

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add functions to abstract access to register types

Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions
provided access to the hardware encodings for the register types. We
often mixed these with the logical BRW_REGISTER_TYPE_* enums (which
themselves used to be the hardware format!) with bad results.

With that functionality now available with the hw_ versions (see
previous commit), we now add functions that take the logical
BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice
versa. To do the conversion we also have to provide the file.

Note the asymmetry between the two functions: the new getter reads the
file from the instruction word, and to ensure that is always set the
setter writes both the file and the type.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Rename brw_inst's functions that access the register type

Put hw_ in the name so that it's clear these are the hardware encodings.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Index brw_hw_reg_type_to_size()'s table by logical type

I'll be transitioning everything to use the logical types.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add a brw_hw_type_to_reg_type() function

Will be used in later commits.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Use a common table to translate logical to hardware types

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Extract functions dealing with register types to separate file

I'm going to encapsulate all of the logic dealing with register types in
this file.

Rename the parameters for the hardware encodings from type -> hw_type at
the same time.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Reverse file/type arguments to register type functions

I think of the initial arguments as "state" and the last as the actual
subject.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Add support for disassembling 64-bit integer immediates

After the last patch converted things into enums, I helpfully got a
compiler warning about these missing from the switch statement.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Use separate enums for register vs immediate types

The hardware encodings often mean different things depending on whether
the source is an immediate.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Reorder brw_reg_type enum values

These vaguely corresponded to the hardware encodings, but that is purely
historical at this point. Reorder them so we stop making things "almost
work" when mixing enums.

The ordering has been closen so that no enum value is the same as a
compatible hardware encoding.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Validate destination restrictions with vector immediates

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Don't let raw-move check be tricked by immediate vector types

UB and B type encodings are the same as UV and VF. Noticed when writing
the following patch.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Only change type of 0.0f to VF if destination stride == 1

The destination stride must be equivalent to a dword if VF is used.

Also, since the only compaction table entires with "i:vf" have the
destination as "r:f" specifically check that the destination is of type
float.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Remove CONT/BREAK from instruction compaction test

These cannot be compacted. A similar mistake was fixed in commit
90eaf01616a8

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Test instruction compaction on all supported Gens

Note that there's no point in testing on G45, since its compaction is
the same as Gen5. Same logic applies to Gen7 variants and low-power
parts.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Silence signed/unsigned comparison warning

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Move compaction "prepass" into brw_eu_compact.c

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

i965: Mark src inst pointer const in compaction code

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

vulkan: import 1.0.59 headers and xml.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

Android: Fix LLVM duplicated symbols linking for N and M

Both statically linking libLLVMCore and dynamically linking libLLVM causes
duplicated symbols in gallium_dri.so and it fails to dlopen. We don't
really need to link libLLVMCore, but just need generated headers to be
built first. Dynamically linking to libLLVM instead is enough to do
that. Thanks to Qiang Yu for finding the root cause.

With this change, we can align all versions and just have libLLVM as a
shared lib dependency.

This also requires changes in the M and N versions of LLVM to export the
include paths for libLLVM. AOSP master is okay.

Fixes: 26aee6f4d5a ("Android: rework LLVM build support")
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>

docs: update calendar, add news item and link release notes for 17.1.7

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.1.7

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add release notes for 17.1.7

Signed-off-by: Andres Gomez <agomez@igalia.com>

st/va: add MJPEG for config

To enable MJPEG HW decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: reallocate surface with YUYV stream

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: detect MJPEG format from bitstream

To find if the format is supported YUYV by sampling factor which
is embedded from bitstream. So we could use this info for buffer
reallocation on the correct format.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: add YUYV format support for target buffer

Make chroma plane optional for YUYV support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: reallocate surface when interlaced

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/video: MJPEG not support stacked video buffers

So we have to detect it for reallocation of de-interlaced buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: make surface allocate functions more usefully

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: reconstruct MJPEG bitstream

The current tier 1 mjpeg firmware only supports at the bitstream
level, the later tier 2 support will be at the buffers level with
newer hardware.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>

st/va: add slice parameter handling for MJPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: add huffman table handling for MJPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: add iq matrix handling for MJPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: add picture parameter handling for MJPEG

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: add handles for MJPEG Buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: create decoder for MJPEG format

Mjpeg doesn't need reference

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: add MJPEG picture to context

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/video: add MJPEG support

v2: add ASIC and Kernel version check

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: add MJPEG support

There is no need of dpb buffer for mjpeg codec

v2: check dpb_size instead of format

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: add MJPEG stream type

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: add MJPEG picture description

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl: add MJPEG profile and format

v2: move util video change to here

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: get the target buffer pitch correct for different format

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: update non-resident bindless descriptors if needed

Only resident bindless descriptors are currently updated and
re-uploaded, this makes sure that the non-resident ones are
also updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

dri3: Move up fourcc utility function

It will be needed in next patches.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>

egl: Add dma_buf_import_modifiers for glvnd

Make sure we advertise the new entrypoints to libglvnd's EGL dispatch.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reported-by: Emmanuel Gil Peyrot <emmanuel.peyrot@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101982
Fixes: 4c412293d0e ("egl: advertise EGL_EXT_image_dma_buf_import_modifiers")

intel/blorp: Adjust intra-tile x when faking rgb with red-only

v2 (Jason): Adjust directly in surf_fake_rgb_with_red()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

ac/nir: fixup layer/viewport export for GFX9.

GFX9 moved where the viewport index export goes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965/bufmgr: s/BO_ALLOC_FOR_RENDER/BO_ALLOC_BUSY/

"Alloc for render" is a terrible name for a flag because it means
basically nothing.  What the flag really does is allocate a busy BO
which someone theorized at one point in time would be more efficient if
you're planning to immediately render to it.  If the flag really means
"alloc a busy BO" we should just call it that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/tex: Change the flags type on create_for_teximage

This matches the actual function declaration.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: only copy requested compressed teximage cubemap faces

This is analogous to commit 2259b11 which only fixed the regular case

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102308
Signed-off-by: Christoph Haag <haagch+mesadev@frickel.club>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

i965/tex: Don't pass samples to miptree_create_for_teximage

In 76e2f390f9863a35, when Topi switched num_samples from 0 to 1 for
single-sampled, he accidentally switched the last parameter in the call
to miptree_create_for_teximage from 0 to 1 thinking it was num_samples
when it was actually layout_flags.  Switching from 0 to 1 added the
MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a
busy BO instead of an idle one.  This caused the subsequent CPU upload
to consistently stall.  The end result was a 15% performance drop in the
SynMark v7 DrvRes microbenchmark.  This restores the old behavior and
fixes the performance regression.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes: 76e2f390f9863a356d1419982dec705260d67eff
Bugzilla: https://bugs.freedesktop.org/102260
Cc: mesa-stable@lists.freedesktop.org