i965: Mark functions static

Cuts 300 bytes of .text

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/intel/compiler/brw_fs_surface_builder.cpp b/src/intel/compiler/brw_fs_surface_builder.cpp
index 8990a5ca71019d9fa77fc7ffde106028a3948ddf..d00d8920b2b7f586ea7f6d39cf6c131b80054842 100644 (file)
--- a/src/intel/compiler/brw_fs_surface_builder.cpp
+++ b/src/intel/compiler/brw_fs_surface_builder.cpp
@@ -169,7 +169,7 @@ namespace {
        * they come in from SPIR-V or Vulkan.  We need to turn them into an ISL
        * enum before we can use them.
        */
-      enum isl_format
+      static enum isl_format
       isl_format_for_gl_format(uint32_t gl_format)
       {
          switch (gl_format) {
@@ -358,7 +358,7 @@ namespace {
       /**
        * Check whether the bound image is suitable for untyped access.
        */
-      brw_predicate
+      static brw_predicate
       emit_untyped_image_check(const fs_builder &bld, const fs_reg &image,
                                brw_predicate pred)
       {
@@ -390,7 +390,7 @@ namespace {
        * the comparison result to f0.0.  Returns an appropriate predication
        * mode to use on subsequent image operations.
        */
-      brw_predicate
+      static brw_predicate
       emit_typed_atomic_check(const fs_builder &bld, const fs_reg &image)
       {
          const gen_device_info *devinfo = bld.shader->devinfo;
@@ -420,7 +420,7 @@ namespace {
        * and write the comparison result to f0.0.  Returns an appropriate
        * predication mode to use on subsequent image operations.
        */
-      brw_predicate
+      static brw_predicate
       emit_bounds_check(const fs_builder &bld, const fs_reg &image,
                         const fs_reg &addr, unsigned dims)
       {
@@ -443,7 +443,7 @@ namespace {
        * the surface, which may be more than the sum of \p surf_dims and \p
        * arr_dims if padding is required.
        */
-      unsigned
+      static unsigned
       num_image_coordinates(const fs_builder &bld,
                             unsigned surf_dims, unsigned arr_dims,
                             isl_format format)
@@ -465,7 +465,7 @@ namespace {
        * Transform image coordinates into the form expected by the
        * implementation.
        */
-      fs_reg
+      static fs_reg
       emit_image_coordinates(const fs_builder &bld, const fs_reg &addr,
                              unsigned surf_dims, unsigned arr_dims,
                              isl_format format)
@@ -505,7 +505,7 @@ namespace {
        * Section 4.5 "Address Tiling Function" of the IVB PRM for an in-depth
        * explanation of the hardware tiling format.
        */
-      fs_reg
+      static fs_reg
       emit_address_calculation(const fs_builder &bld, const fs_reg &image,
                                const fs_reg &coord, unsigned dims)
       {
@@ -679,7 +679,7 @@ namespace {
        * shifts and widths.  Note that bitfield components are not allowed to
        * cross 32-bit boundaries.
        */
-      fs_reg
+      static fs_reg
       emit_pack(const fs_builder &bld, const fs_reg &src,
                 const color_u &shifts, const color_u &widths)
       {
@@ -712,7 +712,7 @@ namespace {
        * shifts and widths.  Note that bitfield components are not allowed to
        * cross 32-bit boundaries.
        */
-      fs_reg
+      static fs_reg
       emit_unpack(const fs_builder &bld, const fs_reg &src,
                   const color_u &shifts, const color_u &widths)
       {
@@ -740,7 +740,7 @@ namespace {
        * Convert an integer vector into another integer vector of the
        * specified bit widths, properly handling overflow.
        */
-      fs_reg
+      static fs_reg
       emit_convert_to_integer(const fs_builder &bld, const fs_reg &src,
                               const color_u &widths, bool is_signed)
       {
@@ -780,7 +780,7 @@ namespace {
        * Convert a normalized fixed-point vector of the specified signedness
        * and bit widths into a floating point vector.
        */
-      fs_reg
+      static fs_reg
       emit_convert_from_scaled(const fs_builder &bld, const fs_reg &src,
                                const color_u &widths, bool is_signed)
       {
@@ -810,7 +810,7 @@ namespace {
        * Convert a floating-point vector into a normalized fixed-point vector
        * of the specified signedness and bit widths.
        */
-      fs_reg
+      static fs_reg
       emit_convert_to_scaled(const fs_builder &bld, const fs_reg &src,
                              const color_u &widths, bool is_signed)
       {
@@ -859,7 +859,7 @@ namespace {
        * Convert a floating point vector of the specified bit widths into a
        * 32-bit floating point vector.
        */
-      fs_reg
+      static fs_reg
       emit_convert_from_float(const fs_builder &bld, const fs_reg &src,
                               const color_u &widths)
       {
@@ -890,7 +890,7 @@ namespace {
        * Convert a vector into a floating point vector of the specified bit
        * widths.
        */
-      fs_reg
+      static fs_reg
       emit_convert_to_float(const fs_builder &bld, const fs_reg &src,
                             const color_u &widths)
       {
@@ -927,7 +927,7 @@ namespace {
       /**
        * Fill missing components of a vector with 0, 0, 0, 1.
        */
-      fs_reg
+      static fs_reg
       emit_pad(const fs_builder &bld, const fs_reg &src,
                const color_u &widths)
       {

diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index 0e8807c5b42b57c6e0ab72411393a0751bb98e70..211682916f59b8d3034b23c56e26d0f84a8c7ca0 100644 (file)
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -2049,7 +2049,7 @@ vec4_visitor::nir_emit_jump(nir_jump_instr *instr)
    }
 }
 
-enum ir_texture_opcode
+static enum ir_texture_opcode
 ir_texture_opcode_for_nir_texop(nir_texop texop)
 {
    enum ir_texture_opcode op;
@@ -2073,7 +2073,8 @@ ir_texture_opcode_for_nir_texop(nir_texop texop)
 
    return op;
 }
-const glsl_type *
+
+static const glsl_type *
 glsl_type_for_nir_alu_type(nir_alu_type alu_type,
                            unsigned components)
 {

diff --git a/src/intel/compiler/brw_vec4_surface_builder.cpp b/src/intel/compiler/brw_vec4_surface_builder.cpp
index 00c94fedca20e0ebc783c73368120d5a4c320c26..5029cdce558bd825ea1ffef4ff5c8bc98ed66bf3 100644 (file)
--- a/src/intel/compiler/brw_vec4_surface_builder.cpp
+++ b/src/intel/compiler/brw_vec4_surface_builder.cpp
@@ -31,7 +31,7 @@ namespace {
        * Copy one every \p src_stride logical components of the argument into
        * one every \p dst_stride logical components of the result.
        */
-      src_reg
+      static src_reg
       emit_stride(const vec4_builder &bld, const src_reg &src, unsigned size,
                   unsigned dst_stride, unsigned src_stride)
       {
@@ -57,7 +57,7 @@ namespace {
        * left unmodified in SIMD4x2 form, otherwise it will be rearranged into
        * a SIMD8 vector.
        */
-      src_reg
+      static src_reg
       emit_insert(const vec4_builder &bld, const src_reg &src,
                   unsigned n, bool has_simd4x2)
       {
@@ -83,7 +83,7 @@ namespace {
        * argument is left unmodified in SIMD4x2 form, otherwise it will be
        * rearranged from SIMD8 form.
        */
-      src_reg
+      static src_reg
       emit_extract(const vec4_builder &bld, const src_reg src,
                    unsigned n, bool has_simd4x2)
       {