freedreno: Refactor the UBWC flags registers emission.

It's the same logic for each of these being emitted, and I was about to
change the rsc->layout.* for UBWC.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

freedreno: Drop the extra offset field for mipmap slices.

We can just bake the UBWC-goes-first delta into the slices at setup time.
I did have to fix up the resource shadowing swap path to swap the slice
fields, as it was missing and regressed the format reinterpets otherwise.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/decoder: Make get_state_size take a full 64-bit address and a base

i965 wants to use an offset from a base because everything is in a
single buffer whose address may be relocated, and all base addresses
are set to the start of that buffer.

iris wants to use a full 64-bit address, because state lives in separate
buffers which may be in the shader, surface, and dynamic memory zones,
where addresses grow downward from the top of a 4GB zone,  So it's very
possible for a 32-bit offset to exist relative to multiple bases,
leading to the wrong state size.

iris: INTEL performance query implementation

low-level implementation of INTEL-performance-query APIs in
Intel iris driver. Most of functions and procedures defined here
are adopted from i965 driver (brw_performance_query.c)

v2: - replace genX_init_performance_query with
      iris_init_perfquery_functions which is gen's version agnositic
    - general code clean-up

v3: include gen_perf_gens.h as some of defines were moved to this new
    header file

v4: - checking for kernel 4.13+ won't be needed here as Iris won't be
      loaded anyway without DRM_SYNCOBJ that is enabled after Kernel
      4.13.

    - checking whether gen < 8 or is_cherryview won't be required as
      well because those cases are screened in iris_screen_create.

v5: remove genX(init_performance_query)

v6: - remove oa_metrics_kernel_support as iris works only with kernel
    4.18 and newer.

    - use perf functions defined in separate file, iris_perf.h/c

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: separating out common perf code

The configuration of the gen_perf vtable will be the same for
INTEL_performance_query and AMD_performance_monitor.
Initialize the table in a single routine that can be called from both
implementations.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: enable INTEL_PERFORMANCE_QUERY

new state tracker APIs added for INTEL_performance_query
This extension is enabled if all vendor specific functions for it
exist.

v2: add st_cb_perfquery.* to the list of sources in Makefile
v3: minor code clean-up
v4: - add driver hooks for intel-performance-query apis
    - add PIPE level performance counter and type enums that
      match to OpenGL enums
    - do conversion of pipe_perf_counter_type and
      pipe_perf_counter_data_type enums to GL defines in state_tracker

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

meson/broadcom: libbroadcom_cle also needs zlib

Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>

anv: Enable Gen11 Color/Z write merging optimization

TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

iris: Enable Gen11 Color/Z write merging optimization

TCCNTLREG contains additional L3 cache write merging optimizations.

The default value on my system appears to be:
- URB Partial Write Merging (bit 0)
- L3 Data Partial Write Merging (bit 2)
- TC Disable (bit 3)

Windows drivers appear to set bit 1 as well to enable "Color/Z Partial
Write Merging".  This should solve an issue we were seeing where MRT
benchmarks were using substantially more bandwidth than they ought.
However, we have not observed it to cause measurable FPS gains.

It is unclear whether we should be setting bit 0 or bit 3, so for now
we leave those at the hardware default value.

Improves performance in Manhattan 3.0 by 6% on ICL 8x8 at a fixed
frequency, according to Felix Degrood.  I didn't see any improvements
at out-of-the-box power management settings, however.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Add a partial TCCNTLREG definition

TCCNTLREG contains additional cache programming settings.  In
particular, there are several write combining controls we'd like to use.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

util: Detect use-after-destroy in simple_mtx

This makes simple_mtx_destroy set the counter to an invalid canary
value and then makes lock/unlock assert that the value is legal.

That way, calling lock/unlock after destroy will assert fail,
rather than deadlocking or potentially even working.

This has caught real deadlocks in dEQP multithreaded tests (in st/mesa
shader variant zombie list handling), which have since been fixed.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>

freedreno/a6xx: enable LRZ by default

Now that dEQP should be happy, lets flip the switch.

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a6xx: fix LRZ logic

In particular, we need to invalidate the LRZ state when we cannot be
confident in what the Z state would be during rendering:

1) depth test modes not supported by LRZ
2) stencil test, which would require full rasterization and stencil
   test in the binning pass (whereas LRZ normally just needs to
   determine the min and max z value in an 8x8 quad)

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a6xx: fix LRZ layout

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a5xx+a6xx: split LRZ layout to per-gen

Seems to be a bit different for a6xx, so let's split this out.

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a6xx: disable LRZ when blending

Signed-off-by: Rob Clark <robdclark@chromium.org>

radeonsi: don't rely on CLEAR_STATE to set PA_SC_GENERIC_SCISSOR_*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: simplify the tess_turns_off_ngg condition

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: disable vertex grouping

based on PAL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: enable NIR by default and document GL 4.6 support

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

st/dri: assume external consumers of back buffers can write to the buffers

This was reverted needlessly because if was part of another series.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-By: Tapani Pälli <tapani.palli@intel.com>

ANV: Stop advertising smoothLines support on gen10+

Reviewed-by: Ivan Briano <ivan.briano@intel.com>

meson/broadcom: libbroadcom_cle needs expat headers

Fixes: 1ae8018a6af81eec4832a57d9d0346aa3dd98d28
       ("meson: Add support for the vc4 driver.")
Reviewed-by: Eric Anholt <eric@anholt.net>

anv: fix incorrect VMA alignment for CCS main surfaces

Maybe finer way of dealing with this requirement would be to increase
the number of pdevice->memory.types[] to add a category for special
alignment cases.

Meanwhile this fixes the problem of CCS surface alignment and it's
probably not going to cause issues given the size of our address
space.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6af8a4acc4a4 ("anv: Add aux-map translation for gen12+")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: fix missing gen12 handling

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 181be14d4303 ("anv: Build for gen12")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

docs: reword a bit and list HTTPS before FTP

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

meson: drop `intel_` prefix on imgui_core

Again, no real effect, just the name of a temporary build file.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

meson: drop duplicate `lib` prefix on libiris_gen*

This has no real effect other than the names of the temporary files in
the build folder.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv: implement VK_KHR_separate_depth_stencil_layouts

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: initialize HTILE for separate depth/stencil aspects

It either clears the whole HTILE buffer or part of it depending
on the HTILE mask parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not init HTILE as compressed state when dst layout allows it

I don't think this makes much differences and a potential clear
following the initialization will overwrite HTILE anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: synchronize after performing a separate depth/stencil fast clears

For depth+stencil images, the driver might use an optimized path
if only one aspect is cleared. It either clears the depth or the
stencil part of HTILE. Because the two separate aspects might use
the same HTILE memory we have to synchronize.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gitlab-ci: Don't exclude any piglit quick_shader tests

Now that we're running these with process isolation enabled, their
results will hopefully be stable.

Reviewed-by: Eric Anholt <eric@anholt.net>

gallivm: add TGSI bit arithmetic opcodes support

Add TGSI_OPCODE_BFI, TGSI_OPCODE_POPC, TGSI_OPCODE_LSB,
TGSI_OPCODE_IMSB, TGSI_OPCODE_UMSB, TGSI_OPCODE_IBFE,
TGSI_OPCODE_UBFE, TGSI_OPCODE_BREV support.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>

radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast

PA_SC_AA_CONFIG might be updated when conversative rasterization is
enabled. Because the driver only re-emits the multisample state if
the number of samples is different, that register value might not
be updated correctly.

Found by inspection, doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: move emission of two PA_SC_* registers to the pipeline CS

They don't have to be updated dynamically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

st/dri: use st->flush callback to flush the backbuffer

Previously the flush was done before the call to st->flush but
could lead to problems as FLUSH_VERTICES could push some work
that would change the backbuffer (or modify it).

With this commit, all the backbuffer flushing code is executed
right before the call to st_flush.

Closes: https://gitlab.freedesktop.org/drm/amd/issues/842
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=205049

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add a notify_before_flush callback param to flush

The new callback is called right before the flush is done to allow
users of st->flush to do some work after all the previous work has
been flushed.

This will be used by dri_flush in the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: dcc dirty flag

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix multi plane buffers creation

When using 3 planes, the sequence produces this chain:
  plane0 -> plane2
This commit fixes this to produce:
  plane0 -> plane1 -> plane2

Fixes: 86e60bc2659 ("radeonsi: remove si_vid_join_surfaces and use combined planar allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2193
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use gfx9.surf_offset to compute texture offset

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2177
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use compute shader for clear 12-byte buffer

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: release the draw shader properly to fix driver crashes (iris)

Reviewed-by: Dave Airlie <airlied@redhat.com>

draw, st/mesa: generate TGSI for ffvp/ARB_vp if draw lacks LLVM

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: don't generate VS TGSI if NIR is enabled

it's no longer needed

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: remove struct st_vp_variant in favor of st_common_variant

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: remove st_vp_variant::num_inputs

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: use a separate VS variant for the draw module

instead of keeping the IR indefinitely in st_vp_variant.

This trivially fixes Selection/Feedback/RasterPos for NIR.

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: support shader images for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: support SSBOs for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: support samplers for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: save currently bound vertex samplers and sampler views in st_context

for st_draw_feedback.c

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: support UBOs for Selection/Feedback/RasterPos

Reviewed-by: Dave Airlie <airlied@redhat.com>

gallivm: implement LOAD with CONSTBUF but don't enable it for llvmpipe

This is already used in st_draw_feedback.c, because it uses shaders
generated for drivers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

llvmpipe: implement TEX_LZ and TXF_LZ opcodes

gallivm receives these opcodes anyway because st_draw_feedback.c uses
shaders that were assembled for drivers, not llvmpipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

drirc: set allow_higher_compat_version for Faster Than Light

With 781a78 ("mesa: enable ARB_direct_state_access in compat for
GL3.1+), it's possible to have DSA with GL3.1+.

FTL creates a GL3.1 compat context, but fails the
_mesa_has_geometry_shaders(..) check in frame_buffer_texture.

Bump the compat version to pass the check.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util/atomic: Fix p_atomic_add for unlocked and msvc paths

Braces mismatch (flagged by CI, untested).

Fixes: 385d13f26d2 "util/atomic: Add a _return variant of p_atomic_add"
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

freedreno: Track the set of UBOs to be uploaded in UBO analysis.

We were iterating over the entire 32-entry array each time, when we
can just use a bitset to know that we're only uploading from the first
entry normally.

Knocks ir3_emit_user_consts down from ~.5% of CPU to .1% on WebGL
fishtank.

Reviewed-by: Rob Clark <robdclark@chromium.org>

freedreno: Stop forcing ALLOW_MAPPED_BUFFERS_DURING_EXEC off.

The default is to not throw GL errors when drawing with mapped
buffers, but we were forcing it on for unclear reasons.  Internally we
keep all our buffers mapped anyway, so it should be a no-op other than
reducing CPU overhead (.23% in a perf report for WebGL fishtank)

Reviewed-by: Rob Clark <robdclark@chromium.org>

freedreno/fdperf: use drmOpen()

Signed-off-by: Rob Clark <robdclark@chromium.org>

gallium/util: Support POLYGON in u_stream_outputs_for_vertices

u_decomposed_prims_for_vertices cannot support POLYGON, but POLYGON is
trivial to support as a special case directly (since we have the number
of vertices directly).

Fixes aborts in Panfrost in apps using GL_POLYGON.

Fixes: e881aa8c12c ("gallium/util: Add u_stream_outputs_for_vertices helper")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Revewied-by: Eric Anholt <eric@anholt.net>

intel: Add pci-ids for Jasper Lake

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel: Add device info for 1x4x6 Jasper Lake

Also removing the FIXME comments after matching the numbers with
updated documentation.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

lima: expose tiled format modifier in query_dmabuf_modifiers()

Fixes: 8c12f4e5f24f ("lima: enable tiling")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()

Assume that resource is tiled if we get DRM_FORMAT_MOD_INVALID
in resource_from_handle() and we don't have RO.

Fixes: 8c12f4e5f24f ("lima: enable tiling")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

turnip: add hw binning

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radv: do not use VK_TRUE/VK_FALSE

For consistency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gallivm: add bitfield reverse and ufind_msb

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>

gallium/scons: fix graw_gdi build

Fixes: 44a6b0107b37 (gallivm: add nir->llvm translation (v2))
Reviewed-by: Dave Airlie <Airlied@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

aco: propagate temporaries into expanded vectors

Gives a very slight decrease in code size:
Totals from affected shaders:
Code Size: 1708488 -> 1702768 (-0.33 %) bytes
Max Waves: 2858 -> 2855 (-0.10 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: improve readfirstlane after uniform ssbo loads on GFX7

pipeline-db changes for GFX7:

80310 shaders in 40472 tests
Totals:
SGPRS: 3655900 -> 3643916 (-0.33 %)
VGPRS: 2678324 -> 2686324 (0.30 %)
Spilled SGPRs: 1730 -> 1634 (-5.55 %)
Spilled VGPRs: 14 -> 21 (50.00 %)
Scratch size: 15540 -> 15536 (-0.03 %) dwords per thread
Code Size: 136106120 -> 135457616 (-0.48 %) bytes
LDS: 1259 -> 1259 (0.00 %) blocks
Max Waves: 601014 -> 600206 (-0.13 %)

Totals from affected shaders:
SGPRS: 307832 -> 295848 (-3.89 %)
VGPRS: 267864 -> 275864 (2.99 %)
Spilled SGPRs: 770 -> 674 (-12.47 %)
Spilled VGPRs: 14 -> 21 (50.00 %)
Scratch size: 16 -> 12 (-25.00 %) dwords per thread
Code Size: 22007488 -> 21358984 (-2.95 %) bytes
LDS: 65 -> 65 (0.00 %) blocks
Max Waves: 28668 -> 27860 (-2.82 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: use soffset for MUBUF instructions on SI/CI

pipeline-db changes for GFX7:

80310 shaders in 40472 tests
Totals:
SGPRS: 3655300 -> 3655900 (0.02 %)
VGPRS: 2677732 -> 2678324 (0.02 %)
Spilled SGPRs: 1730 -> 1730 (0.00 %)
Spilled VGPRs: 14 -> 14 (0.00 %)
Scratch size: 15540 -> 15540 (0.00 %) dwords per thread
Code Size: 136488364 -> 136106120 (-0.28 %) bytes
LDS: 1259 -> 1259 (0.00 %) blocks
Max Waves: 601039 -> 601014 (-0.00 %)

Totals from affected shaders:
SGPRS: 316312 -> 316912 (0.19 %)
VGPRS: 273844 -> 274436 (0.22 %)
Spilled SGPRs: 770 -> 770 (0.00 %)
Spilled VGPRs: 14 -> 14 (0.00 %)
Scratch size: 16 -> 16 (0.00 %) dwords per thread
Code Size: 22724904 -> 22342660 (-1.68 %) bytes
LDS: 114 -> 114 (0.00 %) blocks
Max Waves: 30861 -> 30836 (-0.08 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

radv: Enable ACO on GFX7 (Sea Islands)

This patch also disables AMD_shader_ballot on GFX7 by default if ACO is used.
Note that shader_ballot works correctly, but performance seems inferior.
To enable shader_ballot use RADV_PERFTEST=shader_ballot.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: return to loop_active mask at continue_or_break blocks

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

radv: disable Youngblood app profile if ACO is used

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement exclusive scan for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement inclusive_scan for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement (clustered) reductions for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: don't use a scalar temporary for reductions on GFX10

This patch also adds the scalar temporary for scans on SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: flush denorms after fmin/fmax on pre-GFX9

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

radv: only flush scalar cache for SSBO writes with ACO on GFX8+

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: disable disassembly for SI/CI due to lack of support by LLVM

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement 64bit ine/ieq for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement 64bit i2b for SI /CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: make 1/2*PI a literal constant on SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement 64bit VGPR shifts for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: split read/writelane opcode into VOP2/VOP3 version for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix disassembly of writelane instructions.

ACO writes an unused 3rd operand for internal usage
which makes LLVM recoginize it as illegal instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: recognize SI/CI SMRD hazards

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement quad swizzles for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: move buffer_store data to VGPR if needed

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement nir_op_isign on SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: only use scalar loads for readonly buffers on SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: implement nir_op_fquantize2f16 for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: fix SMEM offsets for SI/CI

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: SI/CI - fix sampler aniso

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: handle gfx7 int8/10 clamping on exports

Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: Initial GFX7 Support

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

aco: refactor visit_store_fs_output() to use the Builder

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>

anv: Re-emit all compute state on pipeline switch

It's a very odd case to hit in the real world.  However, there are some
CTS tests which switch back and forth between dispatch and clear without
changing the pipeline.

Fixes: bc612536eb2f "anv: Emit a dummy MEDIA_VFE_STATE before switching..."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>