arch-arm: Implementing SecureEL2 feature for Armv8

This patch adds Secure EL2 feature. This allows stage1
EL2/EL&0 and stage2 secure translation.
The changes are organized as follow:

  + insts/static_inst.cc: Modify checks for illegalInstruction on eret
  + isa.cc/hh: Enabling contorl bits
  + isa/insts/misc.hh/64.hh: Smc fault trigger.
  + miscregs.cc/hh: Declaration and initialization of new registers
  + self_debug.cc/hh: Add secureEL2 types for breakpoints
  + stage2_lookup.cc/hh: Allow stage2 in secure state.
  + tlb.cc/table_walker.cc: Allow secure state for stage2 and stage 1 EL2&0
                     translation regime
  + utility.cc/hh: New function InSecure and refactor of other helpers
                   to enable secure state

JIRA: https://gem5.atlassian.net/browse/GEM5-686

Change-Id: Ie59438b1828508e944334420da1d8f4745649056
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31394
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: relax GenericTimer check for CPU count

At Iff9ad68d64e67b3df51682b7e4e272e5f355bcd6 a check was added to prevent
segfaults when unserializing the GenericTimer in case the new number of
thread contexts was smaller than the old one pre-checkpoint.

However, GenericTimer objects are only created dynamically as needed after
timer miscreg accesses. Therefore, if we take the checkpoint before
touching those registers, e.g. from a simple baremetal example, then the
checkpoint saves zero timers, and upon restore the assert would fail
because we have one thread context and not zero:

> fatal: The simulated system has been initialized with 1 CPUs, but the
Generic Timer checkpoint expects 0 CPUs. Consider restoring the checkpoint
specifying 0 CPUs.

This commit solves that by ensuring only that the new thread context count
larger than, but not necessarily equal to the number of cores.

Change-Id: I8bcb05a6faecd4b4845f7fd4d71df95041bf6c99
JIRA: https://gem5.atlassian.net/browse/GEM5-703
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31894
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: add support for flat atomic adds, subs, incs, decs

Add support for all missing flat atomic adds, subtracts, increments,
and decrements, including their x2 variants.

Change-Id: I37a67fcacca91a09a82be6597facaa366105d2dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31974
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: fix name collisions in verifier.py

In verifier.py, testlib.test_util is imported and renamed to 'test',
while several functions in the file have a subfunction named 'test()',
which causes test.fail() to fail as 'test' points to the
subfunction instead of the module.

This commit addresses the above issue by keeping the imported module
as test_util instead of renaming it to test.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31994
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Avoid code duplication in Pl111

Change-Id: I17af93459ace0e4ef82693622a4135c3e831aaf5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31176
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Relax size constraint on AMBA ID registers

This patch is allowing non word sized accesses to the AMBA ID
registers.

Change-Id: I61a7163a3b4120e8dbcdbd6d9b83d33a7996f979
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31175
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin

Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31941
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix DTB autogen for HDLcd

The HDLcd was wrongly reporting the hardcoded IRQ=63 as the interrupt
number during DTB autogeneration. This is because the DTS is using 63.
However that corresponds to the SPI offset; the gem5 helper is
instead expecting the global IRQ number = 32 + SPI offset

Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make the Sp805 use the new ArmInterruptPin::active

Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make Sp804 use the ArmInterruptPin

Change-Id: I2d71c7e874ba1ec798e2314d7d282cb853b3f360
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31938
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin

Change-Id: I7318b9186cd81f948211e8a955dab7eea6d2a2f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31936
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Make Pl011 UART use the ArmInterruptPin

Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31935
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Introduce the active boolean for ArmInterruptPin

The active boolean will specify if the interrupt line is active
or not (high if it is active high or low if it is active low).

This is decoupled from the interrupt being in a pending state
within the GIC, and it can be used by a peripheral to query the
status of its interrupt pin

Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31934
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move checkpoint parameters for ptable into seperate section

In checkpoint output files, the parameters for page table including
size and entries are organized not very clearly. For example:

  [system.cpu.workload]
  ...
  ptable.size=...

  [system.cpu.workload.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.Entry1]
  ...

This commit moves these parameters into a separate section named
'ptable'. For example:

  [system.cpu.workload.ptable]
  size=...

  [system.cpu.workload.ptable.Entry0]
  vaddr=...
  paddr=...
  flags=...

  [system.cpu.workload.ptable.Entry1]
  ...

Change-Id: Iaa4129b3f4f090e8c3651bde90524abba0999c7f
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31874
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "writefile" unit test to the m5 utility.

Change-Id: Ic0e8d5fbbd5b6d6b57f674cef6460f94206a5872
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27628
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

configs: Change env defaults in apu_se.py for ROCm

This change simplifies the setup process for running
ROCm-based programs by adding the libraries that are
needed to LD_LIBRARY_PATH by default, using
preexisting environment variables that should be set
on the host.

HOME also gets set, as MIOpen-based programs can fail
without it set.

Change-Id: Ic599674babeaebb52de8a55981d04454cdc96cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30275
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

fastmodel: Implement GIC DTB auto-generation.

Implement generateDeviceTree for FastModelGIC so the interrupt
controller is automatically added to the DTB. This is sufficient to
allow a VExpressFastmodel system model to boot Linux without an
explicit DTB.

Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31078
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Remove scs_prefix_appli_output binding.

The scx_prefix_appli_output function is removed in recent Fast Models
releases.

Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31077
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix hierachical Iris component names.

Recent releases of Fast Models structure Iris resources in a hierarchy.
Use the parent resource ID if set to construct the hierachical name of
components when constructing the resource map.

Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31076
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add missing dependencies.

Add -latomic library required by recent Fast Models releases.
Add SystemCExport directory for tlm_has_get_protocol_types.h include.

Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31075
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base,scons: `-wno-deprecated-copy` added for hdf5.cc with GCC

As highlighted by Ciro here:
https://gem5-review.googlesource.com/c/public/gem5/+/31216, and
here: https://gem5.atlassian.net/browse/GEM5-365,  It appears that GCC
versions >= 9 requires `-wno-deprecated-copy` which was removed in
commit: https://gem5-review.googlesource.com/c/public/gem5/+/31216.
`-wno-deprecated-copy` appears to work for all versions of GCC. Clang
does not require `-wno-deprecated-copy` nor `-wno-deprecated` for
sucessfull compilation. Therefore branching has been introduced to the
SConscript to address this and simplify the solution.

Change-Id: I233b32aa945d479dd429bb5591272608ba342d8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31754
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs, mem: Support running VIPER with GCN3

This changeset adds the necessary changes for running
GCN3 ISA with VIPER in apu_se.py.

Changes to the VIPER protocol configs are made to add support
for DMA and scalar caches.

hsaTopology is added to help the pseudo FS create the files
needed by ROCm to understand the device on which the SW is
being run.

Change-Id: I0f47a6a36bb241a26972c0faafafcf332a7d7d1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30274
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ARM8.1-VHE feature

This commit implemented the VHE feature in ARMv8. This consist in 3
parts
    1. Register decl/init and register redirection from el1 to el2
        miscregs.cc/hh
        miscregs_types.hh
        isa.cc
        utility.cc/hh
    2. Definition of new EL2&0 translation regime.
        tlb.cc/hh
        table_walker.cc
        pagetable.hh
        tlbi_op.hh
        isa.cc ( for tlb invalidation functions)
    3. Self Debug adaptation for VHE
        self_debug.cc
    4. Effects on AMO/IMO/FMO interruptions
        faults.cc
        interrupts.hh

JIRA: https://gem5.atlassian.net/browse/GEM5-682

Change-Id: I478389322c295b1ec560571071626373a8c2af61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31177
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update HIP patch used in gcn Dockerfile

The new HIP patch includes a change that allows
calls to hipDeviceSynchronize() (and other functions
that call locked_wait()) to run without crashing

Change-Id: Iae6656c19168de696b0f94503e703be67f0baa09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31794
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Standardize console output in the m5 writefile command.

When the command reports an error, it should then exit(2) and not just
return as if everything worked. When printing the number of bytes
written or the file being opened, it should write this non-error message
to cout, and not cerr.

Also used proper capitalization and punctuation in a couple messages.

Change-Id: I2c0d6592357965ed2eee8f090c8b3d530b354b9f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27627
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the m5 utility's "readfile" command.

This feeds a fake file to the readfile command which is just a sequence
of incrementing 32 bit values. The incrementing values make sure that
the right region of the input file is being read at the right position,
and the relatively small size means there shouldn't be tons of zeroes
everywhere which can't be distinguished from each other.

Change-Id: I4286b1f92684f127c4885c29192c6c5244a61855
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27608
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add unit tests for most remaining m5 utility commands.

The only two which still need unit tests are the more complex commands,
readfile and writefile.

Change-Id: Ib9984c71fb4449cbbbd1e2a43f3140975328d31f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27607
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the m5 util's "sum" command.

This change adds the plumbing for and then implements a unit test for
the "sum" command. Despite the fact that this command is very simple,
there are a few things to verify.

1. That args are passed in the right positions.
2. That the number of arguments is checked correctly.
3. That the output to std::cerr is correct.

Change-Id: I71cd473b78fb710cac94df2d70c8d6dc76e5a037
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27566
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make m5 commands return a bool instead of calling usage.

By delegating actually calling usage() elsewhere, we can remove a dependency
from the commands themselves, and also make testing easier since we won't
exit() every time we call a command with bad arguments.

Change-Id: I6b8e2cb77ce0456b16673f10349362cc53218bba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27565
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Split up the commands into separate files in the m5 util.

This way each individual command can have a unit test written for it,
covering how it gathers its arguments and puts them passes them to the
underlying dispatch function.

Change-Id: Ia629c412c8906fc6f5ae02c509ed630755cee45c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27564
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "command" unit test for the m5 utility.

This tests the common "command" machinery, but not the individual
commands themselves.

Change-Id: I92769b4cef8210458786e60fd3c01e8e787fb9b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27563
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Redistribute command code in the m5 utility.

This division will make it easier to test both the common command code,
and the individual commands.

Change-Id: Ib7be2b93e40d07e9724443ba26784e45ad9d3b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27562
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "call_type" unit test to the m5 utility.

Change-Id: I6ffdf1242a063e776dbb7c18664755773a591b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27561
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add an "args" unit test to the m5 utility.

Change-Id: I7460daaff3301b09e071f2b7e8fb657909805438
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27560
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make the googletest library available to the m5 utility.

The library will be available for the abis so that they can test
their unique call mechanisms, and also the main/native environment for
testing shared components.

Build instructions for things that should be built natively, ie unit
tests for common components, should go in the new SConscript.native.

Change-Id: I4a84b2cf2165c92dfb1b6d903b18b45e4cba1352
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27559
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Use lookup function in cache

There is a function to perform lookups; there is no need to replicate
its code everywhere.

Change-Id: I1290594615d282722cd91071be8ef3c372414e4e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23946
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Cleanup replacement_data usage

The replacement_data can be assigned as soon as a block is allocated.
With this cleanup the lookup function can be used to avoid code
duplication.

Change-Id: I7561fddaa3ed348866699ecaf1e6aa477ba0bc9a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23945
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Getter/setter for atomic ops in WriteMask

Adding getter and setter methods for getting and setting the atomic ops
in the WriteMask class. This allows for message types with WriteMasks to
get or set the atomic ops without explicitly modifying the constructor
for the message type. This will beused by the DMASequencer which uses the
SequencerMsg type where the constructor is auto generated via SLICC.

Change-Id: I71787d294c1b89547618e9a13e386b65bb3e1021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31474
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix Trap to EL1 on register DC CVAU

Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Expose the "sum" m5 op in the m5 utility.

This is just for testing purposes, and can be used to sanity check that
m5 ops work when running a simulation.

Change-Id: I784d033fe4704e60ace5d109beac7bafe1498de6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27558
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim,misc: Add a new m5 op "sum" which just sums its inputs.

This very simple and mostly useless operation has no side effects, and
can be used to verify that arguments are making it into gem5, being
operated on, and then that a result can be returned into the simulation.

Change-Id: I29bce824078526ff77513c80365f8fad88fef128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27557
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Make the device file name used by map_m5_mem overridable.

The name this function uses is now exposed as a global variable called
m5_mmap_dev which can be changed at run time.

This would be useful if using a non-standard location for /dev/mem, or
for testing where we might want to use a totally different device.

Change-Id: I5e7ac106c3e4e0555c99af2a7a0aca8171534451
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27556
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: c++-ify usage printing in the m5 utility.

Change-Id: Ice8641d490fa9a510a6f1e246530ca5c82ef8170
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: c++-ify the commands in the m5 utility.

Change-Id: I6755892c42aa418aed64f1aafcdb8c1290b2e8d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27554
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Further consolidate the Args interface in the m5 utility.

Create static methods to convert any string to an integer or to pack it
into an array of integers. Create non-static methdos named pop() to
pop() the first element and simultaneously convert it. If the conversion
fails, the argument is not popped.

Change-Id: I55d98b3971e7abb7b6206d06ec7fcf046e828d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27553
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Move the m5 utility ABIs into a subdir.

Change-Id: Ia268fad950c8e7ad9ccfe69af72b57d33f6787b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27552
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Implement LevelSensitive PPIs in GICv3

Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31516
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Implement LevelSensitive SPIs in GICv3

Change-Id: If918a8aea934f0037818cc64bf458076bfd0251d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Gicv3 maintenance interrupt never cleared

The maintenance interrupt is a level sensitive interrupt though it has
been treated as edge triggered so far.

In order to be level sensitive, it needs to be cleared once the condition
which led to its generation are not valid anymore.

Change-Id: I9af9f4bf27622a7961393b00a145d6c9835d738b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31614
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add System register trap check for EL1

This change adds and refactors the register trap checks
for EL1 in the same function, unifying the registry trapping

Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31694
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

Those three snoop messages were the same, which made interpreting logs
harder.

Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix systemc array bound error

Currently, gcc 10.0 does not compile gem5 due to an array bound error
in sc_unsigned and sc_signed constructors.

Previous fix only ignores array-bounds warnings for sc_unsigned.cc and
sc_signed for gcc 10.1 onwards.

This commit turns the ignoring array-bounds warning flag on for all
gcc 10 onwards.

JIRA: https://gem5.atlassian.net/browse/GEM5-677.

Change-Id: Id65b6d52cef527f62917e09231ff79e2237affd8
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31634
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,arch: Fixed usage of `bitfield::replaceBits`

`bitfield::replaceBits` has two parameters, `first` and `last`, which
relate to the position of the MSB and the LSB of the bits to be replaced
respectively. Therefore `first` >= `last`. In some areas of the
codebase, this assumption has been flipped with `first` <= `last`. This
caused at least one known error, recorded here:
https://gem5.atlassian.net/browse/GEM5-695. These inconsistencies have
therefore been rectified.

A note has been added to the `bitfield::replaceBits` Doxygen to make
the usage of this function clearer.

Change-Id: Ie75856161d9a5684066430ecbdcc52e04e1e77bf
Issue-on: https://gem5.atlassian.net/browse/GEM5-696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31674
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Implement GDB XML target description for MIPS

Change-Id: Icff3b2c3e60d5989978de854247232afbb3b0dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31574
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch-arm: Fix Fault subsystem adding EL2Enable func

Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31374
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Check for security attribute when writing to ICFGR registers

This is matching the GICD_ICFGR read; a non secure access to a secure
interrupt should be treated as RAZ/WI

Change-Id: I9e92e03c13fe0474ed139b0ed22cebd5847b9109
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31615
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Remove SPI/PPI range check in Gicv3 class

This is not needed since the check will already happen within

* Gicv3Distributor::sendInt
* Gicv3Redistributor::sendPPInt

Change-Id: I1355bde367127513f0501aa19e8f68d302c7a4f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31514
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Updated compiler-tests to support paths with spaces

This script was failing if the gem5 directory path contained a space.
E.g: `/home/bobbys home/gem5`. This script has thereby been improved to
handle this.

Change-Id: Id56ff5a0e9aa31eef14de2111b040f7f2b0b286c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31534
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated git description length policy to 72 chars

Advocating <=75 characters is non-standard. 72 characters is
recommended. Furthermore, within Gerrit, descriptions >72 characters
causes ugly line-wrapping. This commit updates this policy to
72 characters.

The corresponding change within the gem5 webpage:
https://gem5-review.googlesource.com/c/public/gem5-website/+/31134

Change-Id: Iaf542a241772f8e400d8f90624712de1a435d096
Issue-on: https://gem5.atlassian.net/browse/GEM5-665
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31135
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: fix .testsignore for long regression

removed 2 tests from long regression to get nightly tests to pass
fixed .testignore, -arch64 changed to -aarch64, this enables running on ARM hw

Change-Id: Ic8456fef83dfba3417d1edcf62e90873d197d3d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31594
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,arch-riscv: Migrated asmtest to testlib

Issue-on: https://gem5.atlassian.net/browse/GEM5-141
Change-Id: I8f02e53157d32e21591c51e99de803366ad8fd8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27043
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>

arch-gcn3,gpu-compute: Fix GCN3 related compiler errors

Fix all errors that were revealed using the util/compiler-test.sh
script.

Change-Id: Ie0d35568624e5e1405143593f0677bbd0b066b61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31154
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Use beats_per_clock as the DDR data rate for DRAMPower

The data rate is used by the drampower lib to estimate the power
consumption of the DRAM Core. Previously, we used the formula:

burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
data_rate = p->burst_length / burst_cycles;

to derive the data_rate. However, under certain configurations this
formula computes the wrong result due to rounding errors. This patch
simplifies the way we derive the data_rate by passing the value of the
DRAM parameter beats_per_clock.

Change-Id: Ic8cd35bb4641d9c0a704675d2672a6fe4f4ec13e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30056
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

sim: Fixed error when compiling gem5 with dramsim2.

Compiling gem5 with dramsim2 included fails due to some inconsistencies in
including SimObjects. In this patch this issue is fixed along with
temporarily disabling -Werror=nonnull-compare in CCFLAGS. Also, the remote
for cloning dramsim2 has been changed.

Change-Id: Ia24095150d026d736352aaf0d735b7554ede10bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31434
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute, arch-gcn3: Change how waitcnts are implemented

Use single counters per memory operation type and increment
them upon issue, not execute.

Change-Id: I6afc0b66b21882538ef90a14a57a3ab3cc7bd6f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29973
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Add pipeline stage interface classes

This change separates the pipeline stage interfaces
for the GPU's compute unit into their own classes
with a well-defined interface. This helps to create
a cleaner interface for users to extend the CU
pipeline's capabilities and also helps consolidate
all the pipeline communication code in one place
in the source.

Change-Id: I569d52bce84dc1b9fbf8f0f96d53a81a2b6773c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29972
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Add case to op selector when operand is vcc_hi

Change-Id: Ib8846656e18aad04ccb8c9112bc629c69078fe36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29971
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: No RF scheduling in case of SKIP or EMPTY

In case of flat memory instructions the status for the
LM pipe execution unit is set to SKIP or EMPTY, as the bus
between the VRF and the GM and LM pipe is shared. The
destination operands should not be scheduled for the LM pipe,
event if the wave is in the dispatch list. This can lead
to deadlock in the destination cache as DCEs are reused
and the slotsAvailableForBank count gets artificially
incremented.

Change-Id: I2230c53e3bc1032d2cccbe00fab62c99ab8de6cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29970
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Use refs to CU in pipe stages/mem pipes

The pipe stages and memory pipes are changed to store
a reference to their parent CU as opposed to a pointer.
These objects will never change which CU they belong to,
and they are constructed by their parent CU.

Change-Id: Ie5476e1e2e124a024c2efebceb28cb3a9baa78c1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29969
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Fix stride bug in buffer OOB detection logic

The out-of-range logic for buffer accesses is missing the top 4 bits of
const_stride when dealing with scratch buffers.  This can cause
perfectly valid scratch acceses to be suppressed when const_stride is
large.

Change-Id: I8f94d44c242fda26cf6dfb75db04fa3aca934b3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29968
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Replace some instances of std::isnormal with std::fpclassify

Affected instructions: V_DIV_SCALE_F64, V_CMP_CLASS_F64,
V_CMPX_CLASS_F64 and their VOPC, VOP3, F32 variants.

These instances of std::isnormal were being used to check for
subnormal (denorms) values. std::isnormal is not specific enough.
It returns true for normal values but false for NaN, Inf, 0.0, and
subnormals. std::fpclassify returns macros for each category of
floating point numbers. Now we only catch subnormals.

Change-Id: I8d8f4452ff58de71e7c8e0b2b5e73467b532e196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29967
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Fix VOP3 V_LDEXP_F64

Replaced !std::isnormal with std::fpclassify because std::isnormal
is not specific enough. !std::isnormal was incorrectly catching
NaN, Inf, 0.0, and subnormals (aka denormals), where as it was only
suppose to catch subnormals.

The return value and error handling spec of std::ldexp listed on
cppreference.com appears to match up in nearly all cases after
making these changes. If std::ldexp handled subnormals as described
in the GCN3 2016 guide, we could have used vdst[lane] = std::ldexp
and not need to check for any corner cases.

Change-Id: I4c77af77c3b7798f86d40442610cef1296a28441
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29966
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Fix Y-dimension ABI decode

We currently have a bug in decoding workitem ID from the kernel
descriptor with multiple dimensions.  The enable_vgpr_workitem_id bits
are currently seperated into x and y components, when they should be
treated as a single 2 bit value, where y is enabled when it is > 0,
and z is enabled when it is > 1.  The current setup allows a kernel
launch with vgprs reserved for the z dimension and not the y dimension,
which is incorrect.

Change-Id: Iee64b207feb95bcf064898d5db33b8f201e25323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29965
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Fix roundNearestEven for V_RNDNE_F64 and V_RNDNE_F32

roundNearestEven is an inst_util function that RNDNE_F64 and F32
call, including both VOP1 and VOP3 formats. IEEE 754 spec says this
function should round inputs to the nearest integer but round ties
to the nearest even integer. Prior to this patch it was rounding all
inputs to nearest even, not just the ties. It was probably implemented
this way originally because the language in the ISA manual is ambiguous
although it provided the correct logic.

Fixed roundNearestEven to use the semantics originally described in
the GCN3 ISA manual.

Change-Id: I83ecb1d516fcf5bdf17e54ddf409b447a129a9a7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29964
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Don't track vector store insts in CU's headTailMap

This change fixes a memory leak due to live GPUDynInstPtr references
to vector store insts being stored in the CU's headTailMap and never
released.

This happened because store insts are not supposed to have their
head-tail latencies tracked by the headTailMap; instead they use
timing information from the GPUCoalescer. When updating the
headTailLatency stat via the headTailMap, only loads were considered
and removed from the headTailMap, however when inserting into the
headTailMap loads and stores were considered, thus leading to the
memory leak.

This change fixes the issue by only adding loads to the headTailMap.

Change-Id: I8a8f5b79f55e00481ae5e82519a9ed627a7ecbd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29963
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: add all s_buffer_load_dword instructions

Adds the other s_buffer_load_dword* instruction implementations to
f134a84.

Change-Id: I8d97527278900dc68c32463ea1824409ccd04e1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29962
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Add memcpy condition when writing EXEC_LO

Some compilers emit an error on the operand template class when writing
exec mask. Add a condition to explicitly set memcpy size argument to
32b or 64b based on the number of dwords.

Change-Id: I49b0e4a1680283e772d0a5a8efd687b31d4f1624
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29961
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Remove invalid assert when reading EXEC_LO

This assert assumed all reads to EXEC_LO would be
64b, that is, we would always read the entire EXEC
mask. This is invalid as some kernels read only
the low 32b of EXEC.

The write to EXEC_LO is also updated to handle 32b
writes.

Change-Id: Ifeb167578515bf112b1eab70bbf2201a5e936358
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29960
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu_compute: Support loading BLIT kernels

The BLIT kernels used to implement DMA through the shaders don't fill
out all of the standard fields in an amd_kernel_code_t object.  This
patch modifies the code object parsing logic to support these new
kernels.

BLIT kernels are used in APUs when using ROCm memcopies for certain size
buffers, and are used for dGPUs when the SDMA engines are disabled.

Change-Id: Id4e667474d05e311097dbec443def07dfad14a79
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29959
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Implement ds_swizzle

Change-Id: I7d188388afa16932217ae207368666a724207c52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29958
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Implement s_buffer_load_dwordx16

Change-Id: I25382dcae9bb55eaf035385fa925157f25d39c20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29957
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Fixup DIV instructions

Adds support to handle the special cases
for GCN3 DIV instructions.

Change-Id: I18f91870e802407c93831f313ce76be053bc4230
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29956
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix builds on Power systems

Based on the 64-bit ELF ABI for Power systems (ppc64 and
ppc64le), the data types int64_t and uint64_t are typedefs
of long and unsigned long respectively. If the SystemC
data types int64 and uint64 point to these, several errors
are observed while building the simulator on Power systems
due to ambiguity between the types when overloading some
operators and functions.

E.g.
  ...
  build/POWER/systemc/ext/channel/../dt/bit/sc_bit.hh:114:17: error: 'static bool sc_dt::sc_bit::to_value(sc_dt::int64)' cannot be overloaded with 'static bool sc_dt::sc_bit::to_value(long int)'
    114 |     static bool to_value(tp i) { return to_value((int)i); }
        |                 ^~~~~~~~
  ...
  build/POWER/systemc/ext/channel/../dt/bit/sc_bit.hh:114:17: note: previous declaration 'static bool sc_dt::sc_bit::to_value(long int)'
    114 |     static bool to_value(tp i) { return to_value((int)i); }
        |                 ^~~~~~~~
  ...

This adds a minor change to a SystemC datatype header to
ensure that the simulator can be built on Power systems.

Change-Id: Icd8bb38134bf98768cc38f9856d7d11a01ebaf21
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31414
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a ProxyPtr test.

Change-Id: If71cc374030a5ef0dab62d351bc83960ff509af7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29401
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: fixed scale,fixup,fmas f64 ops

Change-Id: Ie13794554db8a958fda1f7103ec18058fda2e66d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29955
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Fix s_getpc operand information

s_getpc was currently reporting only a single operand,
and was only considering the SSRC operand. However,
this instruction' source is implicitly the PC.
Because its destination register was never tracked for
dependence checking purposes, dependence violations
are possible.

Change-Id: Ia80b8b3e24d5885f646a9ee41212a2cb35b9ffe6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29954
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Add handling for Inf/overflow in CVT insts

Change-Id: I0fddffdeaebd9f45fe89f44d536f80a43de63ff5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29953
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: Add ds_bpermute and ds_permute insts

The implementation of these insts provided by this
change is based on the description provided here:

https://gpuopen.com/amd-gcn-assembly-cross-lane-operations/

Change-Id: Id63b6c34c9fdc6e0dbd445d859e7b209023f2874
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29952
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: ds_read_u8 and ds_read_u16 fix

This changeset zero extends the destination register
for ds_read_u8 and ds_read_u16 instructions.

Change-Id: I193adadd68adf2572b59743b1504f18ad225f506
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29951
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: convert vALU instruction counters from 32 to 64-bit

The vALU instruction counters were previously 32 bits, but for some
workloads this value wraps around and triggers an assert failure
because the max vALU operations are reached.  To resolve this, this
commit increases the counter size to 64 bits.

Change-Id: I90ed4514669485cfea7ccc37ba9d69665277bccb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29950
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: implement instruction s_setreg_b32

Instruction s_setreg_b32 was unimplemented, but is used by hipified
rodinia 'srad'. The instruction sets values of hardware internal
registers. If the instruction is writing into MODE to control
single-precision FP round and denorm modes, a simple warn will be
printed; for all other cases (non-MODE hw register or other
precisions), panic will happen.

Change-Id: Idb1cd5f60548a146bc980f1a27faff30259e74ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29949
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>

arch-gcn3: add support for v_mbcnt_hi and v_mbcnt_lo

Change-Id: I1c70fe693c904f1abd7d5a2b99220c74a075eae5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29948
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: fix bug with DPP support

Instructions that use the DPP field need to use the extra SRC0
register associated with the DPP instruction instead of the
"default" SRC0 register, since the default SRC0 register contains
the DPP information when DPP is being used.  This commit fixes
2735c3bb88 to take this into account.  Additionally, this commit
removes write of the src register from the DPP helper functions,
to avoid overwriting any changes made to the destination register.
Finally, this change modifies the instructions that use DPP to
simplify the flow through the execute() functions.

Change-Id: I80fd0af1f131f287f18ff73b3c1c9122d8c60823
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29947
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

arch-gcn3: implement multi-dword buffer loads and stores

Add support for all multi-dword buffer loads and stores:
buffer_load_dword x2, x3, and x4 and buffer_store_dword x2, x3, and x4

Change-Id: I4017b6b4f625fc92002ce8ade695ae29700fa55e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29946
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Init CU object for pipe stages in their ctors

This change updates the constructors of the CU's pipe
stages/memory pipelines to accept a pointer to their
parent CU. Because the CU creates these objects, and
can pass a pointer to itself to these object via their
constructors, this is the safer way to initalize these
classes.

Change-Id: I0b3732ce7c03781ee15332dac7a21c097ad387a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29945
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Add support for rd/wr EXEC_HI to operand class

Change-Id: Ib22dd604f88ea56801964235082835002deffca1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29944
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute, arch-gcn3: refactor barriers

Barriers were not modeled properly. Firstly, barriers were
allocated to each WG that was launched, which is not
correct, and the CU would provide an infinite number
of barrier slots. There are a limited number of barrier slots
per CU in reality. In addition, the CU will not allocate
barrier slots to WGs with a single WF (nothing to sync if
only one WF).

Beyond modeling problems, there also the issue of deadlock.
The barrier could deadlock because not all WFs are freed
from the barrier once it has been satisfied. Instead, we
relied on the scoreboard stage to release them lazily,
one-by-one.

Under this implementation the scoreboard may not fully release
all WFs participating in a barrier; this happens because the
first WF to be freed from the barrier could reach an s_barrier
instruction again, forever causing the barrier counts across
WFs to be out-of-sync.

This change refactors the barrier logic to:

1) Create a proper barrier slot implementation

2) Enforce (via a parameter) the number of barrier
   slots on the CU.

3) Simplify the logic and cleanup the code (i.e., we
   no longer iterate through the entire WF list each
   time we check if a barrier is satisfied).

4) Fix deadlock issues.

Change-Id: If53955b54931886baaae322640a7b9da7a1595e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29943
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: add support of 64-bit SOPK instruction

s_setreg_imm32_b32 is a 64-bit instruction, using a 32-bit literal
constant. Related functions are added to support decoding the second
dword.

Change-Id: I290f8578f726885c137dbfac3773035f814e0a3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29942
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>

arch-gcn3: ensure that atomics follow HSA conventions

Add asserts to make sure atomics are following the HSA conventions
that atomics should be word aligned (i.e., can't be byte aligned)
and should not be misaligned such that a given lane's access
spans multiple cache lines.

Change-Id: Ia48758b9ed96764864234dc607f337e30e287d1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29941
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

gpu-compute: Fix LDS out-of-bounds behavior

The LDS is capable of handling out-of-bounds accesses,
that is, accesses that are outside the bounds of the
chunk allocated to a WG. Currently, the simulator asserts
on these accesses. This patch changes the behavior of the
LDS to return 0 for reads and dropping writes that are
out-of-bounds.

Change-Id: I5f467d0f52113e8565e1a3029e82fb89cc6f07ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29940
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>