riscv-isa-sim.git
6 years agoFix for issue #183: No illegal instruction exception for c.sxxi instructions encoded...
Shubhodeep Roy Choudhury [Fri, 16 Mar 2018 08:16:20 +0000 (13:46 +0530)]
Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount

6 years agoFix a bug caused by moving misa into state_t. (#180)
Prashanth Mundkur [Wed, 14 Mar 2018 16:48:11 +0000 (09:48 -0700)]
Fix a bug caused by moving misa into state_t. (#180)

* Fix misa losing its value in processor constructor due to state:reset() following state.misa initialization.
Make state:reset() preserve misa.

* Set state.misa to max_isa on reset().

* Idiomatic fix for earlier commit.

6 years agoMove processor.isa to state.misa, since it really belongs there.
Prashanth Mundkur [Tue, 13 Mar 2018 23:32:41 +0000 (16:32 -0700)]
Move processor.isa to state.misa, since it really belongs there.

6 years agoFix single stepping csrrw instructions (#178)
Tim Newsome [Sat, 10 Mar 2018 01:54:07 +0000 (17:54 -0800)]
Fix single stepping csrrw instructions (#178)

This code is still a bit voodoo to me, but now we pass all the tests
again. (Stepping was broken by
4299874ad4b07ef457776513a64e5b2397a6a75e.)

6 years agoMerge pull request #177 from riscv/debug_auth
Tim Newsome [Thu, 8 Mar 2018 01:17:39 +0000 (17:17 -0800)]
Merge pull request #177 from riscv/debug_auth

Add debug module authentication.

6 years agoNarrow the interface used by the processors and memory to the top-level simulator...
Prashanth Mundkur [Tue, 20 Feb 2018 23:16:53 +0000 (15:16 -0800)]
Narrow the interface used by the processors and memory to the top-level simulator/htif.
This allows the implementation of an alternative top-level simulator class.

6 years agoFix install of a missed header from debug_rom.
Prashanth Mundkur [Mon, 26 Feb 2018 23:37:01 +0000 (15:37 -0800)]
Fix install of a missed header from debug_rom.

The installed header files from the riscv subproject were incomplete, since
processor.h includes debug_rom_defines.h, and the latter was not installed.
Fix by moving it into riscv/, add it to the riscv subproject header list, which
ensures it will get installed.  While here, also add a missed dependency of debug_rom
on riscv/encoding.h to debug_rom/Makefile.

6 years agoFix a missed header file in the softfloat include install.
Prashanth Mundkur [Mon, 26 Feb 2018 23:21:27 +0000 (15:21 -0800)]
Fix a missed header file in the softfloat include install.

6 years agoImplement clearing-misa.C-while-PC-is-misaligned proposal
Andrew Waterman [Thu, 22 Feb 2018 23:19:26 +0000 (15:19 -0800)]
Implement clearing-misa.C-while-PC-is-misaligned proposal

See https://github.com/riscv/riscv-isa-manual/pull/139

Not adopted yet, but I'm putting the implementation here for reference.

6 years agoEnforce 2-byte alignment of mepc/sepc/dpc
Andrew Waterman [Thu, 22 Feb 2018 00:09:31 +0000 (16:09 -0800)]
Enforce 2-byte alignment of mepc/sepc/dpc

6 years agoMerge pull request #173 from riscv/no_progbuf3
Tim Newsome [Thu, 1 Mar 2018 23:18:01 +0000 (15:18 -0800)]
Merge pull request #173 from riscv/no_progbuf3

Add support for abstract debug access to CSRs and FPRs

6 years agoAdd debug module authentication.
Tim Newsome [Tue, 27 Feb 2018 20:30:46 +0000 (12:30 -0800)]
Add debug module authentication.

Off by default, enabled with --debug-auth.
The protocol is very simple (definitely not secure) to allow debuggers
to test their authentication feature. To authenticate a debugger must:
1. Read authdata
2. Write to authdata the value that it just read, plus 1

6 years agoDon't allow 32-bit instructions to take up multiple slots in I$
Andrew Waterman [Wed, 21 Feb 2018 21:25:44 +0000 (13:25 -0800)]
Don't allow 32-bit instructions to take up multiple slots in I$

I$ indices now maintain a 1:N relationship with PCs.  This is somewhat
faster and also simpler.

6 years agoMerge pull request #171 from riscv/sysbusbits
Tim Newsome [Mon, 19 Feb 2018 19:55:19 +0000 (11:55 -0800)]
Merge pull request #171 from riscv/sysbusbits

Add support for debug bus mastering

6 years agoPasses smoke tests with --progsize=0
Tim Newsome [Tue, 30 Jan 2018 22:13:23 +0000 (14:13 -0800)]
Passes smoke tests with --progsize=0

6 years agoWIP. Doesn't work.
Tim Newsome [Tue, 30 Jan 2018 20:19:55 +0000 (12:19 -0800)]
WIP. Doesn't work.

6 years agoImplement cycleh/instreth CSRs for RV32 (#172)
Andrew Waterman [Tue, 13 Feb 2018 18:43:36 +0000 (10:43 -0800)]
Implement cycleh/instreth CSRs for RV32 (#172)

6 years agoAdd --debug-sba option
Tim Newsome [Thu, 1 Feb 2018 22:32:00 +0000 (14:32 -0800)]
Add --debug-sba option

This lets the user control whether the system bus access implements bus
mastering.

6 years agoUpdate debug_defines
Tim Newsome [Mon, 29 Jan 2018 19:52:31 +0000 (11:52 -0800)]
Update debug_defines

6 years agoSupport debug system bus access.
Tim Newsome [Fri, 12 Jan 2018 23:26:00 +0000 (15:26 -0800)]
Support debug system bus access.

6 years agoUse new debug_defines.h.
Tim Newsome [Tue, 9 Jan 2018 20:29:34 +0000 (12:29 -0800)]
Use new debug_defines.h.

6 years agomem_t: Throw an error if zero-sized memory is requested (#168)
Jonathan Neuschäfer [Tue, 9 Jan 2018 00:00:55 +0000 (01:00 +0100)]
mem_t: Throw an error if zero-sized memory is requested (#168)

* mem_t: Throw an error if zero-sized memory is requested

If for some reason the user requests a memory size of 0 megabytes, print
a useful error message.

* Check for overflow in memory size

If the user passes in a large enough memory size (-m) that the size in
bytes doesn't fit into size_t, catch this error in the make_mems function.

6 years agoAdd some missing RVC instructions to disassembler
Andrew Waterman [Wed, 3 Jan 2018 21:06:21 +0000 (13:06 -0800)]
Add some missing RVC instructions to disassembler

6 years agoMerge pull request #165 from riscv/small_progbuf
Tim Newsome [Mon, 18 Dec 2017 22:25:42 +0000 (14:25 -0800)]
Merge pull request #165 from riscv/small_progbuf

Add support for program buffer of size 2

6 years agoUpdate debug_defines to latest version.
Tim Newsome [Mon, 11 Dec 2017 22:28:10 +0000 (14:28 -0800)]
Update debug_defines to latest version.

6 years agoSet impebreak.
Tim Newsome [Thu, 12 Oct 2017 19:07:11 +0000 (12:07 -0700)]
Set impebreak.

6 years agoUpdate to latest debug_defines.h.
Tim Newsome [Thu, 12 Oct 2017 19:05:26 +0000 (12:05 -0700)]
Update to latest debug_defines.h.

6 years agoMake progbuf a run-time option.
Tim Newsome [Tue, 10 Oct 2017 22:53:23 +0000 (15:53 -0700)]
Make progbuf a run-time option.

Also add an implicit ebreak after the program buffer. This is not part
of the spec, but hopefully it will be.

6 years agoRename badaddr to tval
Andrew Waterman [Mon, 27 Nov 2017 22:29:03 +0000 (14:29 -0800)]
Rename badaddr to tval

6 years agoRename sptbr to satp
Andrew Waterman [Mon, 27 Nov 2017 22:28:29 +0000 (14:28 -0800)]
Rename sptbr to satp

6 years agoSet tval to 0 on traps with no specified tval
Andrew Waterman [Mon, 27 Nov 2017 22:18:06 +0000 (14:18 -0800)]
Set tval to 0 on traps with no specified tval

Simply not writing the register was not a conformant implementation.

6 years agoImplement priv-1.11 interrupt-priority scheme (#161)
Andrew Waterman [Mon, 20 Nov 2017 19:58:14 +0000 (11:58 -0800)]
Implement priv-1.11 interrupt-priority scheme (#161)

Closes #159.

https://github.com/riscv/riscv-isa-manual/commit/a62e76cb16eb508199f74632eb8bf263739f25a3

6 years agoFix commitlog. (#162)
Christopher Celio [Mon, 20 Nov 2017 19:41:31 +0000 (11:41 -0800)]
Fix commitlog. (#162)

A regression caused any instruction with rd=x0 to not be emitted.

6 years agoMerge pull request #156 from p12nGH/noncontiguous_harts
Andrew Waterman [Thu, 16 Nov 2017 00:17:40 +0000 (16:17 -0800)]
Merge pull request #156 from p12nGH/noncontiguous_harts

Support for non-contiguous hartids

6 years agohartids knob description added
Gleb Gagarin [Wed, 15 Nov 2017 23:42:39 +0000 (15:42 -0800)]
hartids knob description added

6 years agoSupport for non-contiguous hartids
Gleb Gagarin [Wed, 15 Nov 2017 23:35:59 +0000 (15:35 -0800)]
Support for non-contiguous hartids

7 years agoRemove redundant U/S mode advertisement
Andrew Waterman [Fri, 10 Nov 2017 03:27:20 +0000 (19:27 -0800)]
Remove redundant U/S mode advertisement

7 years agoH-mode no longer exists
Andrew Waterman [Fri, 10 Nov 2017 02:46:27 +0000 (18:46 -0800)]
H-mode no longer exists

It's supplanted by the hypervisor extension, which doesn't use the privilege
encoding of 2; it still looks like supervisor (i.e. 1).

7 years agoMPP is now WARL
Andrew Waterman [Fri, 10 Nov 2017 02:45:48 +0000 (18:45 -0800)]
MPP is now WARL

7 years agoImplement Q extension for disassembler (#153)
Kito Cheng [Mon, 6 Nov 2017 20:16:50 +0000 (04:16 +0800)]
Implement Q extension for disassembler (#153)

7 years agoFix disassembly of c.li 0
Andrew Waterman [Sat, 4 Nov 2017 01:13:22 +0000 (18:13 -0700)]
Fix disassembly of c.li 0

Resolves #152

7 years agoMerge pull request #151 from riscv/htif_dts
Palmer Dabbelt [Fri, 3 Nov 2017 23:29:57 +0000 (16:29 -0700)]
Merge pull request #151 from riscv/htif_dts

Put HTIF in the device tree

7 years agoPut HTIF in the device tree
Palmer Dabbelt [Fri, 3 Nov 2017 22:38:12 +0000 (15:38 -0700)]
Put HTIF in the device tree

I wanted to actually put the address of the HTIF into the DTS, but that
seems to be a bit too much work: since the HTIF addresses are just
defined in an ELF file it's a bit awkward to make that work.

Instead, I'm just putting a dummy HTIF key in the DTS.

7 years agoMask medeleg correctly
Andrew Waterman [Fri, 3 Nov 2017 02:15:42 +0000 (19:15 -0700)]
Mask medeleg correctly

7 years agoDon't permit delegation of interrupts that M-mode should handle
Andrew Waterman [Thu, 2 Nov 2017 01:57:02 +0000 (18:57 -0700)]
Don't permit delegation of interrupts that M-mode should handle

7 years agoFix commit-log for Q extension, and for RV32 (#143)
Andrew Waterman [Fri, 20 Oct 2017 04:07:22 +0000 (00:07 -0400)]
Fix commit-log for Q extension, and for RV32 (#143)

* Fix commit-log for Q extension, and for RV32

The number of nibbles printed out now depends upon XLEN or FLEN,
as appropriate.

* Factor out FLEN calculation

7 years agoFix bus_t bug with devices at 0x0
Evan Cox [Thu, 19 Oct 2017 16:40:10 +0000 (11:40 -0500)]
Fix bus_t bug with devices at 0x0

Fix a bug that prevented bus_t from storing to, loading from,
or finding a device that existed at address 0x0.

Resolves: #135

7 years agoFix implementation of FMIN/FMAX NaN case
Andrew Waterman [Thu, 19 Oct 2017 19:18:23 +0000 (12:18 -0700)]
Fix implementation of FMIN/FMAX NaN case

If rd=rs1 or rd=rs2, the NaN check examined the wrong value.

7 years agoInclude math.h for NAN (#137)
jar [Sun, 15 Oct 2017 18:22:45 +0000 (14:22 -0400)]
Include math.h for NAN (#137)

commit 85c40db208db3e26f507dc6a74a5dc540b504b5c introduced a NAN dependency but did not include the math.h header

7 years agoMerge pull request #129 from riscv/q-extension
Andrew Waterman [Wed, 11 Oct 2017 01:17:58 +0000 (18:17 -0700)]
Merge pull request #129 from riscv/q-extension

Implement Q extension

7 years agoImplement Q extension
Andrew Waterman [Mon, 25 Sep 2017 03:34:04 +0000 (20:34 -0700)]
Implement Q extension

7 years agoMerge pull request #128 from riscv/reset
Tim Newsome [Mon, 25 Sep 2017 18:05:36 +0000 (11:05 -0700)]
Merge pull request #128 from riscv/reset

Fix debug reset.

7 years agoUpdate SoftFloat
Andrew Waterman [Mon, 25 Sep 2017 03:25:34 +0000 (20:25 -0700)]
Update SoftFloat

7 years agoActually let hartreset be set.
Tim Newsome [Thu, 21 Sep 2017 21:54:06 +0000 (14:54 -0700)]
Actually let hartreset be set.

7 years agoFix debug reset.
Tim Newsome [Thu, 21 Sep 2017 19:34:42 +0000 (12:34 -0700)]
Fix debug reset.

ndmreset now resets all harts (instead of just the current hart), and
hartreset resets the selected hart (instead of being ignored).

7 years agoFix corner case in repeated execution (#127)
Tim Newsome [Thu, 21 Sep 2017 19:42:20 +0000 (12:42 -0700)]
Fix corner case in repeated execution (#127)

Specifically, don't print out the execution count if the same
instruction is executed by different harts.

7 years agoFix comment typo. (#126)
Tim Newsome [Thu, 21 Sep 2017 18:48:31 +0000 (11:48 -0700)]
Fix comment typo. (#126)

7 years agoMerge pull request #123 from riscv/debug_interrupts
Tim Newsome [Tue, 12 Sep 2017 20:53:17 +0000 (13:53 -0700)]
Merge pull request #123 from riscv/debug_interrupts

Don't take interrupts while in Debug Mode.

7 years agoDon't take interrupts while in Debug Mode.
Tim Newsome [Tue, 12 Sep 2017 18:04:08 +0000 (11:04 -0700)]
Don't take interrupts while in Debug Mode.

7 years agoMerge pull request #121 from riscv/debug_store
Tim Newsome [Mon, 28 Aug 2017 22:46:08 +0000 (15:46 -0700)]
Merge pull request #121 from riscv/debug_store

Add a nice debug printf for debug_module_t::store

7 years agoAdd a nice debug printf for debug_module_t::store
Tim Newsome [Mon, 28 Aug 2017 22:19:41 +0000 (15:19 -0700)]
Add a nice debug printf for debug_module_t::store

7 years agoMerge pull request #119 from riscv/quiet
Tim Newsome [Fri, 11 Aug 2017 22:48:15 +0000 (15:48 -0700)]
Merge pull request #119 from riscv/quiet

Turn off debug module debug printfs.

7 years agoTurn off debug module debug printfs.
Tim Newsome [Fri, 11 Aug 2017 22:35:22 +0000 (15:35 -0700)]
Turn off debug module debug printfs.

Nobody wants to see all that, and if they do they should recompile.

7 years agoCorrect c.li and c.lui disassembly (#118)
Palmer Dabbelt [Thu, 10 Aug 2017 22:50:30 +0000 (15:50 -0700)]
Correct c.li and c.lui disassembly (#118)

I currently get this disassembly

    00004881 jr      a7

but if I understand that's incorrect and I want

    00004881 li      a7, 0

If I'm reading the ISA manual correctly, the disassembler was just wrong
here.

7 years agoMerge pull request #117 from riscv/multicore_debug
Tim Newsome [Thu, 10 Aug 2017 20:44:42 +0000 (13:44 -0700)]
Merge pull request #117 from riscv/multicore_debug

Fix multicore debug.

7 years agoFix multicore debug.
Tim Newsome [Mon, 7 Aug 2017 18:21:58 +0000 (11:21 -0700)]
Fix multicore debug.

In an older implementation I was thinking of having different entry
points for different harts, but that's no longer true.

Also get rid of a bunch of trailing whitespace.

7 years agoRemove reference to H-mode in ECALL
Andrew Waterman [Fri, 30 Jun 2017 20:19:18 +0000 (13:19 -0700)]
Remove reference to H-mode in ECALL

7 years agoMerge pull request #113 from riscv/debug_readme
Palmer Dabbelt [Wed, 14 Jun 2017 21:39:15 +0000 (14:39 -0700)]
Merge pull request #113 from riscv/debug_readme

Update README to use --rbb-port

7 years agoSupport 64-bit start PCs in reset vector.
Tim Newsome [Wed, 14 Jun 2017 19:42:00 +0000 (12:42 -0700)]
Support 64-bit start PCs in reset vector.

7 years agoUpdate README to use --rbb-port
Tim Newsome [Fri, 9 Jun 2017 17:30:40 +0000 (10:30 -0700)]
Update README to use --rbb-port

7 years agoMerge pull request #112 from riscv/autoexecwrite
Tim Newsome [Fri, 9 Jun 2017 17:05:18 +0000 (10:05 -0700)]
Merge pull request #112 from riscv/autoexecwrite

Return success on writes to abstractauto

7 years agoReturn success on writes to abstractauto
Tim Newsome [Fri, 9 Jun 2017 17:00:36 +0000 (10:00 -0700)]
Return success on writes to abstractauto

This bug was exposed by newer OpenOCD which actually checks the result.

7 years agoMerge pull request #110 from riscv/debug_rom_build
Tim Newsome [Thu, 8 Jun 2017 20:31:04 +0000 (13:31 -0700)]
Merge pull request #110 from riscv/debug_rom_build

`make clean && make` works again in debug_rom

7 years agoMerge pull request #111 from riscv/dtm_reset_error
Tim Newsome [Thu, 8 Jun 2017 20:28:48 +0000 (13:28 -0700)]
Merge pull request #111 from riscv/dtm_reset_error

Reset to "success" instead of "error."

7 years agoReset to "success" instead of "error."
Tim Newsome [Thu, 8 Jun 2017 20:05:01 +0000 (13:05 -0700)]
Reset to "success" instead of "error."

OpenOCD actually checks this initial value now, and there's no reason
for it to indicate error.

7 years ago`make clean && make` works again in debug_rom
Tim Newsome [Thu, 8 Jun 2017 19:58:11 +0000 (12:58 -0700)]
`make clean && make` works again in debug_rom

7 years agoForbid S-mode execution from user memory
Andrew Waterman [Wed, 7 Jun 2017 21:17:58 +0000 (14:17 -0700)]
Forbid S-mode execution from user memory

https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a

7 years agoMerge pull request #108 from riscv/dtc-error
Palmer Dabbelt [Mon, 5 Jun 2017 19:57:58 +0000 (12:57 -0700)]
Merge pull request #108 from riscv/dtc-error

Configure should fail if device-tree-compiler is not installed

7 years agoConfigure should fail if device-tree-compiler is not installed
Andrew Waterman [Mon, 5 Jun 2017 19:55:26 +0000 (12:55 -0700)]
Configure should fail if device-tree-compiler is not installed

Fixes #107

7 years agominNum -> minimumNumber
Andrew Waterman [Thu, 25 May 2017 09:19:46 +0000 (02:19 -0700)]
minNum -> minimumNumber

7 years agoMerge pull request #104 from riscv/disable-werror
Palmer Dabbelt [Tue, 23 May 2017 15:47:43 +0000 (08:47 -0700)]
Merge pull request #104 from riscv/disable-werror

Disable -Werror when building

7 years agoDisable -Werror when building
Palmer Dabbelt [Tue, 23 May 2017 15:33:20 +0000 (08:33 -0700)]
Disable -Werror when building

This has a tendency to blow up on other platforms.

7 years agoMerge remote-tracking branch 'origin/priv-1.10'
Palmer Dabbelt [Wed, 17 May 2017 20:07:47 +0000 (13:07 -0700)]
Merge remote-tracking branch 'origin/priv-1.10'

7 years agoMerge remote-tracking branch 'origin/debug-0.13' into priv-1.10
Palmer Dabbelt [Tue, 16 May 2017 16:33:40 +0000 (09:33 -0700)]
Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10

7 years agoBetter error message when doing DMI operations and we're busy
Palmer Dabbelt [Tue, 16 May 2017 01:33:27 +0000 (18:33 -0700)]
Better error message when doing DMI operations and we're busy

7 years agodebug: whitespace errors
Megan Wachs [Mon, 15 May 2017 17:06:08 +0000 (10:06 -0700)]
debug: whitespace errors

7 years agoMerge branch 'debug-0.13' into HEAD
Megan Wachs [Mon, 15 May 2017 16:53:42 +0000 (09:53 -0700)]
Merge branch 'debug-0.13' into HEAD

7 years agoMake C.LI/C.LUI trapping behavior match spec
Andrew Waterman [Sun, 14 May 2017 05:37:22 +0000 (22:37 -0700)]
Make C.LI/C.LUI trapping behavior match spec

7 years agoUXL=SXL=MXL
Andrew Waterman [Fri, 5 May 2017 23:27:08 +0000 (16:27 -0700)]
UXL=SXL=MXL

https://github.com/riscv/riscv-isa-manual/commit/326bec83de23f4d2daf24cfed6b5251748cad632

7 years agoTrap superpage PTEs when PPN LSBs are set
Andrew Waterman [Fri, 5 May 2017 21:39:26 +0000 (14:39 -0700)]
Trap superpage PTEs when PPN LSBs are set

7 years agoAdd missing include for devices.h
Kito Cheng [Wed, 3 May 2017 09:58:54 +0000 (17:58 +0800)]
Add missing include for devices.h

 - https://github.com/riscv/riscv-tools/issues/69

7 years agoFix segfault when accessing bad memory addresses
Andrew Waterman [Mon, 1 May 2017 23:44:47 +0000 (16:44 -0700)]
Fix segfault when accessing bad memory addresses

7 years agoSet default entry point from ELF
Andrew Waterman [Mon, 1 May 2017 21:44:42 +0000 (14:44 -0700)]
Set default entry point from ELF

7 years agoAdd option to set start pc
Andrew Waterman [Mon, 1 May 2017 06:45:27 +0000 (23:45 -0700)]
Add option to set start pc

7 years agoSupport more flexible main memory allocation
Andrew Waterman [Mon, 1 May 2017 05:03:15 +0000 (22:03 -0700)]
Support more flexible main memory allocation

7 years agoStore both host & target address in soft TLB
Andrew Waterman [Mon, 1 May 2017 00:37:06 +0000 (17:37 -0700)]
Store both host & target address in soft TLB

7 years agoMerge pull request #96 from riscv/ndmreset
Palmer Dabbelt [Wed, 26 Apr 2017 21:22:00 +0000 (14:22 -0700)]
Merge pull request #96 from riscv/ndmreset

Updates to match the latest debug spec

7 years agoRemove a debugging printf
Palmer Dabbelt [Wed, 26 Apr 2017 16:14:07 +0000 (09:14 -0700)]
Remove a debugging printf

7 years agoDon't spin on the remote bitbang reads
Palmer Dabbelt [Wed, 26 Apr 2017 16:13:49 +0000 (09:13 -0700)]
Don't spin on the remote bitbang reads

7 years agoHandle abstractcs.busy
Palmer Dabbelt [Wed, 26 Apr 2017 16:13:19 +0000 (09:13 -0700)]
Handle abstractcs.busy