openpower-isa.git
2 years agoannoying. DX-Form is one exception to the rule of having the
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 15:04:29 +0000 (16:04 +0100)]
annoying. DX-Form is one exception to the rule of having the
immediate be directly actual fields.  the immediate has to be
"de-constructed" before fitting into its places, d0 d1 and d2

2 years agoset IN1 to NONE for fmvis
Konstantinos Margaritis [Tue, 26 Jul 2022 14:48:21 +0000 (14:48 +0000)]
set IN1 to NONE for fmvis

2 years agofix form and pseudo-code for fmvis, tests in 64-bit mode
Konstantinos Margaritis [Tue, 26 Jul 2022 13:57:46 +0000 (13:57 +0000)]
fix form and pseudo-code for fmvis, tests in 64-bit mode

2 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Tue, 26 Jul 2022 13:25:24 +0000 (14:25 +0100)]
whitespace cleanup

2 years agofix fmvis decoder, it's now a 2-operand instruction
Konstantinos Margaritis [Tue, 26 Jul 2022 13:22:30 +0000 (13:22 +0000)]
fix fmvis decoder, it's now a 2-operand instruction

2 years agoAdd fmvis instruction + tests, bug #887
Konstantinos Margaritis [Tue, 26 Jul 2022 10:02:35 +0000 (10:02 +0000)]
Add fmvis instruction + tests, bug #887

2 years agosvp64.py: fix alignment
Dmitry Selyutin [Mon, 25 Jul 2022 12:39:25 +0000 (15:39 +0300)]
svp64.py: fix alignment

2 years agosvp64.py: update svindex operands
Dmitry Selyutin [Mon, 25 Jul 2022 12:24:39 +0000 (15:24 +0300)]
svp64.py: update svindex operands

2 years agodump output from pypowersim_fp
Luke Kenneth Casson Leighton [Sat, 23 Jul 2022 13:16:38 +0000 (14:16 +0100)]
dump output from pypowersim_fp

2 years agowhoops missing variables in new subfunction after
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:27:49 +0000 (17:27 +0100)]
whoops missing variables in new subfunction after
moving code around in ISACaller

2 years agoadd dsubstep to ISACaller
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:22:19 +0000 (17:22 +0100)]
add dsubstep to ISACaller

2 years agosort out subvl unit test with expected results
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 16:01:42 +0000 (17:01 +0100)]
sort out subvl unit test with expected results

2 years agofix loopend conditions for subvectors in ISACaller
Luke Kenneth Casson Leighton [Thu, 21 Jul 2022 11:38:48 +0000 (12:38 +0100)]
fix loopend conditions for subvectors in ISACaller

2 years agorename substep to ssubstep, add dsubstep to SVP64State
Luke Kenneth Casson Leighton [Wed, 20 Jul 2022 19:20:06 +0000 (20:20 +0100)]
rename substep to ssubstep, add dsubstep to SVP64State

2 years agoadd first subvl unit test, subvl comes from
Luke Kenneth Casson Leighton [Wed, 20 Jul 2022 18:35:24 +0000 (19:35 +0100)]
add first subvl unit test, subvl comes from
RM not SVSTATE

2 years agomove D-Immediate rewriting in ISACaller into separate function
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:47:08 +0000 (21:47 +0100)]
move D-Immediate rewriting in ISACaller into separate function

2 years agomove inputs in ISACaller into get_input()
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:42:08 +0000 (21:42 +0100)]
move inputs in ISACaller into get_input()

2 years agomove debug remap to ISACaller.remap_debug()
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:34:43 +0000 (21:34 +0100)]
move debug remap to ISACaller.remap_debug()

2 years agowhitespace and function-return code-morphing in ISACaller
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:29:22 +0000 (21:29 +0100)]
whitespace and function-return code-morphing in ISACaller

2 years agomove another function in ISACaller (check_write)
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:10:59 +0000 (21:10 +0100)]
move another function in ISACaller (check_write)

2 years agobegin function split in ISACaller
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 20:05:27 +0000 (21:05 +0100)]
begin function split in ISACaller
https://bugs.libre-soc.org/show_bug.cgi?id=728

2 years agoremove duplicate code create ISACaller.advance_svstate_steps()
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 19:55:47 +0000 (20:55 +0100)]
remove duplicate code create ISACaller.advance_svstate_steps()
which performs required stepping of src/dst/sub-steps

2 years agoadd SUBVL (substep) support to PowerDecoder2 and to ISACaller.
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 16:37:36 +0000 (17:37 +0100)]
add SUBVL (substep) support to PowerDecoder2 and to ISACaller.
the actual computation (multiplication) is done inside PowerDecoder2
which will need to understand Pack/Unpack at some point
https://bugs.libre-soc.org/show_bug.cgi?id=871

2 years agoadd substep getter/setter to SVP64State
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 13:58:49 +0000 (14:58 +0100)]
add substep getter/setter to SVP64State

2 years agorename SVSTATE.svstep to SVSTATE.substep to avoid
Luke Kenneth Casson Leighton [Mon, 18 Jul 2022 10:50:53 +0000 (11:50 +0100)]
rename SVSTATE.svstep to SVSTATE.substep to avoid
a name-conflict with the instruction "svstep"

2 years agosimplify remapyield.py, skip shows the bit to be skipped
Luke Kenneth Casson Leighton [Sat, 16 Jul 2022 17:49:04 +0000 (18:49 +0100)]
simplify remapyield.py, skip shows the bit to be skipped

2 years agogot fed up of long list of ifs for manually decoded ".long"s,
Luke Kenneth Casson Leighton [Thu, 14 Jul 2022 18:26:09 +0000 (19:26 +0100)]
got fed up of long list of ifs for manually decoded ".long"s,
replaced with a single search

2 years agoadd jit_test for testing icbi and isync
Jacob Lifshay [Thu, 14 Jul 2022 09:21:54 +0000 (02:21 -0700)]
add jit_test for testing icbi and isync

TODO: integrate into unit test framework

2 years agoadd DX-Form FRS for fmvis
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 15:48:10 +0000 (16:48 +0100)]
add DX-Form FRS for fmvis
https://bugs.libre-soc.org/show_bug.cgi?id=887

2 years agoadd recognition of 0xNNN and 0bMMMM to sv/trans/svp64.py
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 09:31:05 +0000 (10:31 +0100)]
add recognition of 0xNNN and 0bMMMM to sv/trans/svp64.py
for translation of "non-supported" opcodes in binutils

2 years agoadd FRS as destination to PowerDecoder2 DecodeOut
Luke Kenneth Casson Leighton [Tue, 12 Jul 2022 09:30:21 +0000 (10:30 +0100)]
add FRS as destination to PowerDecoder2 DecodeOut

2 years agoadd mm=1 svindex test, setting single targetted SVSHAPE
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 12:29:47 +0000 (13:29 +0100)]
add mm=1 svindex test, setting single targetted SVSHAPE

2 years agofix issue in SelectableInt.__rsub__ causing truncation of values
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 12:21:44 +0000 (13:21 +0100)]
fix issue in SelectableInt.__rsub__ causing truncation of values

2 years agofix issue in SelectableInt using slices involving SelectableInts
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 11:55:51 +0000 (12:55 +0100)]
fix issue in SelectableInt using slices involving SelectableInts

2 years agoAdded insn initialisation for grev() func
Andrey Miroshnikov [Mon, 11 Jul 2022 10:47:59 +0000 (10:47 +0000)]
Added insn initialisation for grev() func

2 years agoMissed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:24:38 +0000 (11:24 +0100)]
Missed another two form sub-headings

2 years agoMissed another two form sub-headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:18:19 +0000 (11:18 +0100)]
Missed another two form sub-headings

2 years agoFixed missing space for form headings
Andrey Miroshnikov [Mon, 11 Jul 2022 10:15:49 +0000 (11:15 +0100)]
Fixed missing space for form headings

2 years agocompute 2nd svindex dimension using unsignee compare
Luke Kenneth Casson Leighton [Mon, 11 Jul 2022 00:45:09 +0000 (01:45 +0100)]
compute 2nd svindex dimension using unsignee compare

2 years agoadd yx svindex test, needed to compute size of 2nd dim
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 17:52:20 +0000 (18:52 +0100)]
add yx svindex test, needed to compute size of 2nd dim

2 years agoIndexed SVSHAPE add bypass mode when dim sizes are 1
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:50 +0000 (17:18 +0100)]
Indexed SVSHAPE add bypass mode when dim sizes are 1

2 years agoadd second svindex test, modulo 3
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:18:05 +0000 (17:18 +0100)]
add second svindex test, modulo 3

2 years agofix svindex pseudocode, set large 2nd dim on nonskip
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 16:17:09 +0000 (17:17 +0100)]
fix svindex pseudocode, set large 2nd dim on nonskip

2 years agofix svindex unit test, experiment setting dimensions
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 12:59:26 +0000 (13:59 +0100)]
fix svindex unit test, experiment setting dimensions
to 0b111111 in svindex pseudocode

2 years agofix SVSHAPE iterator for index case, stop deepcopy
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:26 +0000 (12:42 +0100)]
fix SVSHAPE iterator for index case, stop deepcopy
(was copying entire GPR)

2 years agoadd new svindex sv.add test with arbitrary index map
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:42:02 +0000 (12:42 +0100)]
add new svindex sv.add test with arbitrary index map

2 years agonon-persistence enabled on svindex as well as svremap
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 11:41:32 +0000 (12:41 +0100)]
non-persistence enabled on svindex as well as svremap

2 years agofix svindex pseudocode
Luke Kenneth Casson Leighton [Sun, 10 Jul 2022 10:53:56 +0000 (11:53 +0100)]
fix svindex pseudocode
rename RS to SVG in SVI-Form (svindex) to avoid a register name conflict
start checking things properly in test_caller_svindex.py

2 years agopass GPR to SVSHAPEs in ISACaller
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 21:12:06 +0000 (22:12 +0100)]
pass GPR to SVSHAPEs in ISACaller

2 years agoadd gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:45:12 +0000 (21:45 +0100)]
add gpr lookup in Indexed SVSHAPE iterator (no elwidths yet)

2 years agorough unit test ahowing Index REMAP basically functional in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 20:26:28 +0000 (21:26 +0100)]
rough unit test ahowing Index REMAP basically functional in SVSHAPE

2 years agoadd support for Indexed mode in SVSHAPE
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 19:39:53 +0000 (20:39 +0100)]
add support for Indexed mode in SVSHAPE

2 years agoadd storing of shape in requested SVSHAPE in svindex pseudocode
Luke Kenneth Casson Leighton [Sat, 9 Jul 2022 12:58:21 +0000 (13:58 +0100)]
add storing of shape in requested SVSHAPE in svindex pseudocode

2 years agomove DX Form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 21:08:46 +0000 (22:08 +0100)]
move DX Form

2 years agoadd first stub of svindex pseudocode
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 17:54:07 +0000 (18:54 +0100)]
add first stub of svindex pseudocode
https://bugs.libre-soc.org/show_bug.cgi?id=885

2 years agoaudio/mp3: convert asm to the new notation
Dmitry Selyutin [Wed, 6 Jul 2022 17:33:43 +0000 (20:33 +0300)]
audio/mp3: convert asm to the new notation

https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agosvp64.py: allow macros as register names
Dmitry Selyutin [Wed, 6 Jul 2022 17:10:52 +0000 (17:10 +0000)]
svp64.py: allow macros as register names

This patch enables things like *fv0, where *fv0 is just a macro.
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agosvp64.py: generate registers
Dmitry Selyutin [Thu, 30 Jun 2022 13:11:25 +0000 (16:11 +0300)]
svp64.py: generate registers

2 years agoadd svindex to power_enums.py, minor_22.csv
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 16:55:36 +0000 (17:55 +0100)]
add svindex to power_enums.py, minor_22.csv
https://bugs.libre-soc.org/show_bug.cgi?id=867

2 years agoindentation on fields.txt to make it more markdown-like
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 15:55:28 +0000 (16:55 +0100)]
indentation on fields.txt to make it more markdown-like

2 years agoconvert Logical svp64_cases.py to new vector reg form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:37:17 +0000 (08:37 +0100)]
convert Logical svp64_cases.py to new vector reg form
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agoconvert ALU svp64_cases.py to new vector reg form
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:23:28 +0000 (08:23 +0100)]
convert ALU svp64_cases.py to new vector reg form
https://bugs.libre-soc.org/show_bug.cgi?id=884

2 years agoconverted test_caller_svstate.py to new reg format
Luke Kenneth Casson Leighton [Wed, 6 Jul 2022 07:12:06 +0000 (08:12 +0100)]
converted test_caller_svstate.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconvert test_caller_svp64.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 22:11:03 +0000 (22:11 +0000)]
convert test_caller_svp64.py to new vector numbering convention

2 years agoconvert test_caller_svp64_predication.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 22:04:00 +0000 (22:04 +0000)]
convert test_caller_svp64_predication.py to new vector numbering convention

2 years agoconvert test_caller_svp64_ldst.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 21:52:54 +0000 (21:52 +0000)]
convert test_caller_svp64_ldst.py to new vector numbering convention

2 years agoUpdated the nmigen.sim import
Andrey Miroshnikov [Tue, 5 Jul 2022 21:10:07 +0000 (21:10 +0000)]
Updated the nmigen.sim import

2 years agoconvert test_caller_svp64_fft.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 21:05:48 +0000 (21:05 +0000)]
convert test_caller_svp64_fft.py to new vector numbering convention

2 years agoconvert test_caller_svp64_bc.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 19:21:44 +0000 (19:21 +0000)]
convert test_caller_svp64_bc.py to new vector numbering convention

2 years agoconvert test_caller_svp64_dct.py to new vector numbering convention
Andrey Miroshnikov [Tue, 5 Jul 2022 18:52:29 +0000 (18:52 +0000)]
convert test_caller_svp64_dct.py to new vector numbering convention

2 years agoconverted test_caller_svp64_matrix.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 18:01:30 +0000 (19:01 +0100)]
converted test_caller_svp64_matrix.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconverted test_caller_svp64_fp.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:57:07 +0000 (18:57 +0100)]
converted test_caller_svp64_fp.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconverted test_caller_svp64_mapreduce.py to new reg format
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:51:41 +0000 (18:51 +0100)]
converted test_caller_svp64_mapreduce.py to new reg format
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoconvert test_caller_setvl.py to new vector numbering convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:34:08 +0000 (18:34 +0100)]
convert test_caller_setvl.py to new vector numbering convention
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoadd "*%" and "*" vector-numbering convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:21:55 +0000 (18:21 +0100)]
add "*%" and "*" vector-numbering convention
https://bugs.libre-soc.org/show_bug.cgi?id=884#c0

2 years agoadd note about bug #884 new reg vector naming convention
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 17:19:29 +0000 (18:19 +0100)]
add note about bug #884 new reg vector naming convention

2 years agoadd regression test for completely borked value from mulhd
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 13:04:24 +0000 (14:04 +0100)]
add regression test for completely borked value from mulhd
https://bugs.libre-soc.org/show_bug.cgi?id=855

2 years agotake deepcopy of regs passed in to avoid accidental modification
Luke Kenneth Casson Leighton [Tue, 5 Jul 2022 13:02:29 +0000 (14:02 +0100)]
take deepcopy of regs passed in to avoid accidental modification

2 years agoadd setvl CTR tests, fix CTR mode
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 17:11:59 +0000 (18:11 +0100)]
add setvl CTR tests, fix CTR mode

2 years agofix setvl CTR mode
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 16:59:34 +0000 (17:59 +0100)]
fix setvl CTR mode

2 years agosetvl has new CTR mode, making room in encoding needed
Luke Kenneth Casson Leighton [Sat, 2 Jul 2022 16:37:47 +0000 (17:37 +0100)]
setvl has new CTR mode, making room in encoding needed
fixing unit tests

2 years agodo CSV isatables explicitly in sv_analysis.py
Luke Kenneth Casson Leighton [Thu, 30 Jun 2022 11:33:47 +0000 (12:33 +0100)]
do CSV isatables explicitly in sv_analysis.py
for pandoc to pick up

2 years agoexplicit output of opcode_regs_deduped in mdwn table format
Luke Kenneth Casson Leighton [Thu, 30 Jun 2022 11:04:27 +0000 (12:04 +0100)]
explicit output of opcode_regs_deduped in mdwn table format
so as to make it possible to convert to latex with pandoc

2 years agoadd recognition of "sv." to pysvp64asm
Luke Kenneth Casson Leighton [Tue, 28 Jun 2022 16:30:28 +0000 (17:30 +0100)]
add recognition of "sv." to pysvp64asm

2 years agoremove qemu co-simulation, dump output expected results
Luke Kenneth Casson Leighton [Tue, 28 Jun 2022 15:23:38 +0000 (16:23 +0100)]
remove qemu co-simulation, dump output expected results
test/basic_pypowersim

2 years agoadd predicate mask test svstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:33:06 +0000 (23:33 +0100)]
add predicate mask test svstep

2 years agowhoops svp64.py testing wrong variable on sv.svstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:13:27 +0000 (23:13 +0100)]
whoops svp64.py testing wrong variable on sv.svstep

2 years agoadd predicated srcstep
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 22:04:29 +0000 (23:04 +0100)]
add predicated srcstep

2 years agomake svstep output srcstep/dststep, basically viota
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 21:56:01 +0000 (22:56 +0100)]
make svstep output srcstep/dststep, basically viota

2 years agorename SVRM *field* to SVrm to avoid a name-clash with
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 17:23:35 +0000 (18:23 +0100)]
rename SVRM *field* to SVrm to avoid a name-clash with
SVRM-*Form*

2 years agosvp64.py: decrement SVd operand
Dmitry Selyutin [Sun, 26 Jun 2022 17:10:19 +0000 (20:10 +0300)]
svp64.py: decrement SVd operand

2 years agosvp64.py: fix ignored field range
Dmitry Selyutin [Sun, 26 Jun 2022 16:06:12 +0000 (19:06 +0300)]
svp64.py: fix ignored field range

2 years agosvp64.py: drop commented code
Dmitry Selyutin [Sun, 26 Jun 2022 15:59:20 +0000 (18:59 +0300)]
svp64.py: drop commented code

2 years agosvp64.py: fix fsins/fcoss X-FORM
Dmitry Selyutin [Sun, 26 Jun 2022 15:42:23 +0000 (18:42 +0300)]
svp64.py: fix fsins/fcoss X-FORM

2 years agoagain fix number of arguments to svremap,
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 09:27:04 +0000 (10:27 +0100)]
again fix number of arguments to svremap,
test_caller_svp64_ldst.py

2 years agowhitespace
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 09:23:49 +0000 (10:23 +0100)]
whitespace

2 years agotest_caller_svstate.py: end-of-loop condition sets CR.SO not CR.EQ
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:59:39 +0000 (09:59 +0100)]
test_caller_svstate.py: end-of-loop condition sets CR.SO not CR.EQ

2 years agosvp64_matrix.py svremap reduce to 7 args from 8 (again)
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:46:32 +0000 (09:46 +0100)]
svp64_matrix.py svremap reduce to 7 args from 8 (again)

2 years agosvremap only takes 7 args not 8, same as in svp64_fft.py
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:35:17 +0000 (09:35 +0100)]
svremap only takes 7 args not 8, same as in svp64_fft.py
fix in svp64_dct.py

2 years agoone too many arguments to svremap in svp64_fft.py test
Luke Kenneth Casson Leighton [Sun, 26 Jun 2022 08:24:46 +0000 (09:24 +0100)]
one too many arguments to svremap in svp64_fft.py test