i965: Support dmabuf import with modifiers

Add support for createImageFromDmaBufs2, adding a modifier to the
original, and allow importing CCS resources with auxiliary data from
dmabufs.

v2: avoid DRIimageExtension version bump, pass single modifier to
    createImageFromDmaBufs2.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Improve same-buffer restriction for imports

Intel hardware requires that all planes of an image come from the same
buffer, which is currently implemented by testing that all FDs are
numerically the same.

However, when going through a winsys (e.g.) or anything which transits
FDs individually, the FDs may be different even if the underlying buffer
is the same.

Instead of checking the FDs for equality, we must check if they actually
point to the same buffer (Jason).

Reviewed-by: Varad Gautam <varad.gautam@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Allocate tile aligned height

This patch shouldn't actually do anything because the libdrm function
should already do this alignment. However, it preps us for a future
patch where we add in the CCS AUX size, and in the process it serves as
a good place to find bisectable issues if libdrm or kernel does
something incorrectly.

v2: Do proper alignment for X tiling, and make sure non-tiled case is
handled (Jason)
v3: Rebase (Daniel)

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Move fallback size assignment out of bufmgr

The bufmgr took a mandatory size argument, which would only be used if
the kernel size query failed, i.e. an older kernel. It didn't actually
check that the BO size was sufficient for use.

Pull the check out of the bufmgr, and actually check that the BO is
sufficiently-sized for our import one level up. This also resolves a
chicken/egg we have when importing bufers without explicit modifiers,
namely that we need the tiling mode to calculate the size, but we need
the BO imported to query the tiling mode.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Invert image modifier/tiling inference

When allocating images, we record a tiling mode and then work backwards
to infer the modifier. Unfortunately this is the wrong way around, since
it is a one:many mapping (e.g. TILING_Y can be plain Y-tiling, or
Y-tiling with CCS).

Invert the mapping, so we record a modifier first and then map this to a
tiling mode.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

egl/dri2: Avoid sign extension when building modifier

Since the EGL attributes are signed integers, a straight OR would
also perform sign extension,

Fixes: 6f10e7c37a ("egl/dri2: Create EGLImages with dmabuf modifiers")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i915g: Add blitter_context argument.

Fix build error.

  CC       i915_surface.lo
i915_surface.c:108:63: error: too few arguments to function call, expected 4, have 3
   util_blitter_default_src_texture(&src_templ, src, src_level);
   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~                           ^
../../../../src/gallium/auxiliary/util/u_blitter.h:271:1: note: 'util_blitter_default_src_texture' declared here
void util_blitter_default_src_texture(struct blitter_context *blitter,
^

Fixes: a893c9169733 ("gallium/u_blitter: use 2D_ARRAY for cubemap blits if possible")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101340
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

etnaviv: flush resource when binding as sampler view

As TS is also allowed on sampler resources, we need to make sure to resolve
to self when binding the resource as a texture, to avoid stale content
being sampled.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

etnaviv: don't flush resource to self without TS

A resolve to self is only necessary if the resource is fast cleared, so
there is never a need to do so if there is no TS allocated.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: upgrade DISCARD_RANGE to DISCARD_WHOLE_RESOURCE if possible

Stolen from VC4. As we don't do any fancy reallocation tricks yet, it's
possible to upgrade also coherent mappings and shared resources.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: simplify transfer tiling handling

There is no need to special case compressed resources, as they are already
marked as linear on allocation. With that out of the way, there is room to
cut down on the number of if clauses used.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: don't read back resource if transfer discards contents

Reduces bandwidth usage of transfers which discard the buffer contents,
as well as skipping unnecessary command stream flushes and CPU/GPU
synchronization.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: honor PIPE_TRANSFER_UNSYNCHRONIZED flag

This gets rid of quite a bit of CPU/GPU sync on frequent vertex buffer
uploads and I haven't seen any of the issues mentioned in the comment,
so this one seems stale.

Ignore the flag if there exists a temporary resource, as those ones are
never busy.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

etnaviv: slim down resource waiting

cpu_prep() already does all the required waiting, so the only thing that
needs to be done is flushing the commandstream, if a GPU write is pending.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>

glsl: Fix gl_shader_stage enum unsigned comparison

Replace -1 with MESA_SHADER_NONE enum value to fix sign related warning:

external/mesa3d/src/compiler/glsl/link_varyings.cpp:1415:25: warning: comparison of constant -1 with expression of type 'gl_shader_stage' is always true [-Wtautological-constant-out-of-range-compare]
        (consumer_stage != -1 && consumer_stage != MESA_SHADER_FRAGMENT))) {
         ~~~~~~~~~~~~~~ ^  ~~

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>

Android: vulkan: fix build error due to extra )

Commit 621b3410f5f8 ("util/vulkan: Move Vulkan utilities to
src/vulkan/util") broke the Android build with the following error:

build/core/binary.mk:1427: error: external/mesa3d/src/vulkan/Android.mk: libmesa_vulkan_util: Unused source files: util/vk_util.h).

Fixes: 621b3410f5f8 ("util/vulkan: Move Vulkan utilities to src/vulkan/util")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Rob Herring <robh@kernel.org>

Fix glcpp test expectations

With commit f7741985be0234 we have changed some preprocessor
error messages and warnings. Adapt related glcpp tests
expectations accordingly.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101336
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

util: make set's deleted_key_value declaration consistent with hash table one

This also silences following clang warnings:
no previous extern declaration for non-static variable 'deleted_key' [-Werror,-Wmissing-variable-declarations]
const void *deleted_key = &deleted_key_value;
            ^
no previous extern declaration for non-static variable 'deleted_key_value'
      [-Werror,-Wmissing-variable-declarations]
uint32_t deleted_key_value;
         ^

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965: Delete intel_resolve_map

Now that we've moved over to the new array mechanism, it's no longer
needed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965: Use the new tracking mechanism for HiZ

This is similar to the previous commit only for HiZ.  For HiZ, apart
from everything looking different, there is really only one functional
change:  We now track the ISL_AUX_STATE_COMPRESSED_NO_CLEAR state.
Previously, if you rendered to a resolved slice of the miptree and then
did a fast-clear with a different clear color, that slice would get
resolved even though it hadn't been fast-cleared.  Now that we can track
COMPRESSED_NO_CLEAR, we know that it doesn't have any blocks in the
"clear" state so we can skip the resolve.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Make level_has_hiz take a const miptree

Acked-by: Chad Versace <chadversary@chromium.org>

i965: Wholesale replace the color resolve tracking code

This commit reworks the resolve tracking for CCS and MCS to use the new
isl_aux_state enum.  This should provide much more accurate and easy to
reason about tracking.  In order to understand, for instance, the
intel_miptree_prepare_ccs_access function, one only has to go look at
the giant comment for the isl_aux_state enum and follow the arrows.
Unfortunately, there's no good way to split this up without making a
real mess so there are a bunch of changes in here:

 1) We now do partial resolves.  I really have no idea how this ever
    worked before.  So far as I can tell, the only time the old code
    ever did a partial resolve was when it was using CCS_D where a
    partial resolve and a full resolve are the same thing.

 2) We are now tracking 4 states instead of 3 for CCS_E.  In particular,
    we distinguish between compressed with clear and compressed without
    clear.  The end result is that you will never get two partial
    resolves in a row.

 3) The texture view rules are now more correct.  Previously, we would
    only bail if compression was not supported by the destination
    format.  However, this is not actually correct.  Not all format
    pairs are supported for texture views with CCS even if both support
    CCS individually.  Fortunately, ISL has a helper for this.

 4) We are no longer using intel_resolve_map for tracking aux state but
    are instead using a simple array of enum isl_aux_state indexed by
    level and layer.  This is because, now that we're tracking 4
    different states, it's no longer clear which should be the "default"
    and array lookups are faster than linked list searches.

 5) The new code is very assert-happy.  Incorrect transitions will now
    get caught by assertions rather than by rendering corruption.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965: Delete most of the old resolve interface

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965: Use the new get/set_aux_state functions for color clears

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965: Move blorp to the new resolve functions

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Chad Versace <chadversary@chromium.org>

i965: Move depth to the new resolve functions

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Move images to the new resolve functions

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Move framebuffer fetch to the new resolve functions

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Remove an unneeded render_cache_set_check_flush

This is only needed to fix rendering corruptions caused by not flushing
after doing a resolve operation.  The resolve now does all the needed
flushing so this is unnecessary.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Move color rendering to the new resolve functions

This also removes an unneeded brw_render_cache_set_check_flush() call.
We were calling it in the case where the surface got resolved to satisfy
the flushing requirements around resolves.  However, blorp now does this
itself, so the extra is just redundant.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Move texturing to the new resolve functions

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Use the new resolve function for several simple cases

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Add new entrypoints for resolve management

This commit adds a new unified interface for doing resolves.  The basic
format is that, prior to any surface access such as texturing or
rendering, you call intel_miptree_prepare_access.  If the surface was
written, you call intel_miptree_finish_write.  These two functions take
parameters which tell them whether or not auxiliary compression and fast
clears are supported on the surface.  Later commits will add wrappers
around these two functions for texturing, rendering, etc.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add an enum for describing auxiliary compression state

This enum describes all of the states that a auxiliary compressed
surface can have.  All of the states as well as normative language for
referring to each of the compression operations is provided in the
truly colossal comment for the new isl_aux_state enum.  There is also
a diagram showing how surfaces move between the different states.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Combine render target resolve code

We have two different bits of resolve code for render targets: one in
brw_draw where it's always been and one in brw_context to deal with sRGB
on gen9.  Let's pull them together.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Be a bit more conservative about certain resolves

There are several places where we were resolving the entire miptree
when we really only needed to resolve a single slice.  Let's avoid the
unneeded resolving.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Move MCS allocation earlier for clears

This way it happens before we call get_aux_state.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Refactor do_single_blorp_clear

Previously, we had two checks for can_fast_clear and a tiny bit of
shared code in between.  This commit pulls all of the fast clear code
together and duplicates the tiny bit that declares some surface structs
and calls blorp_surf_for_miptree.  The duplication is no real loss and
we're about to change the two in slightly different ways.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/blorp: Take an explicit fast clear op in resolve_color

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Move color resolve on map to intel_miptree_map

None of the other methods such as blit work with CCS either so we need
to do the resolve for all maps.  This change also makes us only resolve
the one slice we're mapping and not the entire image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Inline renderbuffer_att_set_needs_depth_resolve

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Get rid of intel_renderbuffer_resolve_*

There is exactly one caller so it's a bit pointless to have all of this
plumbing.  Just inline it at the one place it's used.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Refactor intel_miptree_resolve_color

The new version now takes a range of levels as well as a range of
layers.  It should also be a tiny bit faster because it only walks the
resolve_map list once instead of once per layer.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/miptree: Clean up the depth resolve helpers a little

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965/surface_state: Images can't handle CCS at all

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

i965: Mark depth surfaces as needing a HiZ resolve after blitting

Cc: "17.0 17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chadversary@chromium.org>

st_glsl_to_tgsi: cleanup variable storage search.

I forgot to put the cleanup in earlier.

Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/main: fix gl_buffer_index enum comparison

For clang, enums are unsigned by default and gives the following warning:

external/mesa3d/src/mesa/main/buffers.c:764:21: warning: comparison of constant -1 with expression of type 'gl_buffer_index' is always false [-Wtautological-constant-out-of-range-compare]
      if (srcBuffer == -1) {
          ~~~~~~~~~ ^  ~~

Replace -1 with an enum value to fix this.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

glsl: fix bounds check in blob_overwrite_bytes

clang gives a warning in blob_overwrite_bytes because offset type is
size_t which is unsigned:

src/compiler/glsl/blob.c:110:15: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare]
   if (offset < 0 || blob->size - offset < to_write)
       ~~~~~~ ^ ~

Remove the less than 0 check to fix this.

Additionally, if offset is greater than blob->size, the 2nd check would
be false due to unsigned math. Rewrite the check to avoid subtraction.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>

st_glsl_to_tgsi: replace variables tracking list with a hash table

This removes the linear search which is fail when number of variables
goes up to 30000 or so.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st_glsl_to_tgsi: rewrite rename registers to use array fully.

Instead of having to search the whole array, just use the whole
thing and store a valid bit in there with the rename.

Removes this from the profile on some of the fp64 tests

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st_glsl_to_tgsi: bump index back up to 32-bit

with some of the fp64 emulation, we are seeing shaders coming in with
> 32K temps, they go out with 40 or so used, but while doing register
renumber we need to store a lot of them.

So bump this fields back up to 32-bit.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

util/u_queue: fix a use-before-initialization race for queue->threads

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac/nir: remove another unused variable

Declared by each loop already.
Trivial.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>

radv/meta: remove an unused variable

Trivial.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: convert several ifs to a switch

Also solve "outinfo may be used uninitialized" warning by putting in an
unreachable().

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: mark some arguments const

Most functions are only inspecting nir, so nir related arguments can be
marked const. Some more can be done if/when some nir changes are
accepted.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: Use libdrm to get chipset name

v2: Add a func pointer to radeon_winsys to support radeon later.

Change-Id: I614ea71424f9e5c97e4ae68654315d28c89eaa5f
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

util: Add extern c to u_dynarray.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Delete nir_array.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Port to u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

nir: Remove unused include

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Port nir_array functionality to u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Remove unused includes and convert to lower-case memory ops

Also, prepare for the next commit by correcting some coding style
changes. This should be all non-functional changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

util: Move u_dynarray to src/util

This will be used as the basis for unification

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

gallium: Add missing includes

These will need to be in place to avoid regressions when
removing these includes from the u_dynarray

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

radeonsi: update clip_regs on shader state changes only when it's needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: precompute some fields for PA_CL_VS_OUT_CNTL in si_shader_selector

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add a new helper si_get_vs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: isolate real framebuffer changes from the decompression passes (v3)

When a stencil buffer is part of the framebuffer state, it is
decompressed but because it's bindless, all draw calls set
stencil_dirty_level_mask to 1.

v2: Marek - set the flags outside the loop
          - also clear and set framebuffer.do_update_surf_dirtiness there
          - do it in the DB->CB copy path too
v3: Marek - save and restore the do_update_surf_dirtiness flag

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: do EarlyCSEMemSSA LLVM pass

so that LLVM IR looks like CSE has been run on it. It's also recommended
by the instruction combining pass.

This also fixes:
- GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 (crash)
- piglit/spec/arb_shader_ballot/execution/fs-readFirstInvocation-uint-loop (fail)

The code size decrease is positive, the register usage isn't. There is
a decrease in VGPR spilling for Tomb Raider, but increase in DiRT Showdown
and GRID Autosport.

EarlyCSEMemSSA has a -0.01% change in code size compared EarlyCSE.

SGPRS: 1935420 -> 1938076 (0.14 %)
VGPRS: 1645504 -> 1645988 (0.03 %)
Spilled SGPRs: 2493 -> 2651 (6.34 %)
Spilled VGPRs: 107 -> 115 (7.48 %)
Private memory VGPRs: 1332 -> 1332 (0.00 %)
Scratch size: 1512 -> 1516 (0.26 %) dwords per thread
Code Size: 61981592 -> 61890012 (-0.15 %) bytes
Max Waves: 371847 -> 371798 (-0.01 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove 8 bytes from si_shader_key

We can use a union in si_shader_key::mono.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move PSIZE and CLIPDIST unique IO indices after GENERIC

Heaven LDS usage for LS+HS is below. The masks are "outputs_written"
for LS and HS. Note that 32K is the maximum size.

Before:
  heaven_x64: ls=1f1 tcs=1f1, lds=32K
  heaven_x64: ls=31 tcs=31, lds=24K
  heaven_x64: ls=71 tcs=71, lds=28K

After:
  heaven_x64: ls=3f tcs=3f, lds=24K
  heaven_x64: ls=7 tcs=7, lds=13K
  heaven_x64: ls=f tcs=f, lds=17K

All other apps have a similar decrease in LDS usage, because
the "outputs_written" masks are similar. Also, most apps don't write
POSITION in these shader stages, so there is room for improvement.
(tight per-component input/output packing might help even more)

It's unknown whether this improves performance.

Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

svga: Always set the alpha value to 1 when sampling using an XRGB view

If the XRGB view is sampling from an ARGB svga format, change
PIPE_SWIZZLE_W to PIPE_SWIZZLE_1 for all channels.
Previously we unconditionally set PIPE_SWIZZLE_1 on the alpha channel which
could be both insufficient and incorrect.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Fix imported surface view creation

When deciding to create a view with or without an alpha channel we need to
look at the SVGA3D format and not the PIPE format.

This fixes the glx-tfp piglit test for dri3/xa.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Set alpha to 1 for non-alpha views

Gallium RGB textures may be backed by imported ARGB svga3d surfaces. In those
and similar cases we need to set the alpha value to 1 when sampling.

Fixes piglit glx::glx-tfp

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: Allow format differences in 16-bit RGBA surface sharing

For the purpose of surface sharing, treat SVGA3D_R5G6B5 and
SVGA3D_B5G6R5_UNORM as identical formats.
This fixes the following piglit tests with dri3/xa:

glx@glx-visuals-depth -pixmap
glx@glx-visuals-stencil -pixmap

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Deepak Singh Rawat <drawat@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

dri/vmwgfx: Disable a couple of glx extensions also for Ubuntu unity / compiz

It appears like the GLX_EXT_buffer_age extension also prevents Compiz /
Ubuntu Unity from performing partial buffer swaps when it otherwise
feels like doing so. So try to get them back again. We also disable
GLX_OML_sync_control since it appears it had a favourable impact on
gnome-shell.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>

dri: Turn of a couple of glx extensions for gnome-shell on vmwgfx.

Increases performance on vmwgfx since we're avoiding full buffer damage and
since we can't sync to vertical retrace anyway.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/dri: Allow gallium drivers to turn off two GLX extensions

Allow gallium drivers to turn off GLX_EXT_buffer_age and
GLX_OML_sync_control if needed, using driconf.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

dri: Optionally turn off a couple of GLX extensions based on driconf options

With GLX_EXT_buffer_age turned on, gnome-shell will use full-screen damage
with GLX, which severely hurts performance with architectures that emulate
page-flips with copies. Like vmware. We would like to be able to turn off that
extension. Similarly, typically the GLX_OML_sync_control doesn't make much
sense on a virtual architecture since we don't really sync to the host's
vertical retrace. We'd like to be able to turn it off as well.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/dri: Allow dri users to query also driver options

There will be situations where we want to control, for example, the
GLX behaviour based on applications and drivers. So allow DRI users access
to the driver options.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: clean up decompress blend state names

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: clean up a misleading statement from the old days

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE

It's always good to have fewer decompress blits.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable TC-compatible stencil compression on VI

Most things are in place. Ideally we won't see decompress blits for stencil
anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: don't keep framebuffer state in st_context

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: cache pipe_surface for GL_FRAMEBUFFER_SRGB changes

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: use gl_driver_flags::NewFramebufferSRGB

also call st_init_driver_flags when st_context is initialized.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: add gl_driver_flags::NewFramebufferSRGB

_NEW_BUFFERS updates too much stuff.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: prevent a race when the previous shader's main part is missing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: wait for main part compilation of 1st shaders of merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix LS scratch buffer support without TCS for GFX9

LS is merged into TCS. If there is no TCS, LS is merged into fixed-func
TCS. The problem is the fixed-func TCS was ignored by scratch update
functions, so LS didn't have the scratch buffer set up.

Note that Mesa 17.1 doesn't have merged shaders.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move streamout state update out of si_update_shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove dead code in declare_input_fs

Colors are interpolated in the PS prolog. This was never used.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move handling of DBG_NO_OPT_VARIANT into si_shader_selector_key

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use a compiler queue with a low priority for optimized shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

util/u_queue: add an option to set the minimum thread priority

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: decrease the number of compiler threads to num CPUs - 1

Reserve one core for other things (like draw calls).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: drop unfinished shader compilations when destroying shaders

If we enqueue too many jobs and destroy the GL context, it may take
several seconds before the jobs finish. Just drop them instead.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>