mesa.git
5 years agoaco: Introduce vgpr_limit to keep track of available VGPRs.
Timur Kristóf [Thu, 24 Oct 2019 15:34:37 +0000 (17:34 +0200)]
aco: Introduce vgpr_limit to keep track of available VGPRs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: Implement subgroup shuffle in GFX10 wave64 mode.
Timur Kristóf [Sat, 21 Sep 2019 16:03:56 +0000 (18:03 +0200)]
aco: Implement subgroup shuffle in GFX10 wave64 mode.

Previously subgroup shuffle was implemented using the bpermute
instruction, which only works accross half-waves, so by itself it's
not suitable for implementing subgroup shuffle when the shader is
running in wave64 mode.

This commit adds a trick using shared VGPRs that allows to implement
subgroup shuffle still relatively effectively in this mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: Remove dead code in reduction lowering.
Rhys Perry [Thu, 12 Sep 2019 19:04:20 +0000 (20:04 +0100)]
aco: Remove dead code in reduction lowering.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: Fix reductions on GFX10.
Rhys Perry [Thu, 12 Sep 2019 18:28:52 +0000 (19:28 +0100)]
aco: Fix reductions on GFX10.

Fixes p_reduce (all cluster sizes), p_inclusive_scan and p_exclusive_scan
with all reduction operations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoloader: default to iris for all future PCI IDs
Eric Engestrom [Sat, 5 Oct 2019 21:30:51 +0000 (22:30 +0100)]
loader: default to iris for all future PCI IDs

The existing "fallback" code didn't actually do anything, so this
removes it, and instead we just always fallback to `iris` for future
PCI IDs.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoanv: add a couple printflike() annotations
Eric Engestrom [Thu, 24 Oct 2019 12:29:37 +0000 (13:29 +0100)]
anv: add a couple printflike() annotations

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agost/mesa: lower global vars to local after lowering clip
Erik Faye-Lund [Mon, 28 Oct 2019 13:02:02 +0000 (14:02 +0100)]
st/mesa: lower global vars to local after lowering clip

When this code was merged, this wasn't necessary because the
state-tracker would do it later anyway. But this recently got changed,
without changing the code that depended on this.

Arguably, this was a mistake in the lowering pass to begin with. Either
way, let's fix it by not assuming that the lowering code gets called
later when it's not needed.

This fixed user-defined clip-planes in Zink.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: eaffdad1082 ("st/mesa: don't lower_global_vars_to_local for VS if there are no dead inputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoiris: Create resource with aux_usage MCS_CCS
Sagar Ghuge [Wed, 18 Sep 2019 20:14:31 +0000 (13:14 -0700)]
iris: Create resource with aux_usage MCS_CCS

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agointel/isl: Support lossless compression with multisamples
Sagar Ghuge [Wed, 18 Sep 2019 19:37:59 +0000 (12:37 -0700)]
intel/isl: Support lossless compression with multisamples

GEN12 adds the ability to losslessly compress each sample plane in a
multisampled buffer that uses MCS compression.

v2: Remove unnecessary assertion (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoiris: Get correct resource aux usage for copy
Sagar Ghuge [Fri, 20 Sep 2019 21:05:58 +0000 (14:05 -0700)]
iris: Get correct resource aux usage for copy

Add case for MCS_CCS so that we get the correct aux usage while copy
operation.

v2: Fix commit subject (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agointel/blorp: Use isl_aux_usage_has_mcs instead of comparing
Sagar Ghuge [Thu, 10 Oct 2019 17:40:17 +0000 (10:40 -0700)]
intel/blorp: Use isl_aux_usage_has_mcs instead of comparing

Depending on MCS_CSS or MCS we can emit blorp blit shaders.

As we support MCS_CSS and MCS, it makes sense to use
isl_aux_usage_has_mcs function.

v2: Fix commit message (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoiris: Define MCS_CCS state transitions and usages
Sagar Ghuge [Wed, 18 Sep 2019 20:15:47 +0000 (13:15 -0700)]
iris: Define MCS_CCS state transitions and usages

v2: 1) Fix assertion check (Nanley Chery)
    2) Correct commit subject (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agoiris: Initialize CCS to fast clear while using with MCS
Sagar Ghuge [Thu, 19 Sep 2019 15:13:15 +0000 (08:13 -0700)]
iris: Initialize CCS to fast clear while using with MCS

v2: Explain Bsepc quotes properly (Nanley Chery)

v3: 1) Fix comment format (Nanley Chery)
    2) Fix typo in comment (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agointel/isl: Don't reconfigure aux surfaces for MCS
Sagar Ghuge [Thu, 19 Sep 2019 15:20:34 +0000 (08:20 -0700)]
intel/isl: Don't reconfigure aux surfaces for MCS

If aux for MCS is already configured, don't configure again.

v2: Fix missing period in commit message (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
5 years agozink: emulate optional depth-formats
Erik Faye-Lund [Wed, 23 Oct 2019 09:59:03 +0000 (11:59 +0200)]
zink: emulate optional depth-formats

The Vulkan spec says that an implementation has to support one of
VK_FORMAT_X8_D24_UNORM_PACK32 and VK_FORMAT_D32_SFLOAT, as well of
one of VK_FORMAT_D24_UNORM_S8_UINT and VK_FORMAT_D32_SFLOAT_S8_UINT.

So let's keep track which one is supported of earch pair, and emulate
one on top of the other one.

This won't give the exact result for comparisons, or when mapping and
unmapping the resources. But it's better than flat out failing to create
the resource, and we can fix the map/unmap issue later if needed.

Tested-by: Duncan Hopkins <duncan@thefoundry.co.uk>
5 years agozink: error if VK_KHR_maintenance1 isn't supported
Erik Faye-Lund [Tue, 22 Oct 2019 13:29:55 +0000 (15:29 +0200)]
zink: error if VK_KHR_maintenance1 isn't supported

While we're at it, remove the VK_-prefix from the extension bool; all
extensions have this so it's kinda superfluous.

5 years agoiris: Disallow incomplete resource creation
Nanley Chery [Fri, 2 Aug 2019 22:38:36 +0000 (15:38 -0700)]
iris: Disallow incomplete resource creation

If a modifier specifies an aux, it must be created.

Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Don't leak the resource for unsupported modifier
Nanley Chery [Wed, 25 Sep 2019 19:48:57 +0000 (12:48 -0700)]
iris: Don't leak the resource for unsupported modifier

Make sure the res struct is free'd before returning.

Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Enable HIZ_CCS sampling
Nanley Chery [Wed, 21 Aug 2019 22:23:24 +0000 (15:23 -0700)]
iris: Enable HIZ_CCS sampling

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/blorp: Satisfy clear color rules for HIZ_CCS
Nanley Chery [Wed, 18 Sep 2019 16:44:02 +0000 (09:44 -0700)]
intel/blorp: Satisfy clear color rules for HIZ_CCS

Store the converted depth value into two dwords. Avoids regressing the
piglit test "fbo-depth-array depth-clear", when HIZ_CCS sampling is
enabled in a later commit.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Fix and use HIZ_CCS write through mode
Nanley Chery [Wed, 21 Aug 2019 17:57:29 +0000 (10:57 -0700)]
intel: Fix and use HIZ_CCS write through mode

Write through to the CCS if the surface is used as a texture and can be
sampled by the HW with CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Start using blorp_can_hiz_clear_depth()
Nanley Chery [Mon, 7 Oct 2019 22:52:21 +0000 (15:52 -0700)]
iris: Start using blorp_can_hiz_clear_depth()

Check that the alignment requirements for HIZ_CCS are satisfied by using
this function.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/blorp: Satisfy HIZ_CCS fast-clear alignments
Nanley Chery [Mon, 7 Oct 2019 22:53:44 +0000 (15:53 -0700)]
intel/blorp: Satisfy HIZ_CCS fast-clear alignments

Prevent the piglit test,
amd_vertex_shader_layer-layered-depth-texture-render, from regressing in
in a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Refactor blorp_can_hiz_clear_depth()
Nanley Chery [Mon, 7 Oct 2019 22:48:33 +0000 (15:48 -0700)]
intel: Refactor blorp_can_hiz_clear_depth()

Prepare this function to be used in iris and to handle new Gen12 behavior.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoisl: Add isl_surf_supports_hiz_ccs_wt()
Nanley Chery [Thu, 19 Sep 2019 20:10:24 +0000 (13:10 -0700)]
isl: Add isl_surf_supports_hiz_ccs_wt()

Add a helper to determine if an ISL surface supports the write-through
mode of HIZ_CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Enable HIZ_CCS in depth buffer instructions
Nanley Chery [Fri, 9 Aug 2019 18:08:26 +0000 (11:08 -0700)]
iris: Enable HIZ_CCS in depth buffer instructions

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Define initial HIZ_CCS state and transitions
Nanley Chery [Fri, 9 Aug 2019 00:39:47 +0000 (17:39 -0700)]
iris: Define initial HIZ_CCS state and transitions

Make it match those of HIZ.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Create an unusable secondary aux surface
Nanley Chery [Wed, 7 Aug 2019 23:02:51 +0000 (16:02 -0700)]
iris: Create an unusable secondary aux surface

The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers
store information about two aux buffers. We choose to represent this as
HiZ/MCS being the primary aux surface and the CCS as an secondary/extra
aux surface. This representation has the effect of placing most of the
code that will have to choose between the two aux surfaces around the
aux-map entry points.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Don't guess the aux_usage
Nanley Chery [Thu, 1 Aug 2019 23:49:57 +0000 (16:49 -0700)]
iris: Don't guess the aux_usage

Instead of guessing an aux_usage, then confirming it if the
isl_surf_get_*_surf functions are successful, just call the ISL
functions up-front. This will help us to more easily determine if a
depth buffer supports HIZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/blorp: Treat HIZ_CCS like HiZ
Nanley Chery [Fri, 9 Aug 2019 17:02:50 +0000 (10:02 -0700)]
intel/blorp: Treat HIZ_CCS like HiZ

Allow it in depth buffer instructions but disable it for blits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/blorp: Assert against HiZ in surface states
Nanley Chery [Wed, 21 Aug 2019 23:43:26 +0000 (16:43 -0700)]
intel/blorp: Assert against HiZ in surface states

Avoid unexpected behavior if the caller happens to pass in a HiZ aux
usage.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Support HIZ_CCS in isl_surf_get_ccs_surf
Nanley Chery [Mon, 19 Aug 2019 16:17:26 +0000 (09:17 -0700)]
intel: Support HIZ_CCS in isl_surf_get_ccs_surf

Add an extra aux parameter which will be filled out with CCS if the
first two isl_surf parameters fit the requirements for HiZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoisl: Reduce assertions during aux surf creation
Nanley Chery [Wed, 31 Jul 2019 21:38:29 +0000 (14:38 -0700)]
isl: Reduce assertions during aux surf creation

Return false more often to reduce the burden on the caller.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
Nanley Chery [Thu, 8 Aug 2019 20:40:08 +0000 (13:40 -0700)]
intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+

While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable
Nanley Chery [Sat, 10 Aug 2019 00:18:48 +0000 (17:18 -0700)]
intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/isl: Support HIZ_CCS in emit_depth_stencil_hiz
Jason Ekstrand [Fri, 4 May 2018 16:43:42 +0000 (09:43 -0700)]
intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz

v2. Remove undocumented CCS_E-only mode for depth. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Use RENDER_SURFACE_STATE::DepthStencilResource
Nanley Chery [Sat, 10 Aug 2019 01:04:58 +0000 (18:04 -0700)]
intel: Use RENDER_SURFACE_STATE::DepthStencilResource

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Update alignment restrictions for HiZ surfaces.
Jordan Justen [Wed, 30 May 2018 00:10:47 +0000 (17:10 -0700)]
intel: Update alignment restrictions for HiZ surfaces.

v2 (Nanley):
* Maintain a chronological ordering for HiZ alignments. Suggested by
  Ken.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Clear ::has_hiz when disabling aux
Nanley Chery [Fri, 30 Aug 2019 21:58:54 +0000 (14:58 -0700)]
iris: Clear ::has_hiz when disabling aux

Fixes: 2cddc953cd0 ("iris: some initial HiZ bits")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel/blorp: Disable depth testing for slow depth clears
Nanley Chery [Thu, 15 Aug 2019 17:17:11 +0000 (10:17 -0700)]
intel/blorp: Disable depth testing for slow depth clears

We'll start doing slow depth clears more often on HIZ_CCS buffers in a
future commit. Reduce the performance impact by making them use less
bandwidth.

From the Depth Test section of the BSpec:

   This function is enabled by the Depth Test Enable state variable. If
   enabled, the pixel's ("source") depth value is first computed. After
   computation the pixel's depth value is clamped to the range defined
   by Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state.
   Then the current ("destination") depth buffer value for this pixel is
   read.

and from the Depth Buffer Updates section of the BSpec:

   If depth testing is disabled or the depth test passed, the incoming
   pixel's depth value is written to the Depth Buffer.

Taken together, it's clear that depth testing isn't necessary to perform
a depth buffer clear. Mark Janes and I analyzed this patch with
frameretrace and a depthrange piglit test. I disabled HiZ to ensure we'd
get slow depth clears. We've observed the bandwidth consumption by the
depth buffer access to be cut ~50% on BDW and SKL during depth clears.
On a more graphically intensive workload, the Shadowmapping Sascha
benchmark, I took the average of 3 runs on a BDW with a display
resolution of about 1920x1200 (minus some desktop environment
decorations). I measured a 22.61% FPS improvement when HiZ is disabled.

v2. The BSpec doesn't mandate this behavior, update comment accordingly.
    (Ken)

Fixes: bc4bb5a7e30 ("intel/blorp: Emit more complete DEPTH_STENCIL state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agointel: Enable CCS_E for some formats on Gen12
Nanley Chery [Mon, 25 Mar 2019 21:15:01 +0000 (14:15 -0700)]
intel: Enable CCS_E for some formats on Gen12

In ISL:
   Update the format table to add CCS_E support for some 8BPP formats,
   some 16BPP formats, and R10G10B10A2_UNORM_SRGB.

   In the helper for determining CCS_E support, we return false for some
   16BPP formats because they aren't properly handled in blorp_copy().

In BLORP:
   Allow the new and non-problematic formats for CCS_E-enabled copies.

v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
5 years agoisl: Redefine the CCS layout for Gen12
Nanley Chery [Wed, 20 Mar 2019 01:23:46 +0000 (18:23 -0700)]
isl: Redefine the CCS layout for Gen12

The CCS could be described in a number of ways, but this format was
chosen to minimize churn in the drivers. We may decide on an different
direction in the future.

v2. Increase alignment for display surfaces. (Nanley)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoisl: Add and use isl_tiling_flag_to_enum()
Nanley Chery [Mon, 14 Jan 2019 19:32:21 +0000 (11:32 -0800)]
isl: Add and use isl_tiling_flag_to_enum()

Use a helper that will automatically handle Gen12's CCS tiling when
creating a CCS isl_surf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoiris: Allow for non-Y-tiled aux allocation
Nanley Chery [Mon, 12 Aug 2019 22:41:11 +0000 (15:41 -0700)]
iris: Allow for non-Y-tiled aux allocation

The Gen12 CCS is not Y-tiled.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoisl/drm: Map HiZ and CCS tilings to Y
Nanley Chery [Wed, 27 Mar 2019 21:40:58 +0000 (14:40 -0700)]
isl/drm: Map HiZ and CCS tilings to Y

In the function which translates ISL tilings to i915 tilings, map ISL's
HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/isl: Update surf_fill_state for gen12
Jason Ekstrand [Fri, 4 May 2018 16:44:24 +0000 (09:44 -0700)]
intel/isl: Update surf_fill_state for gen12

v2 (Nanley):
* Avoid driver churn for now.
* Include some media compression changes.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/isl/fill_state: Separate aux_mode handling from aux_surf
Jason Ekstrand [Fri, 4 May 2018 16:34:52 +0000 (09:34 -0700)]
intel/isl/fill_state: Separate aux_mode handling from aux_surf

v2. Avoid driver churn for now. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/isl: Add new aux modes available on gen12
Jason Ekstrand [Fri, 4 May 2018 16:43:01 +0000 (09:43 -0700)]
intel/isl: Add new aux modes available on gen12

v2. Add media compression. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoi965/miptree: Avoid -Wswitch for the Gen12 aux modes
Nanley Chery [Fri, 27 Sep 2019 00:23:33 +0000 (17:23 -0700)]
i965/miptree: Avoid -Wswitch for the Gen12 aux modes

Avoid the compiler warnings for the new enums that will be introduced in
a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoanv/private: Modify aux slice helpers for Gen12 CCS
Nanley Chery [Fri, 13 Sep 2019 21:18:42 +0000 (14:18 -0700)]
anv/private: Modify aux slice helpers for Gen12 CCS

The isl_surf structs for Gen12's CCS won't describe how many slices in
the main surface can be compressed. All slices will be compressable if
CCS is enabled, so lookup the main surface's logical dimension.

v2. Add a space before a `?`. (Jordan)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/blorp: Don't assert aux slices match main slices
Nanley Chery [Fri, 30 Aug 2019 21:16:54 +0000 (14:16 -0700)]
intel/blorp: Don't assert aux slices match main slices

This isn't accurate enough for HiZ which can have a discontiguous range
of supported aux slices. This also won't work with the plan to represent
Gen12 CCS as a single slice surface.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/blorp: Use surf instead of aux_surf for image dimensions
Jason Ekstrand [Tue, 15 May 2018 22:57:39 +0000 (15:57 -0700)]
intel/blorp: Use surf instead of aux_surf for image dimensions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/blorp: Halve the Gen12 fast-clear/resolve rectangle
Nanley Chery [Thu, 9 May 2019 23:38:12 +0000 (16:38 -0700)]
intel/blorp: Halve the Gen12 fast-clear/resolve rectangle

Update their dimensions according to the Bspec.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agointel/blorp/gen12: Set FWCC when storing the clear color.
Rafael Antognolli [Wed, 24 Apr 2019 20:05:20 +0000 (13:05 -0700)]
intel/blorp/gen12: Set FWCC when storing the clear color.

From "Render Target Fast Clear" description for Gen12:

   "SW must store clear color using MI_STORE_DATA_IMM with
   ForceWriteCompletionCheck bit set."

From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):

   "Following the last write from this command, Command Streamer
   will wait for all previous writes are completed and in global
   observable domain before moving to next command."

We use 4 SDIs to store the clear color (one per channel). From the
description, it looks to me that setting that flag only on the last SDI
should be enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoisl: Round up some pitches to 512B for Gen12's CCS
Nanley Chery [Tue, 23 Apr 2019 22:28:18 +0000 (15:28 -0700)]
isl: Round up some pitches to 512B for Gen12's CCS

Gen12's CCS requires that the main surface have a pitch aligned to 512B.

v2. Provide a BSpec citation. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Don't assume CCS_E includes CCS_D
Nanley Chery [Tue, 17 Sep 2019 16:16:12 +0000 (09:16 -0700)]
iris: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoanv/cmd_buffer: Don't assume CCS_E includes CCS_D
Nanley Chery [Tue, 17 Sep 2019 16:16:12 +0000 (09:16 -0700)]
anv/cmd_buffer: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoanv/image: Disable CCS_D on Gen12+
Nanley Chery [Fri, 14 Sep 2018 18:25:43 +0000 (11:25 -0700)]
anv/image: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoisl: Disable CCS_D on Gen12+
Nanley Chery [Fri, 9 Aug 2019 17:41:38 +0000 (10:41 -0700)]
isl: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

v2. Add BSpec reference. (Sagar)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoiris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+
Nanley Chery [Mon, 23 Sep 2019 18:09:46 +0000 (11:09 -0700)]
iris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoanv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+
Nanley Chery [Mon, 23 Sep 2019 20:32:06 +0000 (13:32 -0700)]
anv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoanv: Properly allocate aux-tracking space for CCS_E
Nanley Chery [Mon, 21 Oct 2019 19:56:00 +0000 (12:56 -0700)]
anv: Properly allocate aux-tracking space for CCS_E

add_aux_state_tracking_buffer() actually checks the aux usage when
determining how many dwords to allocate for state tracking. Move the
function call to the point after the CCS_E aux usage is assigned.

Fixes: de3be618016 ("anv/cmd_buffer: Rework aux tracking")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoanv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
Nanley Chery [Wed, 23 Oct 2019 22:51:56 +0000 (15:51 -0700)]
anv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR

Avoid failing the `info->use_clear_address` assertion in ISL on Gen12+.

Fixes: 6c9f9a82d78 ("intel/genxml,isl: Add gen12 render surface state changes")
Reported-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoanv: Add support for depth bounds testing.
Plamena Manolova [Thu, 24 Oct 2019 20:05:11 +0000 (21:05 +0100)]
anv: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoiris: Add support for depth bounds testing.
Plamena Manolova [Wed, 23 Oct 2019 19:56:45 +0000 (20:56 +0100)]
iris: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agogenxml: Add 3DSTATE_DEPTH_BOUNDS instruction.
Plamena Manolova [Wed, 23 Oct 2019 20:39:02 +0000 (21:39 +0100)]
genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.

In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction
which enables support for depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoglsl: Initialize all fields of ir_variable in constructor
Danylo Piliaiev [Fri, 25 Oct 2019 16:33:08 +0000 (19:33 +0300)]
glsl: Initialize all fields of ir_variable in constructor

Better be safe, even if we could technically avoid this for
some fields.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1999
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoutil: remove LIST_IS_EMPTY macro
Timothy Arceri [Mon, 28 Oct 2019 10:30:51 +0000 (21:30 +1100)]
util: remove LIST_IS_EMPTY macro

Just use the inlined function directly. The new function was introduced
in addcf410.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: rename list_empty() to list_is_empty()
Timothy Arceri [Mon, 28 Oct 2019 10:27:52 +0000 (21:27 +1100)]
util: rename list_empty() to list_is_empty()

This makes it clear that it's a boolean test and not an action
(eg. "empty the list").

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_DEL macro
Timothy Arceri [Sun, 27 Oct 2019 23:11:53 +0000 (10:11 +1100)]
util: remove LIST_DEL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_DELINIT macro
Timothy Arceri [Sun, 27 Oct 2019 23:08:00 +0000 (10:08 +1100)]
util: remove LIST_DELINIT macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_REPLACE macro
Timothy Arceri [Sun, 27 Oct 2019 23:05:45 +0000 (10:05 +1100)]
util: remove LIST_REPLACE macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_ADD macro
Timothy Arceri [Sun, 27 Oct 2019 23:03:21 +0000 (10:03 +1100)]
util: remove LIST_ADD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_ADDTAIL macro
Timothy Arceri [Sun, 27 Oct 2019 22:58:31 +0000 (09:58 +1100)]
util: remove LIST_ADDTAIL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoutil: remove LIST_INITHEAD macro
Timothy Arceri [Sun, 27 Oct 2019 22:49:39 +0000 (09:49 +1100)]
util: remove LIST_INITHEAD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agogitlab-ci: fixup debian tags
Erik Faye-Lund [Mon, 28 Oct 2019 11:02:51 +0000 (12:02 +0100)]
gitlab-ci: fixup debian tags

When resolving a merge-conflict, I accidentally only updated the
ARM64-tag tag. Let's correct this.

Fixes: 3d529c17393 ("gitlab-ci: also build Zink on CI")
5 years agointel/compiler: Fix C++ one definition rule violations
Danylo Piliaiev [Fri, 25 Oct 2019 16:49:43 +0000 (19:49 +0300)]
intel/compiler: Fix C++ one definition rule violations

When building with "-flto" brw::block_data definitions
were colliding.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
5 years agogitlab-ci: also build Zink on CI
Erik Faye-Lund [Tue, 22 Oct 2019 07:08:11 +0000 (09:08 +0200)]
gitlab-ci: also build Zink on CI

This prevents accidentally breaking the driver-build while working on
other drivers.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agozink: simplify gl-to-vulkan lowering
Erik Faye-Lund [Wed, 9 Oct 2019 09:25:50 +0000 (11:25 +0200)]
zink: simplify gl-to-vulkan lowering

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: more complete sampler-dim handling
Erik Faye-Lund [Tue, 8 Oct 2019 09:54:10 +0000 (11:54 +0200)]
zink/spirv: more complete sampler-dim handling

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: fixup scissoring
Erik Faye-Lund [Tue, 8 Oct 2019 09:43:29 +0000 (11:43 +0200)]
zink: fixup scissoring

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: limited uniform buffer size so the limits is not exceeded.
Duncan Hopkins [Thu, 26 Sep 2019 11:25:26 +0000 (12:25 +0100)]
zink: limited uniform buffer size so the limits is not exceeded.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: do not set lineWidth to invalid value
Erik Faye-Lund [Mon, 23 Sep 2019 20:13:50 +0000 (22:13 +0200)]
zink: do not set lineWidth to invalid value

Some implementations don't support the lineWidth-feature, so let's
avoid setting invalid state to them. But since we don't have a fallback
for this, inform the user.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: pass screen to zink_create_gfx_pipeline
Erik Faye-Lund [Mon, 23 Sep 2019 20:11:35 +0000 (22:11 +0200)]
zink: pass screen to zink_create_gfx_pipeline

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: respect ubo buffer alignment requirement
Duncan Hopkins [Thu, 11 Jul 2019 10:51:08 +0000 (11:51 +0100)]
zink: respect ubo buffer alignment requirement

The driver can report a minimum alignment for UBOs, and that can be
larger than 64, which we've currently been using. Let's play ball, and
use the reported value instead.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: fix line-width calculation
Duncan Hopkins [Wed, 10 Jul 2019 13:50:16 +0000 (14:50 +0100)]
zink: fix line-width calculation

There's two things that goes wrong in this code on some drivers:
1. Rounding off the line-width to granularity can push it outside the
   legal range.
2. A granularity of 0.0 results in NaN, because we divide by zero.

So let's make this code a bit more robust.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: fixup return-value
Erik Faye-Lund [Thu, 25 Jul 2019 18:52:10 +0000 (20:52 +0200)]
zink: fixup return-value

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: refactor blitting
Erik Faye-Lund [Wed, 24 Jul 2019 21:18:08 +0000 (23:18 +0200)]
zink: refactor blitting

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: implement resource_from_handle
Erik Faye-Lund [Wed, 24 Jul 2019 15:58:54 +0000 (17:58 +0200)]
zink: implement resource_from_handle

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: use VK_FORMAT_B8G8R8A8_UNORM for PIPE_FORMAT_B8G8R8X8_UNORM
Erik Faye-Lund [Wed, 24 Jul 2019 19:59:04 +0000 (21:59 +0200)]
zink: use VK_FORMAT_B8G8R8A8_UNORM for PIPE_FORMAT_B8G8R8X8_UNORM

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: do not set VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT for non-3D textures
Erik Faye-Lund [Wed, 24 Jul 2019 12:09:11 +0000 (14:09 +0200)]
zink: do not set VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT for non-3D textures

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: alias var0 on tex0 etc instead
Erik Faye-Lund [Tue, 23 Jul 2019 15:55:51 +0000 (17:55 +0200)]
zink/spirv: alias var0 on tex0 etc instead

This fixes Quake3, and is more in line with directx semantics.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: lower two-sided coloring
Erik Faye-Lund [Thu, 25 Jul 2019 11:50:40 +0000 (13:50 +0200)]
zink: lower two-sided coloring

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: alias generic varyings on non-generic ones
Erik Faye-Lund [Mon, 22 Jul 2019 14:16:40 +0000 (16:16 +0200)]
zink/spirv: alias generic varyings on non-generic ones

This gets rid of the nasty location-allocation hack.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: implement load_front_face
Erik Faye-Lund [Mon, 22 Jul 2019 11:24:14 +0000 (13:24 +0200)]
zink/spirv: implement load_front_face

We're now adding interface-types during code-emitting, so we need to
defer emitting the entry-point. No biggie, spirv_builder is prepares for
this.

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: fixup b2i32
Erik Faye-Lund [Fri, 19 Jul 2019 15:35:27 +0000 (17:35 +0200)]
zink/spirv: fixup b2i32

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink: do not lower bools to float
Erik Faye-Lund [Fri, 19 Jul 2019 15:05:19 +0000 (17:05 +0200)]
zink: do not lower bools to float

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: prepare for 1-bit booleans
Erik Faye-Lund [Fri, 19 Jul 2019 15:04:50 +0000 (17:04 +0200)]
zink/spirv: prepare for 1-bit booleans

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: fixup b2i32 and implement b2f32
Erik Faye-Lund [Fri, 19 Jul 2019 14:53:04 +0000 (16:53 +0200)]
zink/spirv: fixup b2i32 and implement b2f32

Acked-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agozink/spirv: clean up get_[fu]vec_constant
Erik Faye-Lund [Fri, 19 Jul 2019 14:25:21 +0000 (16:25 +0200)]
zink/spirv: clean up get_[fu]vec_constant

Acked-by: Jordan Justen <jordan.l.justen@intel.com>