Tobias Platen [Wed, 10 Nov 2021 17:57:57 +0000 (18:57 +0100)]
test testcase for exception
Tobias Platen [Tue, 9 Nov 2021 19:43:00 +0000 (20:43 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Tue, 9 Nov 2021 19:42:29 +0000 (20:42 +0100)]
test_issuer_mmu.py: add case_5_allsprs
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 17:49:30 +0000 (17:49 +0000)]
add core instruction-issue PriorityPickers
this got more complicated than expected. it should have been dead easy:
* identify each type of ALU (Logical, Shift, Mul)
* create a list per type of ALU of all Function Units providing that Function
* create a PriorityPicker for each type of ALU
* pick one
* shove that into the "issue" of the picked Function Unit.
where that went wrong was nothing to do with issue, it was to do with the
selection of the register files.
a return result from connect_instruction is a dictionary of "enabled"
bits, one per FU, giving permission for that FU to perform read/write
access to regfile ports.
however with the fu_bitdict changing from "continuously-enabled" over
to "single-pulse indicating issue", the read/write ports were no longer
requested.
to fix this, an *additional* dictionary was created: fu_selected, which
has the OR of the FU issue *and* the FU "busy" signal, which will be
HI for the whole time that the FU is active (even including the first
issue cycle: normally busy_o only goes active one cycle *after* issue
is blipped)
thus in theory, although in practice it will not happen, the read/write
ports could be requested immediately the instruction is issued.
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 12:50:32 +0000 (12:50 +0000)]
comments
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 12:49:54 +0000 (12:49 +0000)]
core.py: create a dictionary of lists of Function Units capable of
dealing with a particular instruction (by power_enums Function: ALU, MMU, DIV
LOGICAL etc.)
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 12:38:25 +0000 (12:38 +0000)]
create function core conect_satellite_decoders
just moving code from elaborate to make it clearer
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 00:39:04 +0000 (00:39 +0000)]
add cancel in to alu_ok / alu_valid in LDSTCompUnit
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 00:34:42 +0000 (00:34 +0000)]
rename LDSTCompUnit cancel to canceln (because it is active low)
Luke Kenneth Casson Leighton [Tue, 9 Nov 2021 00:27:05 +0000 (00:27 +0000)]
whoops must remember to do rdmaskn on LDSTCompUnit as well
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 23:54:02 +0000 (23:54 +0000)]
remove unit test that is unfinished
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 23:48:05 +0000 (23:48 +0000)]
shorter way of getting FU busy signals
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 23:42:21 +0000 (23:42 +0000)]
MultiCompUnit fixed to not need rdmask to be sustained indefinitely
only needs to be set on input (when issue is raised)
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 23:38:58 +0000 (23:38 +0000)]
in MultiCompUnit, put rdmaskn into src latch rather than OR in src release
this allows rdmaskn to be set just once rather than left permanently
on. but, it does mean that the internal src register latches end up
having the wrong (previous) output, which then bleed through into
ALUs.
to stop that, the src data latches are all set to zero if the CompUnit
is not busy
Tobias Platen [Mon, 8 Nov 2021 20:02:07 +0000 (21:02 +0100)]
mmu unit test working again
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 16:37:51 +0000 (16:37 +0000)]
remove unused variable
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 16:34:57 +0000 (16:34 +0000)]
code comments
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 16:17:26 +0000 (16:17 +0000)]
comments
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 14:36:09 +0000 (14:36 +0000)]
remove issue_i from core, use i_valid instead to decide when to issue
converting core to Pipeline API
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 14:19:14 +0000 (14:19 +0000)]
move "exception happened" detection from TestIssuer to Core
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 14:14:43 +0000 (14:14 +0000)]
use p.i_valid in core instead of explicit signal ivalid_i
converting core to Pipeline API
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 14:08:05 +0000 (14:08 +0000)]
use Pipeline API o_ready instead of explicit core busy_o signal
converting core.py to Pipeline API
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 13:59:16 +0000 (13:59 +0000)]
convert core.py to Pipeline API, deriving from ControlBase
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 13:45:10 +0000 (13:45 +0000)]
remove unneeded imports
Luke Kenneth Casson Leighton [Mon, 8 Nov 2021 11:12:40 +0000 (11:12 +0000)]
move simple core input and output data to in/out data structures
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 22:39:24 +0000 (22:39 +0000)]
make FSMDivCoreStage properly conform to Stage API
added ispec and ospec functions, no need to explicitly set
self.p_i_data and self.n.o_data because that is the job of the Stage API
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 15:40:17 +0000 (15:40 +0000)]
add hazard vectors to Regfiles
the reason for adding it to Regfiles is because both In-Order and OoO
need global hazard vectors.
in the case of In-Order the hazard vector bits are set directly by the
Issue Engine.
in the case of Out-of-Order the vector bits are set by way of an
amalgamation (Great Big Or Gate) of the columns from the DMs
in either case the vectors are needed, so might as well be added to Regfiles
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 15:17:32 +0000 (15:17 +0000)]
add quick test of regfiles to output rtlil
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 13:45:41 +0000 (13:45 +0000)]
switch over to single-entry (num_rows=1) ReservationStation2 based
MultiCompUnit
this is effectively identical to FunctionUnitBaseSingle behaviour except
that now there is the possibility of increasing the number of rows
(number of "fronts" to the ALU) to 2 or greater
DIV FSM, Trap and SPR as well as LDST have been left alone
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 13:40:33 +0000 (13:40 +0000)]
for some reason mul test cases had not been added to test_issuer
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 12:57:12 +0000 (12:57 +0000)]
adding an FSM-based MultiCompUnit test (does not work yet)
Luke Kenneth Casson Leighton [Sun, 7 Nov 2021 12:29:53 +0000 (12:29 +0000)]
remove some of the uses of wrmask (redundant)
https://bugs.libre-soc.org/show_bug.cgi?id=742
in MultiCompUnit, wrmask is the amalgamation of the incoming "data ok"
signals from an ALU. ALUs are given the *option* to write to registers:
they are not told, "you absolutely have to write to this register"
but of course for Hazard purposes, the MultiCompUnit has to be told
to "hold" off the write until such time as the ALU can determine whether
it has anything to write
it _should_ now be possible for the ReservationStation version of
FunctionUnit to use combinatorial-setting of write data+ok
Tobias Platen [Sat, 6 Nov 2021 14:14:47 +0000 (15:14 +0100)]
update test_issuer_mmu.py testcase, add needed debug outputs
Tobias Platen [Fri, 5 Nov 2021 20:18:53 +0000 (21:18 +0100)]
tlbie, mtspr and mfspr test cases
Tobias Platen [Fri, 5 Nov 2021 19:15:16 +0000 (20:15 +0100)]
add mmu/dcache unit test
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 19:11:28 +0000 (19:11 +0000)]
use ReservationStations2 (disabled for now)
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 19:07:37 +0000 (19:07 +0000)]
write-ok is expected to stay valid *after* being set,
working out what is going on here
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 18:47:36 +0000 (18:47 +0000)]
add name to write pick on core
Luke Kenneth Casson Leighton [Thu, 4 Nov 2021 18:05:33 +0000 (18:05 +0000)]
fix missing naming ready_i -> i_ready
Tobias Platen [Wed, 3 Nov 2021 17:37:35 +0000 (18:37 +0100)]
cleanup fsm
Tobias Platen [Wed, 3 Nov 2021 17:34:57 +0000 (18:34 +0100)]
loadstore.py: add Display statement on SPR change
Tobias Platen [Wed, 3 Nov 2021 16:54:12 +0000 (17:54 +0100)]
add first tlbie test case
Tobias Platen [Tue, 2 Nov 2021 19:44:16 +0000 (20:44 +0100)]
WIP testcase for TLBIE
Tobias Platen [Tue, 2 Nov 2021 19:27:59 +0000 (20:27 +0100)]
mmu fsm: symbols have been renamed
Tobias Platen [Tue, 2 Nov 2021 19:18:52 +0000 (20:18 +0100)]
hack to fix UnusedElaboratables in src/soc/fu/mmu/test/test_pipe_caller.py
Tobias Platen [Tue, 2 Nov 2021 17:27:45 +0000 (18:27 +0100)]
add test_compldst_multi_mmu_fsm.py
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 23:09:35 +0000 (23:09 +0000)]
add beginnings of FunctionUnitBaseMulti
uses ReservationStations, which is where we find that Fan-In and Fan-Out
in ReservationStations is completely broken. deep joy.
Tobias Platen [Mon, 1 Nov 2021 19:14:20 +0000 (20:14 +0100)]
hack: resolve DriverConflict in src/soc/fu/mmu/fsm.py
Tobias Platen [Mon, 1 Nov 2021 17:50:57 +0000 (18:50 +0100)]
test_issuer_dcache.py: cleanup
Luke Kenneth Casson Leighton [Mon, 1 Nov 2021 09:53:13 +0000 (09:53 +0000)]
code comments for core
Tobias Platen [Sat, 30 Oct 2021 11:16:18 +0000 (13:16 +0200)]
update unittest for dcbz
Tobias Platen [Sat, 30 Oct 2021 11:12:54 +0000 (13:12 +0200)]
compldst_multi.py: fix reset on dcbz
Tobias Platen [Sat, 30 Oct 2021 09:43:31 +0000 (11:43 +0200)]
write_vcd - add missing file extension
Tobias Platen [Sat, 30 Oct 2021 09:15:17 +0000 (11:15 +0200)]
loadstore.py: add debug output for dcbz
Tobias Platen [Sat, 30 Oct 2021 09:14:30 +0000 (11:14 +0200)]
update unit test
Tobias Platen [Sat, 30 Oct 2021 09:11:33 +0000 (11:11 +0200)]
compldst_multi.py: handle dcbz
Tobias Platen [Fri, 29 Oct 2021 17:25:43 +0000 (19:25 +0200)]
test_compldst_multi_mmu.py: verify dcbz result, add debug outputs
Tobias Platen [Fri, 29 Oct 2021 16:45:47 +0000 (18:45 +0200)]
fix unittest test_compldst_multi_mmu.py (load now returned byte previously stored)
Tobias Platen [Thu, 28 Oct 2021 18:25:51 +0000 (20:25 +0200)]
test_compldst_multi_mmu.py: use nmigen.back.pysim
Tobias Platen [Thu, 28 Oct 2021 17:20:53 +0000 (19:20 +0200)]
test_compldst_multi_mmu.py: use nmigen.compat.sim
Luke Kenneth Casson Leighton [Sun, 10 Oct 2021 12:26:49 +0000 (13:26 +0100)]
replace PartitionedSignal with SimdSignal
Las Safin [Fri, 8 Oct 2021 17:15:55 +0000 (17:15 +0000)]
nix: Remove outdated comment about license
Luke Kenneth Casson Leighton [Fri, 8 Oct 2021 13:37:01 +0000 (14:37 +0100)]
Merge branch 'pr' from nix-soc
klehman [Thu, 7 Oct 2021 23:21:35 +0000 (19:21 -0400)]
comments for test_runner
klehman [Thu, 7 Oct 2021 15:57:39 +0000 (11:57 -0400)]
added comment to teststate
Tobias Platen [Tue, 5 Oct 2021 16:33:20 +0000 (18:33 +0200)]
cleanup test_compldst_multi_mmu.py
Tobias Platen [Mon, 4 Oct 2021 18:20:29 +0000 (20:20 +0200)]
refactoring test_compldst_multi_mmu.py
Tobias Platen [Mon, 4 Oct 2021 18:04:42 +0000 (20:04 +0200)]
update test_compldst_multi_mmu.py to use pagetables
Tobias Platen [Mon, 4 Oct 2021 17:50:41 +0000 (19:50 +0200)]
move pagetable to external file
Tobias Platen [Mon, 4 Oct 2021 17:22:36 +0000 (19:22 +0200)]
add wishbone driver for test_compldst_multi_mmu.py
Tobias Platen [Sun, 3 Oct 2021 12:35:48 +0000 (14:35 +0200)]
update test_compldst_multi_mmu.py
Tobias Platen [Sun, 3 Oct 2021 12:10:51 +0000 (14:10 +0200)]
src/soc/experiment/compldst_multi.py: update signal names in load()
Tobias Platen [Sun, 3 Oct 2021 11:37:58 +0000 (13:37 +0200)]
use LoadStore1 and DCache in test_compldst_multi_mmu.py
Tobias Platen [Sun, 3 Oct 2021 08:58:00 +0000 (10:58 +0200)]
more cleanup on pimem.py
Tobias Platen [Sun, 3 Oct 2021 08:38:38 +0000 (10:38 +0200)]
whitespace
Tobias Platen [Sun, 3 Oct 2021 08:33:35 +0000 (10:33 +0200)]
remove redunant pi_dcbz
Tobias Platen [Sun, 3 Oct 2021 07:37:15 +0000 (09:37 +0200)]
an extra dcbz parameter in all six places
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 23:46:59 +0000 (00:46 +0100)]
have to remove dcbz from pimem.py entirely
Luke Kenneth Casson Leighton [Sat, 2 Oct 2021 23:39:44 +0000 (00:39 +0100)]
commented-out and disabled the set_dcbz_addr function, it is the wrong
approach.
it is much better to add an extra parameter to set_wr_addr
"dcbz".
this to be added right across all set_wr_addr functions
(6 places)
Tobias Platen [Sat, 2 Oct 2021 14:00:50 +0000 (16:00 +0200)]
dcbz: cleanup
Tobias Platen [Sat, 2 Oct 2021 13:17:31 +0000 (15:17 +0200)]
dcbz symbol rename
Tobias Platen [Sat, 2 Oct 2021 12:50:00 +0000 (14:50 +0200)]
loadstore.py: add function set_dcbz_addr
Tobias Platen [Sat, 2 Oct 2021 12:42:56 +0000 (14:42 +0200)]
update test_dcbz_pi.py test case
Tobias Platen [Sat, 2 Oct 2021 12:17:17 +0000 (14:17 +0200)]
PortInterfaceBase: add dcbz handling
Luke Kenneth Casson Leighton [Fri, 1 Oct 2021 16:54:39 +0000 (17:54 +0100)]
move TestRunner to openpower-isa now that it is part of the Test API
https://bugs.libre-soc.org/show_bug.cgi?id=686
commit
5d5a1807d553985c25bdc8bf4d04aedfecddf34f openpower-isa repo
Tobias Platen [Wed, 29 Sep 2021 17:52:25 +0000 (19:52 +0200)]
compldst_multi.py: pass dcbz to portinterface
Tobias Platen [Wed, 29 Sep 2021 17:03:47 +0000 (19:03 +0200)]
testcase for compldst: wait for address
Tobias Platen [Tue, 28 Sep 2021 18:34:08 +0000 (20:34 +0200)]
rename ra_needed to zero_a
Tobias Platen [Tue, 28 Sep 2021 18:18:33 +0000 (20:18 +0200)]
update testcase for dcbz
Tobias Platen [Tue, 28 Sep 2021 17:49:36 +0000 (19:49 +0200)]
add testcase for dcbz
klehman [Sun, 26 Sep 2021 11:47:12 +0000 (07:47 -0400)]
add a state list for method calling
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 19:41:23 +0000 (20:41 +0100)]
found accidental commenting-out of memory setup in HDLRunner
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 19:28:07 +0000 (20:28 +0100)]
move debug printout to see whats going on for ldst
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 19:20:24 +0000 (20:20 +0100)]
comments
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 19:16:23 +0000 (20:16 +0100)]
Revert "move coresync clock synchronisation into HDLRunner"
This reverts commit
8a51f6944fa6c5185285b0139f5b419fb68aa145.
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 18:03:45 +0000 (19:03 +0100)]
call StateRunner constructor, to add to StateRunner class Factory
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 17:59:23 +0000 (18:59 +0100)]
more TODO comments
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 17:59:15 +0000 (18:59 +0100)]
move coresync clock synchronisation into HDLRunner
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 17:53:23 +0000 (18:53 +0100)]
whoops missed one function which should be a yield (of nothing)
Luke Kenneth Casson Leighton [Sat, 25 Sep 2021 17:51:53 +0000 (18:51 +0100)]
use yield from on StateRunners