util/vk_alloc: Ensure NULL is handled correctly in vk_free

Reviewed-by: Dave Airlie <airlied@redhat.com>

anv/device: Silence a 32-bit warning

nir: Avoid an extra NIR op in integer divide lowering.

NIR bools are ~0 for true, so ((unsigned)a >> 31) != 0 -> ((int)a >> 31).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

vc4: Try compiling our FSes in multithreaded mode on new kernels.

Multithreaded fragment shaders let us hide texturing latency by a
hyperthreading-style switch to another fragment shader.  This gets us up
to 20% framerate improvements on glmark2 tests.

vc4: Add support for ETC1 textures if the kernel is new enough.

The kernel changes for exposing the param have now been merged, so we can
expose it here.

vc4: Fix simulator mode missing-GETPARAM debug info.

The value is 0 since we didn't set it, we wanted to see the param.

vc4: Fix resource leak in register allocation failure path.

CID 1394322

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>

glsl: stub out _mesa_reference_program() in standalone compiler

The follow patch will call this directly from the linker, the
shader cache will also start calling these from the compiler.

st/mesa/r200/i915/i965: move ARB program fields into a union

It's common for games to compile 2000 programs or more so at

32bits x 2000 programs x 22 fields x 2 (at least) stages

This should give us something like 352 kilobytes in savings
once we add some more glsl only fields.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/mesa: stop initialing Instructions and NumInstructions

Since gl_program is now created with rzalloc() they should
already be initialised.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa: make use of ralloc when creating ARB asm gl_program fields

This will allow us to move the ARB asm fields in gl_program into
a union as we will be able call ralloc_free() on the entire struct
when destroying the context.

In this change we switch over to using ralloc for the Instructions,
String and LocalParams fields of gl_program.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa: remove unused Comment field in prog_instruction

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: get num_abos from shader_info rather than gl_linked_shader

This is a step towards freeing gl_linked_shader after linking.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa/glsl: copy num_abos to gl_program

We should be able to free gl_linked_shader after linking in order to
do so we need to switch to getting values from gl_program instead.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: get num_images from shader_info rather than gl_linked_shader

This is a step towards freeing gl_linked_shader after linking.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa/glsl: copy num_images to gl_program

We should be able to free gl_linked_shader after linking in order to
do so we need to switch to getting values from gl_program instead.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

nir: add support for counting AoA uniforms in nir_shader_gather_info()

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: only try print GLSL IR once when using INTEL_DEBUG to dump ir

Since we started releasing GLSL IR after linking the only time we can
print GLSL IR is during linking. When regenerating variants only NIR
will be available.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

anv/descriptor_set: Put the whole state in the state free list

We're not really saving much by just putting the offset in there.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

anv/descriptor_set: Write the state offset in the surface state free list.

When Kristian reworked descriptor set allocation, somehow he forgot to
actually store the offset in the free list.  Somehow, this completely
missed CTS testing until now... This fixes all 2744 of the new
'dEQP-VK.texture.filtering.* tests in the latest CTS.

Cc: "12.0 13.0" <mesa-dev@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

compiler: remove now unused copy_shader_info() declaration

Left over from 4ac66861

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

compiler: include shader_enums.h in shader_info.h

We make use of some enums here.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

swr: [rasterizer core] fix clear with multiple color attachments

Fixes fbo-mrt-alphatest

v2: styling fixes

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

Partial revert "i965: "Fix" aux offsets"

This partially reverts commit 0d241085f723402120b4b47e939fe77020a16d80.

HiZ buffer cannot do this properly now, and it's not required, so remove
it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: "Fix" aux offsets

When 1 BO is used for aux data, it needs to point to the correct offset,
which will not be the BOs offset but instead an offset from the BOs
offset. Since today there are always multiple BOs for aux, this doesn't
actually change anything.

Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/blorp: Handle VK_ATTACHMENT_UNUSED in CmdClearAttachments

From the Vulkan 1.0.29 spec for vkCmdClearAttachments:

   "If the subpass’s depth/stencil attachment is VK_ATTACHMENT_UNUSED,
   then the clear has no effect."

and

   "If colorAttachment is VK_ATTACHMENT_UNUSED then the clear has no
   effect."

I have no idea why it's spec'd this way; it seems very anti-Vulkan to me,
but that's what it says and it's really not much work to support.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

Allocate a null state whenever there is depth/stencil

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv: Set framebuffer to NULL in secondary command buffers

Nothing that is allowed to be called within a secondary now relies on the
framebuffer.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

anv/blorp: Use the new clear_attachments entrypoint for attachment clears

This allows us to re-use the surface states emitted from the Vulkan driver
instead of blorp creating its own.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/blorp: Break the guts of alloc_binding_table into a shared helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv: Bring back anv_cmd_buffer_emit_state_base_address

This reverts most of commit 52904ba85c7e1e3092601e3497bfbc246b00b84a.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add a clear_attachments entrypoint

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add capability to use pre-baked binding tables

When a pre-baked binding table is requested, no binding table is created,
instead the binding table offset (relative to surface state base address)
provided by the user is used verbatim.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add support for vertex shaders

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Use an actual chunk of vertex buffer for the VUE header

We're about to start passing other things in as a sort of "VS header" for
vertex shaders and we need a place to put them.  Since we want the instance
id to be one of them, it makes sense to have one vec4 that's either VUE
header or VS header.  Always uploading some handy zeros makes the code a
bit simpler.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

blorp/exec: Use uint32_t for copying varying data

Some things may not be floats and intel CPUs are known for mangling bits
when a float type is used for copying integers.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Handle NIR clear inputs the same way as blit inputs

By using offsetof() we can ensure that adding fiels to wm_inputs is always
safe as long as we maintain alignment.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Remove NIR support for uniforms

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add a shader type to make keys more unique

Depending on how the driver using blorp implements its shader caching,
there is a small chance of shader collisions due to identical keys between
blit and clear programs.  Adding a small shader type at the top of the key
alleviates this problem.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Make the number of samples an explicit parameter

Previously, we always inferred it from params->dst which meant that
references to params->dst were scattered all throughout the state upload
code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/cmd_buffer: Stop relying on the framebuffer for 3DSTATE_SF on gen7

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv: Rework the way render target surfaces are allocated

This commit moves the allocation and filling out of surface state from
CreateImageView time to BeginRenderPass time.  Instead of allocating the
render target surface state as part of the image view, we allocate it in
the command buffer state at the same time that we set up clears.  For
secondary command buffers, we allocate memory for the surface states in
BeginCommandBuffer but don't fill them out; instead, we use our new
SOL-based memcpy function to copy the surface states from the primary
command buffer.  This allows us to handle secondary command buffers without
the user specifying the framebuffer ahead-of-time.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/cmd_buffer: Expose add_surface_state_reloc as an inline helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/cmd_buffer: Use the surface state alloc helper in null_surface_state

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv: Add a helper for doing buffer copies with nothing but VF and SOL.

This method of doing copies has the advantage of touching very little of
the GPU state.  While it does disable all the shader stages, it doesn't
have to blow away binding tables, viewports, scissors, or any other bits of
dynamic state other than VBO 32 which is already reserved.  All of the
state that it does touch is contained within a pipeline anyway so that's
the only thing that has to be dirtied.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_device

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv/pipeline: Use get_scratch_space/address for compute shaders

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv: Move INTERFACE_DESCRIPTOR_DATA setup to the pipeline

There are a few dynamic bits, namely binding table and sampler addresses,
but most of it is static and really belongs in the pipeline.  It certainly
doesn't belong in flush_compute_descriptor_set.  We'll use the same state
merging trick we use for gen7 DEPTH_STENCIL.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline: Roll genX_pipeline_util.h into genX_pipeline.c

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline: Unify graphics_pipeline_create

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipline: Re-order state emission and make it consistent

This commit makes both gen7 and gen8 pipeline setup emit state packets
in exactly the same order.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Rework the 3DSTATE_VF_TOPOLOGY helper

It gets a new name and moved to genX_pipeline_util.h.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Move 3DSTATE_PS_EXTRA setup into a helper

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Unify 3DSTATE_WM emission

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

intel/genxml: Make 3DSTATE_WM more consistent across gens

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline: Unify 3DSTATE_PS emission

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline/gen7: Properly set 3DSTATE_PS::DualSourceBlendEnable

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

intel/genxml: Make some 3DSTATE_PS fields more consistent

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Make emit_3dstate_sbe safe to call without a FS

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline: Unify 3DSTATE_GS emission

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline/gen8: Set 3DSTATE_GS::InstanceControl

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/genxml: Make some 3DSTATE_GS fields more consistent

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Unify 3DSTATE_VS emission

With this commit, a few fields are now specified on gen7 which weren't
before.  However, the values specified are zero which is the default so the
final hardware packet remains the same.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline/gen8: Enable VS statistics

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

anv/pipeline: Stop claiming to support running without a vertex shader

From the Vulkan spec version 1.0.32 docs for vkCreateGraphicsPipelines:

    The stage member of one element of pStages must be
    VK_SHADER_STAGE_VERTEX_BIT

Since a vertex shader is always required, this hasn't been used since we
deleted meta.  Let's get rid of the complexity.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

intel/genxml: Make some VS/GS fields consistent across gens

We use the names from gen8+

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Get rid of the kernel pointer fields

Now that we have anv_shader_bin, they're completely redundant with other
information we have in the pipeline.  For vertex shaders, we also go
through way too much work to put the offset in one or the other field and
then look at which one we put it in later.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

anv/pipeline: Set correct binding table and sampler counts

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

mesa: if MESA_DEBUG=context, create a debug context

A number of drivers report useful debug/perf information accessible
through GL_ARB_debug_output and with debug contexts (i.e. setting the
GLX_CONTEXT_DEBUG_BIT_ARB flag).  But few applications actually use
the GL_ARB_debug_output extension.

This change lets one set the MESA_DEBUG env var to "context" to force-set
a debug context and report debug/perf messages to stderr (or whatever
file MESA_LOG_FILE is set to).  This is a useful debugging tool.

The small change in st_api_create_context() is needed so that
st_update_debug_callback() gets called to hook up the driver debug
callbacks when ST_CONTEXT_FLAG_DEBUG was not set, but MESA_DEBUG=context.

v2: use %.*s format string instead of allocating temporary buffer.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

u_simple_shaders: try to un-break the Windows build

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: fix a subtle bounds checking corner case with 3-component attributes

I'm also sending out a piglit test, gl-2.0/vertexattribpointer-size-3,
which exposes this corner case.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: reject some 3-component formats as buffer textures

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

st/mesa: swap bytes in the fallback format translation path of GetTexImage

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pixelstore.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

st/mesa: simplify and fix st_GetTexSubImage

By using _mesa_image_address, the code becomes simpler _and_ fixes the bug
that GL_PACK_SKIP_IMAGES was applied even on non-3D textures.

Also, converting a whole slice at a time simplifies the format translation
fallback path.

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pixelstore.

v2: fix a silly mistake during code movement

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

st/mesa: fix SINT <-> UINT conversion during PBO upload / download

This fixes use cases like glReadPixels from an RGBA8I framebuffer into
a PBO with type GL_INT by clamping values appropriately when they fall
outside the range of the destination format.

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

st/mesa: change st_pbo_create_upload_fs to st_pbo_get_upload_fs

For consistency with st_pbo_get_download_fs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

st/mesa: fix ReadPixels into packed formats with PBO

When using the GPU download path, we bind the PBO as a buffer texture,
so call is_format_supported accordingly. On radeonsi, this means that
GPU downloads aren't used for UNSIGNED_SHORT_5_6_5 destinations, for
example.

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

util/blitter: add clamping during SINT <-> UINT blits

Even though glBlitFramebuffer cannot be used for SINT <-> UINT blits, we
still need to handle this type of blit here because it can happen as part
of texture uploads / downloads, e.g. uploading a GL_RGBA8I texture from
GL_UNSIGNED_INT data.

Fixes parts of GL45-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

util/blitter: index texfetch_col shaders by type

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

i965: miptree: prevent potential NULL pointer access

If the mcs buffer allocation fails we might get a NULL pointer. This
was reported by Coverity and should only happen if we run out of
memory.

v2: return failure at the point of allocation (Chris)

CID: 1394290
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/blorp: Use designated initializers in surf_convert_to_single_slice

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

EGL/android: pbuffer implementation

Android path didn't support pbuffer, so add pbuffer support to fix
most failing dEQP and CTS pbuffer test cases.

Patch adds a single buffer config to support pbuffer, and creates
image in getBuffers for pbuffer when surface type is front surface.

The EGL 1.5 spec states that pbuffers have a back buffer but no front
buffer, single-buffered surfaces with no front buffer confuse Mesa;
so we deviate from the spec, following the precedent of Mesa's EGL
X11 platform.

V3: update commit message and code review changes.

Signed-off-by: Liu Zhiquan <zhiquan.liu@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: add missing error-checking to eglReleaseTexImage()

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

i965: Fix KBL typo in string

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Consolidate GEN9 LP definition

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/glk: Add basic Geminilake support

v2: s/bdw/gen; Add the 2x6 config
v3: Add min_ds_entries

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

util: Fix Clang trivial destructor check.

Check for Clang before GCC.

Clang defines __GNUC__ == 4 and __GNUC_MINOR__ == 2 and matches the GCC
check but not the GCC version for trivial destructor.

Fixes: 98ab905af0e0 ("mesa: Define introspection macro to determine
whether a type is trivially destructible.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98526
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

swr: mark color clamping as unsupported

There is no functionality in swr to clamp either vertex or frag colors.
This could be added in swr_shader, at which point these could be
re-enabled.

Fixes arb_color_buffer_float-render

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: always enable adding start/base vertex to gl_VertexId

Fixes gl-3.2-basevertex-vertexid

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: add support for upper-left fragcoord position

Fixes glsl-arb-fragment-coord-conventions.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: make sure that all rendering is finished on shader destroy

Rendering could still be ongoing (or have yet to start) when the shader
is deleted. There's no refcounting on the shader text, so insert a
pipeline stall unconditionally when this happens.

[Note, we should instead introduce a way to attach work to
fences, so that the freeing can be done in the current fence.]

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: disable blending for integer formats

The EXT_texture_integer test says that blending and alphatest should
all be disabled. st/mesa takes care of alphatest already.

Fixes the ext_texture_integer-fbo-blending piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: mark rgb9_e5 as unrenderable

The support in swr requires shaders to output the components as UINTs.
This is not how GL or Gallium work, and since this is not a
required-renderable format, just leave it out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: no support for shader stencil export

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: mark both frag and vert textures read, don't forget about cbs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: fix texture layout for compressed formats

Fixes the texsubimage piglit and lets the copyteximage one get further.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: add archrast generated files to gitignore

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer jitter] don't bother quantizing unused channels

In a BGR10X2 or BGR5X1 situation, there's no need to try to quantize the
X channel - the default will have the proper quantization required.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer memory] fix store tile for 128-bit ymajor tiling

Noticed by inspection.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>