st/glsl: support clamping color outputs in compat for gs/tes

This support requires the driver to be a NIR driver as we use the
NIR lowering pass to do the clamping.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: add tess support to nir_lower_clamp_color_outputs()

This will be used to add compat profile support for higher GL
versions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Fix round64 conversion function

Fix round64 function to handle round to nearest even cases specially
with positive and negative numbers with fraction part 0.5.

v2: 1) Simplify unused bits (Elie Tournier)

Fixes:
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec4
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_double
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

panfrost/ci: Add RK3288 flipflops I don't want to deal with right now

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/ci: Update failures list

A ton of tests were fixed by this series. A few were incorrectly passing
before (QualityError, for instance) and now are explicitly failing. A
few legitimate regressions but overwhelmingly positive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0

Fixes cube map tests due to disagreements between Mesa, dEQP, and the
spec...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>

panfrost/ci: Run full set of mipmap tests

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Advertise support for other 8-bit UNORM formats

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Use pipe_surface->format directly in blitter

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Invert swizzle for rendering

Fixes rendering to e.g. alpha textures.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Honour first_layer...last_layer when sampling

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Use the sampler_view target (not the textures)

u_blitter gets "special treatment" and uses this mechanism to cast
cube maps to 2D textures in order to texelFetch them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/midgard: Assert guard texelFetch against cubemaps

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Zero pixels in any axis is zero pixels total

Multiplication, not addition, so switch the logic operator.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Respect mip level when wallpapering

Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a
mipmap.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/midgard: Fixup NIR texture op

In a vertex shader, a tex op should map to txl, as there *must* be a LOD
given to the hardware (implicitly or explicitly).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Support (non-)seamless cube maps

Identify the seamless cubemap bit and passthrough the Gallium state
rather than setting unconditionally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Merge checksum buffer with main BO

This is similar to the AFBC merge; now all (non-imported) buffers use a
common backing buffer. Reenables checksumming, eliminating a performance
regression.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/decode: Limit MRT blend count

I thought I already fixed this. Maybe that was a dream...? Then again, I
might be dreaming now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Clamp tile coordinates before job submission

Fixes TILE_RANGE_FAULT raised on some tests in
dEQP-GLES3.functional.fbo.blit.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Use dedicated u_blitter context for wallpapers

The main ctx->blitter instance should be reserved for blits originated
from Gallium (like mipmap generation). Since wallpapering is
conceptually different -- wallpaper blits can be triggered by Gallium
blits -- the blitter pipes must be separate to avoid potential u_blitter
recursion.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Sanity check layer

It doesn't make sense to try to render to multiple array elements at
once.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Divide array_size by 6 for cubemaps

Addresses the disparity between Mali and Gallium definitions of
array_size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Use get_texture_address for framebuffer computations

Allows for sharing some code as well as theoretically allowing cubemap
rendering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Merge AFBC slab with BO backing

Rather than tracking AFBC memory "specially", just use the same codepath
as linear and tiled. Less things to mess up, I figure. This allows us to
use the standard setup_slices() call with AFBC resources, allowing
mipmapped AFBC resources.

Unfortunately, we do have to disable AFBC (and checksumming) in the
meantime to avoid functional regressions, as we don't know _a priori_ if
we'll need to access a resource from software (which is not yet hooked
up with AFBC) and we don't yet have routines to switch the layout of a
BO at runtime.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Z/S can't be tiled

As far as we know, Utgard-style tiling only works for color render
targets, not depth/stencil, so ensure we don't try to tile it (rather
than compress or plain old linear) and drive ourselves into a corner.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Enable mipmapping

Now the autogeneration of mipmaps is working (via u_blitter), we can
finally enable mipmaps!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Enable blitting

Now that all the prerequisites breaking u_blitter are fixed, we can
finally hook up panfrost_blit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Allow texelFetch for wallpaper blits

We just implemented the routine; we may as well use it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/midgard: Implement texelFetch (2D only)

txf instructions can result from blits, so handle them rather than
crash. Only works for 2D textures (not even 2D array texture) due to a
register allocation constraint that may not be sorted for a while.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Skip flushes only for wallpapers, not any blit

We need the flush from u_blitter for a normal blit (e.g. for mipmaps);
it's only wallpaper-related blits that are special-cased.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Handle generate_mipmap ourselves

To avoid interference with the wallpaper code, we need to do some state
tracking when generating mipmaps. In particular, we need to mark the
generated layers as invalid before generating the mipmap, so we don't
try to backblit them if they already had content.

Likewise, we need to flush both before and after generating a mipmap
since our usual set_framebuffer_state flushing isn't quite there yet.
Ideally better optimizations would save the flush but I digress.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Disable mipmapping if necessary

If a mipfilter is not set, it's legal to have an incomplete mipmap; we
should handle this accordingly. An "easy way out" is to rig the LOD
clamps.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

intel/blorp: Disable sampler state prefetching on Gen11

Sampler state prefetching is broken on Gen11, and WA_160668216 says
to disable it.  Apparently sampler state prefetching also has basically
zero impact on performance, so we don't need to worry there.

i965, anv, and iris already handle this correctly, but we missed BLORP.
Ideally the kernel should globally disable this by writing SARCHKMD, at
which point we wouldn't have to worry about it.  But let's be defensive
and handle it ourselves too.

v2: separate out from BTP workaround in case we change that eventually

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> [v1]

anv/descriptor_set: Only write texture swizzles if we have an image view

When immutable samplers are set we call write_image_view with a NULL
image view.  This causes issues on IVB where we have to fake texture
swizzling.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110999
Fixes: d2aa65eb18 "anv: Emulate texture swizzle in the shader when..."

virgl: add VIRGL_DEBUG_XFER

When set, do as requested and skip any transfer optimization.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>

virgl: add VIRGL_DEBUG_SYNC

When set, wait after every each flush.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>

virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLE

VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3.  Make some cosmetic
changes as well.

Fixes: a478e56fbd33fa23503b63d41265a1c2f3253ed2
    virgl: Add debug flag to bypass driconf to enable the BGRA tweaks

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>

radv: rename and re-document cache flush flags

SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: set DISABLE_CONSTANT_ENCODE_REG to 1 for Raven2

Ported from RadeonSI, will be emitted for GFX10 too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: clear CMASK layers instead of the whole buffer on GFX8

This reduces the size of fill operations needed to clear CMASK
for layered color textures.

GFX9 unsupported for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: clear FMASK layers instead of the whole buffer on GFX8

This reduces the size of fill operations needed to clear FMASK
for layered color textures.

GFX9 unsupported for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: always initialize levels without DCC as fully expanded

This fixes a rendering issue with RoTR/DXVK.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

i965: leaking of upload-BO with push constants

In case of any enabled VS members from: uses_firstvertex,
uses_baseinstance, uses_drawid, uses_is_indexed_draw
leaks may happens.
Call gen6_upload_push_constants allocates
stage_stat->push_const_bo. It than takes pointer from
push_const_bo to draw_params_bo (in the call
brw_prepare_shader_draw_parameters by brw_upload_data)
and do reference which finally haven't got unreferenced.

Fixes leak:
 136 bytes in 1 blocks are definitely lost in loss record 6 of 13
    at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
    by 0xC2B64B7: bo_alloc_internal (brw_bufmgr.c:596)
    by 0xC2B6748: brw_bo_alloc (brw_bufmgr.c:672)
    by 0xC314BB3: brw_upload_space (intel_upload.c:88)
    by 0xC2EBBC5: gen6_upload_push_constants (gen6_constant_state.c:155)
    by 0xC9E4FA6: gen9_upload_vs_push_constants (genX_state_upload.c:3300)
    by 0xC2E0EDA: check_and_emit_atom (brw_state_upload.c:540)
    by 0xC2E0EDA: brw_upload_pipeline_state (brw_state_upload.c:659)
    by 0xC2E0FF1: brw_upload_render_state (brw_state_upload.c:681)
    by 0xC2C5D2D: brw_draw_single_prim (brw_draw.c:1052)
    by 0xC2C62CB: brw_draw_prims (brw_draw.c:1175)
    by 0xC488AD1: vbo_exec_vtx_flush (vbo_exec_draw.c:386)
    by 0xC485270: vbo_exec_FlushVertices_internal (vbo_exec_api.c:652)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>

docs: update calendar, add news item and link release notes for X.Y.Z

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: fix some typos in 19.0.7 release notes

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: add sha256 checksums for 19.1.1

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit d54dc24d6d6ad9ce4fbebd5f9a69a92633504c40)

docs: add release notes for 19.1.1

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 22eddd8b9d4d905237494c9841e65e4c073ab514)

intel/compiler: silence a warning of using different enum type

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

egl: replace dead vfunc with an error

st/egl used to support eglCreatePbufferFromClientBuffer, but now that
it's gone, any call to it would segfault.

Let's return a nice error instead.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: delete unused vfuncs

Nobody ever uses these, so let's just hard code them instead.

If an EGL driver ever comes around that needs them they're trivial to
re-add.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: drop empty eglfallbacks.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: move eglGetSyncAttrib() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglSwapInterval() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglSurfaceAttrib() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglQuerySurface() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglQueryContext() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglGetConfigAttrib() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglChooseConfig() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

egl: move eglGetConfigs() fallback to eglapi.c

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

freedreno/a5xx: fix batch leak in fd5 blitter path

Fixes: 3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create.
Signed-off-by: Rob Clark <robdclark@chromium.org>

radeonsi: don't set spi_ps_input_* for monolithic shaders

The driver doesn't use these values and ac_rtld has assertions
expecting the value of 0.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: rename and re-document cache flush flags

SMEM and VMEM caches are L0 on gfx10.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: fix AMD_DEBUG=nofmask

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: flatten the switch for DPBB tunables

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

radeonsi: set the calling convention for inlined function calls

otherwise the behavior is undefined

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

radeonsi: refactor si_update_vgt_shader_config

We'll have to extend this at some point, and using a bitfield union in
this way makes it easier to get the right index without excessive
branching.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

amd/rtld: update the ELF representation of LDS symbols

The initial prototype used a processor-specific symbol type, but
feedback suggests that an approach using processor-specific section
name that encodes the alignment analogous to SHN_COMMON symbols is
preferred.

This patch keeps both variants around for now to reduce problems
with LLVM compatibility as we switch branches around.

This also cleans up the error reporting in this function.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/surface: remove addrlib_family_rev_id

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

docs: update calendar, add news item and link release notes for 19.0.7

docs: Add SHA256 sums for 19.0.7

Docs add 19.0.7 release notes

glsl: Don't increase the iteration count when there are no terminators

Incrementing the iteration count was intended to fix an off-by-one error
when the first terminator was superseded by a later terminator.  If
there is no first terminator or later terminator, there is no off-by-one
error.  Incrementing the loop count creates one.  This can be seen in
loops like:

    do {
        if (something) {
            // No breaks or continues here.
        }
    } while (false);

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Abel Briggs <abelbriggs1@hotmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110953
Fixes: 646621c66da ("glsl: make loop unrolling more like the nir unrolling path")

freedreno: Only upload the used part of UBO0 to the constant buffer.

We were pessimistically uploading all of it in case of indirection,
but we can just bump that when we encounter indirection.

total constlen in shared programs: 2529623 -> 2485933 (-1.73%)

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: Stop treating UBO 0 specially in UBO uploading.

ir3_nir_analyze_ubo_ranges() has already told us how much of cb0 we
need to upload (all of it, since it will lower indirect UBO 0 accesses
from load_ubo back to indirection on the constant buffer).

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno: Clamp UBO uploads to the constlen decided by the shader.

If the NIR-level analysis decided to move UBO loads to the constant
file, but the backend decided not to load those constants, we could
upload past the end of constlen.  This is particularly relevant for
pre-a6xx, where we emit a different constlen between bin and render
variants.

(Fix by Rob, commit message by anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>

panfrost: Allow up to 16 UBOs

This is the hardware max, as far as I can tell.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: DRY between shader stage setup

Just a little spring cleanup, extending UBOs to vertex shaders in the
process.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost/midgard: Implement UBO reads

UBOs and uniforms now use a common code path with an explicit `index`
argument passed, enabling UBO reads.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Handle disabled/empty UBOs

Prevents an assert(0) later in this (not so edge) case. We still have to
have a dummy there.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Identify "uniform buffer count" bits

We've known about this for a while, but it was never formally in the
machine header files / decoder, so let's add them in.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Upload UBOs

Now that all the counting is sorted, it's a matter of passing along a
GPU address and going.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Allow for dynamic UBO count

We already uploaded UBOs, but only a fixed number (1) for uniforms;
let's upload as many as we compute we need.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Report UBO count

We look at the highest set bit in the UBO enable mask to work out the
maximum indexable UBO, i.e. the UBO count as we need to report to the
hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Constant buffer refactor

We refactor panfrost_constant_buffer to mirror v3d's constant buffer
handling, to enable UBOs as well as a single set of uniforms.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Replace varyings for point sprites

This doesn't handle Y-flipping, but it's good enough to render the stars
in Neverball.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Track point sprites in fragment shader key

In preparation for lowering point sprites, track them like we track
alpha testing state.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

i965: Move resources lowering after NIR linking

Those either depend on information filled by the NIR linking steps OR
are restricted by those:

- gl_nir_lower_samplers: depends on UniformStorage being set by the
  linker.

- brw_nir_lower_image_load_store: After 6981069fc80 "i965: Ignore
  uniform storage for samplers or images, use binding info" we want
  this pass to happen after gl_nir_lower_samplers.

- gl_nir_lower_buffers: depends on UniformBlocks and
  SharedStorageBlocks being set by the linker.

For the regular GLSL code path, those datastructures are filled
earlier.  For NIR linking code path we need to generate the nir_shader
first then process it -- and currently the processing works with all
shaders together.  So move the passes out of brw_create_nir into its
own function, called by the brwProgramStringNotify and
brw_link_shader().

This patch prepares ground for ARB_gl_spirv, that will make use of NIR
linker.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/nir: Fix copying 64-bit values in uniform storage

The iterator `i` already walks the right amount now that is
incremented by `dmul`, so no need to `* 2`.  Fixes invalid memory
access in upcoming ARB_gl_spirv tests.

Failure bisected by Arcady Goldmints-Orlov.

Fixes: b019fe8a5b6 "glsl/nir: Fix handling of 64-bit values in uniform storage"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl/nir: Fix copying vector constant values

For n_columns == 1, we have a vector which is handled by the else
case.  Fixes invalid memory access in upcoming ARB_gl_spirv tests.

Failure bisected by Arcady Goldmints-Orlov.

Fixes: 81e51b412e9 "nir: Make nir_constant a vector rather than a matrix"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

amd/common: lower bitfield_extract to ubfe/ibfe.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

amd/common: lower bitfield_insert to bfm & bitfield_select

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: introduce lowering of bitfield_insert to bfm and a new opcode bitfield_select.

bitfield_select is defined as:
bitfield_select(mask, base, insert) = (mask & base) | (~mask & insert)
matching the behavior of AMD's BFI instruction.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/algebraic: Use unsigned comparison when lowering bitfield insert/extract

This lets us use the optimization pattern
(('ult', 31, ('iand', b, 31)), False) to remove the
bcsel instruction for code originating in D3D shaders.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/algebraic: Remove unnecessary iand of [iu]bfe and bfm sources

The [iu]bfe and bfm instructions are defined to only use the five
least significant bits.
This optimizes a common pattern from D3D -> SPIR-V translation.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: define behavior of nir_op_bfm and nir_op_u/ibfe according to SM5 spec.

That is: the five least significant bits provide the values of
'bits' and 'offset' which is the case for all hardware currently
supported by NIR and using the bfm/bfe instructions.
This patch also changes the lowering of bitfield_insert/extract
using shifts to not use bfm and removes the flag 'lower_bfm'.

Tested-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir/algebraic: add optimization pattern for ('ult', a, ('and', b, a)) and friends.

These optimizations are based on the fact that
'and(a,b) <= umin(a,b)'.
For AMD, this series moves the optimization from LLVM to NIR,
so currently no vkpipeline-db changes here.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

lima/ppir: Add fsat op

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

lima/ppir: Add fneg op

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

lima/ppir: Add fabs op

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>