Luke Kenneth Casson Leighton [Wed, 29 May 2019 21:35:34 +0000 (22:35 +0100)]
wire up FU-FU matrix using inverted row/col
Luke Kenneth Casson Leighton [Wed, 29 May 2019 21:28:09 +0000 (22:28 +0100)]
make FU-FU DepCell a row
Luke Kenneth Casson Leighton [Wed, 29 May 2019 20:46:40 +0000 (21:46 +0100)]
do dependency row as multi-bit SRLatch
Luke Kenneth Casson Leighton [Wed, 29 May 2019 15:11:32 +0000 (16:11 +0100)]
add start of instruction queue
Luke Kenneth Casson Leighton [Wed, 29 May 2019 12:02:51 +0000 (13:02 +0100)]
wait for individual batch-units rather than the global signal
Luke Kenneth Casson Leighton [Wed, 29 May 2019 10:13:35 +0000 (11:13 +0100)]
whoops wrong mask for branch instruction decode
Luke Kenneth Casson Leighton [Wed, 29 May 2019 10:10:22 +0000 (11:10 +0100)]
get issue logic working for issue unit array
Luke Kenneth Casson Leighton [Wed, 29 May 2019 09:41:25 +0000 (10:41 +0100)]
latch opcode on instruction issue
Luke Kenneth Casson Leighton [Wed, 29 May 2019 03:21:04 +0000 (04:21 +0100)]
use opcode-base issue units, parallel units
Luke Kenneth Casson Leighton [Wed, 29 May 2019 00:24:01 +0000 (01:24 +0100)]
add docstring
Luke Kenneth Casson Leighton [Wed, 29 May 2019 00:10:49 +0000 (01:10 +0100)]
group computation units together
Luke Kenneth Casson Leighton [Mon, 27 May 2019 12:02:23 +0000 (13:02 +0100)]
remove waw stall from issue unit
Luke Kenneth Casson Leighton [Mon, 27 May 2019 10:58:09 +0000 (11:58 +0100)]
add an IssueUnitGroup which has a priority picker
Luke Kenneth Casson Leighton [Mon, 27 May 2019 09:51:17 +0000 (10:51 +0100)]
stop on shadow for the moment
Luke Kenneth Casson Leighton [Sun, 26 May 2019 01:03:07 +0000 (02:03 +0100)]
have to bring in a reset signal into the shadow units to get them to go to
a known state, after a branch result is known
Luke Kenneth Casson Leighton [Sat, 25 May 2019 22:48:40 +0000 (23:48 +0100)]
separate out go_die from go_rd/go_wr to stop reg read/write triggering
Luke Kenneth Casson Leighton [Sat, 25 May 2019 22:21:14 +0000 (23:21 +0100)]
get fake branch delay time working
Luke Kenneth Casson Leighton [Sat, 25 May 2019 22:16:49 +0000 (23:16 +0100)]
whoops, operation supposed to be tested, not counter
Luke Kenneth Casson Leighton [Sat, 25 May 2019 17:21:20 +0000 (18:21 +0100)]
branch success/fail nearly there
Luke Kenneth Casson Leighton [Sat, 25 May 2019 12:34:11 +0000 (13:34 +0100)]
experimenting with branch shadowing
Luke Kenneth Casson Leighton [Sat, 25 May 2019 07:55:47 +0000 (08:55 +0100)]
add branch speculation using shadows
Luke Kenneth Casson Leighton [Fri, 24 May 2019 16:54:43 +0000 (17:54 +0100)]
use internal latch qlq value instead of creating a separate sync register
Luke Kenneth Casson Leighton [Fri, 24 May 2019 16:38:58 +0000 (17:38 +0100)]
remove dummy values for branch setup
Luke Kenneth Casson Leighton [Fri, 24 May 2019 16:37:32 +0000 (17:37 +0100)]
replace m.d.comb += with comb += etc. increases readability
Luke Kenneth Casson Leighton [Fri, 24 May 2019 16:09:54 +0000 (17:09 +0100)]
remove unneeded import
Luke Kenneth Casson Leighton [Fri, 24 May 2019 14:44:01 +0000 (15:44 +0100)]
use create_random_ops function
Luke Kenneth Casson Leighton [Fri, 24 May 2019 14:41:39 +0000 (15:41 +0100)]
add in branch speculation recorder, link to branch
Luke Kenneth Casson Leighton [Fri, 24 May 2019 14:17:01 +0000 (15:17 +0100)]
add branch speculation record
Luke Kenneth Casson Leighton [Fri, 24 May 2019 13:30:19 +0000 (14:30 +0100)]
make bgt accessible outside of CU
increase shadow width (make room for branch shadow)
Luke Kenneth Casson Leighton [Fri, 24 May 2019 13:15:15 +0000 (14:15 +0100)]
check that bgt test ALU works
Luke Kenneth Casson Leighton [Fri, 24 May 2019 13:01:23 +0000 (14:01 +0100)]
add delay on branches
Luke Kenneth Casson Leighton [Fri, 24 May 2019 13:00:44 +0000 (14:00 +0100)]
remove unneeded code
Luke Kenneth Casson Leighton [Fri, 24 May 2019 13:00:00 +0000 (14:00 +0100)]
add delay on branches
Luke Kenneth Casson Leighton [Fri, 24 May 2019 11:41:08 +0000 (12:41 +0100)]
work on branch simulation logic
Luke Kenneth Casson Leighton [Fri, 24 May 2019 11:40:28 +0000 (12:40 +0100)]
reset shadow latches if neither success nor fail are applied
Luke Kenneth Casson Leighton [Fri, 24 May 2019 09:06:39 +0000 (10:06 +0100)]
split out shared wait for issue and wait for busy clear functions
Luke Kenneth Casson Leighton [Fri, 24 May 2019 08:49:48 +0000 (09:49 +0100)]
make a start on a branch simulator
Luke Kenneth Casson Leighton [Fri, 24 May 2019 07:56:59 +0000 (08:56 +0100)]
add simple branch-compare example ALU
Luke Kenneth Casson Leighton [Fri, 24 May 2019 07:12:03 +0000 (08:12 +0100)]
add priority picker docstring
Luke Kenneth Casson Leighton [Fri, 24 May 2019 06:55:06 +0000 (07:55 +0100)]
cleanup, docstrings
Luke Kenneth Casson Leighton [Thu, 23 May 2019 20:57:56 +0000 (21:57 +0100)]
shadow seems to do the job of guaranteeing write-after-write
Luke Kenneth Casson Leighton [Thu, 23 May 2019 14:19:49 +0000 (15:19 +0100)]
set up the shadow grid
Luke Kenneth Casson Leighton [Thu, 23 May 2019 13:27:10 +0000 (14:27 +0100)]
only want a single-bit transition
Luke Kenneth Casson Leighton [Thu, 23 May 2019 13:23:32 +0000 (14:23 +0100)]
add in busy_prev/next signal to work out which unit was activated
Luke Kenneth Casson Leighton [Thu, 23 May 2019 12:55:38 +0000 (13:55 +0100)]
shadow fail/good signals need to be amalgamated (shadow enable is the matrix)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 11:07:03 +0000 (12:07 +0100)]
make shadow inputs/good/fail arrays (actual matrix now)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 10:58:19 +0000 (11:58 +0100)]
decide to do write-after-write shadows
Luke Kenneth Casson Leighton [Thu, 23 May 2019 09:28:40 +0000 (10:28 +0100)]
connect FUFU/FURegs Matrices to resettable go_rd/go_wr (include go_die)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 09:12:10 +0000 (10:12 +0100)]
start wiring up shadow matrix
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:58:14 +0000 (09:58 +0100)]
re-enable shadow/go_die
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:52:14 +0000 (09:52 +0100)]
whoops disconnected go_wr from CUs by mistake
Luke Kenneth Casson Leighton [Thu, 23 May 2019 08:44:42 +0000 (09:44 +0100)]
add shadow matrix (unconnected)
Luke Kenneth Casson Leighton [Thu, 23 May 2019 07:51:15 +0000 (08:51 +0100)]
add shadow matrix, array of shadow functions
Luke Kenneth Casson Leighton [Thu, 23 May 2019 07:50:49 +0000 (08:50 +0100)]
add in shadown and go_die into comp unit
Luke Kenneth Casson Leighton [Thu, 23 May 2019 06:51:13 +0000 (07:51 +0100)]
split out shadow into separate module
Luke Kenneth Casson Leighton [Wed, 22 May 2019 23:20:46 +0000 (00:20 +0100)]
sort out counter, rename data_o to data_r (register), document CompUnit
Luke Kenneth Casson Leighton [Wed, 22 May 2019 19:43:35 +0000 (20:43 +0100)]
invert write pending before use
Luke Kenneth Casson Leighton [Wed, 22 May 2019 19:18:08 +0000 (20:18 +0100)]
testing if hazard can be done in current cycle
Luke Kenneth Casson Leighton [Wed, 22 May 2019 13:22:18 +0000 (14:22 +0100)]
use global pending vectors for read/write pending accumulation
Luke Kenneth Casson Leighton [Wed, 22 May 2019 13:05:44 +0000 (14:05 +0100)]
clean up names, also note that readable is true if no writes are pending
and writable is true if no reads are pending
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:36:39 +0000 (13:36 +0100)]
use shifter opcode
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:24:01 +0000 (13:24 +0100)]
ignore self-to-self read and write pending hazards
Luke Kenneth Casson Leighton [Wed, 22 May 2019 12:09:49 +0000 (13:09 +0100)]
read-after-write self-referring hazard
Luke Kenneth Casson Leighton [Wed, 22 May 2019 10:56:56 +0000 (11:56 +0100)]
allow loops to run instruction batches more than once
Luke Kenneth Casson Leighton [Wed, 22 May 2019 10:10:13 +0000 (11:10 +0100)]
WaW needs to stall
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:43:43 +0000 (10:43 +0100)]
wait for busy to go LOW before ending
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:43:20 +0000 (10:43 +0100)]
experiment with different completion times
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:24:49 +0000 (10:24 +0100)]
add in 2 more ALUs, now 4x4 scoreboard
Luke Kenneth Casson Leighton [Wed, 22 May 2019 09:00:50 +0000 (10:00 +0100)]
add mul and shift to simulation
Luke Kenneth Casson Leighton [Wed, 22 May 2019 08:57:46 +0000 (09:57 +0100)]
add extra regression test
Luke Kenneth Casson Leighton [Wed, 22 May 2019 08:57:36 +0000 (09:57 +0100)]
add div and shift (as experiment)
Luke Kenneth Casson Leighton [Wed, 22 May 2019 07:34:12 +0000 (08:34 +0100)]
have to stop forward progress if issue is set
Luke Kenneth Casson Leighton [Wed, 22 May 2019 06:27:37 +0000 (07:27 +0100)]
random regression test shows an inter-dependency fail
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:59:53 +0000 (23:59 +0100)]
working on all cycles, RaW / WaR
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:54:02 +0000 (23:54 +0100)]
got working (sort-of) cscore6600
Luke Kenneth Casson Leighton [Tue, 21 May 2019 22:53:53 +0000 (23:53 +0100)]
got working (sort-of) cscore6600
Luke Kenneth Casson Leighton [Tue, 21 May 2019 09:32:23 +0000 (10:32 +0100)]
add read/write reg select vectors, in and out, similar to FunctionUnit
Luke Kenneth Casson Leighton [Mon, 20 May 2019 20:00:52 +0000 (21:00 +0100)]
use dep cell format
Luke Kenneth Casson Leighton [Mon, 20 May 2019 11:11:30 +0000 (12:11 +0100)]
invert x/y in fu pending
Luke Kenneth Casson Leighton [Mon, 20 May 2019 10:19:13 +0000 (11:19 +0100)]
nearly there with readable/writable on FU matrix
Luke Kenneth Casson Leighton [Mon, 20 May 2019 08:07:44 +0000 (09:07 +0100)]
attempting to work out FU-FU matrix connections
Luke Kenneth Casson Leighton [Mon, 20 May 2019 07:49:48 +0000 (08:49 +0100)]
include hazard line to swap rd/wr dependencies
Luke Kenneth Casson Leighton [Sun, 19 May 2019 16:43:05 +0000 (17:43 +0100)]
non-overlapping instructions ok
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:34:50 +0000 (16:34 +0100)]
sync ok on simple add
Luke Kenneth Casson Leighton [Sun, 19 May 2019 15:11:51 +0000 (16:11 +0100)]
add reg clearing and read-request release
Luke Kenneth Casson Leighton [Sun, 19 May 2019 09:34:02 +0000 (10:34 +0100)]
use register-based DepCell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 08:19:40 +0000 (09:19 +0100)]
creating separate dependency cell which can be used for all 3 src1/src2/dest
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:39 +0000 (07:15 +0100)]
experiment switching over fwd and rsel in dependency cell
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:15:12 +0000 (07:15 +0100)]
add individual dependency cell (sync mode)
Luke Kenneth Casson Leighton [Sun, 19 May 2019 06:14:31 +0000 (07:14 +0100)]
scoreboard 6600 experimentation
Luke Kenneth Casson Leighton [Sat, 18 May 2019 14:53:57 +0000 (15:53 +0100)]
whoops bug where rsel lists were being re-initialised to empty
Luke Kenneth Casson Leighton [Sat, 18 May 2019 11:38:56 +0000 (12:38 +0100)]
reduce length of vectors (per-row only single bit)
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:12:23 +0000 (10:12 +0100)]
connect up vectors direct
Luke Kenneth Casson Leighton [Sat, 18 May 2019 09:03:46 +0000 (10:03 +0100)]
connect dependency row outputs
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:53:10 +0000 (09:53 +0100)]
compress dependency matrix outputs into a row
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:43:27 +0000 (09:43 +0100)]
move dependency cells to row class
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:19:54 +0000 (09:19 +0100)]
Revert "whoops use global vector correctly"
This reverts commit
d6723d9007b9fb5b9f56290e26af3e6bfa4f69f1.
Luke Kenneth Casson Leighton [Sat, 18 May 2019 08:18:03 +0000 (09:18 +0100)]
whoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:47:29 +0000 (08:47 +0100)]
whoops use global vector correctly
Luke Kenneth Casson Leighton [Sat, 18 May 2019 07:00:03 +0000 (08:00 +0100)]
reduce syncs, get FU-FU and FU on same clock cycle