mem-ruby: LL/SC fixes

The implementation for load-linked/store-conditional did not work
correctly for multi-core simulations. Since load-links were treated as
stores, it was not possible for a line to have multiple readers which
often resulted in livelock when using these instructions to implemented
mutexes. This improved implementation treats load-linked instructions
similarly to loads but locks the line after a copy has been fetched
locally. Writes to a monitored address ensure the 'linked' property is
blown away and any subsequent store-conditional will fail.

Change-Id: I19bd74459e26732c92c8b594901936e6439fb073
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27103
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add support for multiple call types in the m5 utility.

Using mechanisms added in previous CLs, this change modifies the m5
utility so that it can use any of the back ends enabled and implemented
by each variant, defaulting to one particular implementation if not is
selected explicitly.

On x86, the default mechanism is the magic address. All other variants
default to the magic instruction since they don't have a well
established address to use or even in most cases an implementation to
use.

The ability to override the particular magic address the utility wants
to use (necessary on variants such as aarch64) will be added in a future
CL.

Change-Id: I5fc414740e30759e7dde719cddcc8d5d41f8cc74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27242
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: added news on RISC-V to RELEASE-NOTES.md.

Change-Id: I9b60cd2f533e6d4ce677e8a9b7bb5a5698e51c61
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28448
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: be prepared for CSR changes during PT walk.

If the address space is changed (by writing to SATP), it can happen that
a page table walk is in progress. Previously, this failed if the ASID
changed, because we then used the wrong ASID for the lookup.

This commit makes sure that we don't access CSRs after the beginning of
the walk by loading SATP, STATUS, and PRV at the beginning.

Change-Id: I8c184c7ae7dd44d78e881bb5ec8d430dd480849c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28447
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix MESI_Three_Level erroneous transition

The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update tests to save output on failure

The previous commit which tried to do this, did not work with parallel
execution. In this case, the fixtures that were modified were in the
child process and the parent process's fixtures were never updated.
Instead of modifying the object, use the information passed in from the
testlib.

See 4c28149ffa5d09e6fe14952dcaf8df5d0cd8f328
Previous review:
https://gem5-review.googlesource.com/c/public/gem5/+/17451

Change-Id: Ib4c06c5e3f82994199d6f0c1fa69452e93444d75
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19529
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Fix tmpfiles in testlib

Previously, the testlib would generate and not clean up 100s of
temporary files in /tmp. This puts all of the tempfiles in the same
directory to make sure they are cleaned up on a successful test.

Change-Id: If4dcd93ab4b5df556c046753266a71365d1388c1
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19528
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Build the marshal binary in a bare minimum environment

This change adds an additional bare minimum environment that includes
python only and changes the marshal binary to compile using it.

Change-Id: Id5d1ee6899796d746d8dc1a004cfe4795f040c55
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28428
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: update linux boot tests

This change updates the config scripts used by linux boot
tests to make them compatible with change that deprecated
LinuxX86System

JIRA: https://gem5.atlassian.net/browse/GEM5-440

Change-Id: I04beff2915c03a2c3a774351edbba60d7ff26867
Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28427
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use AssociativeSet in Stride prefetcher

Avoid replicating associative set functionality in Stride prefetcher's
pc tables.

The indexing policy used previously had some peculiarities, so both
the extractTag and extractSet have been made virtual so that previous
behavior could be kept.

Change-Id: I19a86cb3c4b40031fef427d5f7eed9d5c5673a44
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24603
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use SatCounter in Stride prefetcher

There is no need to reimplement saturating counter functionality.

Change-Id: Ie7753089873f41a378ab88fd5f095302c3428797
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24542
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Cleanup of SBOOE prefetcher

Made the latencyBuffer a CircularQueue.

Improved encapsulation of the Sandbox struct.

Fixed score() to follow function declaration guidelines.

Removed redundant fatal error checking for score threshold.

Change-Id: I1904884e96f103c67930abafc28b75796aadc406
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24541
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use CircularQueue in PIF prefetcher

Use CircularQueue for PIF's history buffer, and change the indexing
storage to a CQ iterator.

Change-Id: I75bbb75a6be41bd063f662baedbd4c9de33644de
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24540
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Use CircularQueue for the STeMS's RMOB

Replace rmobHead functionality with a CircularQueue. As a side
effect, RMOB entry's valid bit was removed.

Change-Id: If0b39cfe15de1e47dde0689a0ebc46b623ec1e55
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24539
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix DCPT with CircularQueue

This patch fixes the following bugs:

- Previously when deltaPointer was 0 or 1, getting the last or penultimate deltas
  would be wrong for non-pow2 deltas.size(). For example, if the last added delta
  was to position 0, the previous should be in position 19, if deltas.size() = 20.
  However, 0-1=4294967295, and 4294967295%20=15.

- When searching for the previous late and penultimate, the oldest entry was being
  skipped.

Change-Id: Id800b60b77531ac4c2920bb90c15cc8cebb137a9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24538
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Don't assert on branch target addresses

We should assume a branch target can be any address.

JIRA: https://gem5.atlassian.net/browse/GEM5-483

Change-Id: I6f6da1f9260d6e8978536967dc7fcf1808965db2
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28347
Reviewed-by: Trivikram Reddy <tvreddy@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added RELEASE-NOTES.md

These release notes will enable users to keep track of the main changes
between gem5 versions. The RELEASE-NOTES.md should also notify the user
of any API changes they should be aware of when using this release of
gem5.

Notes on major changes should be apended to the end of the list as
they are added to the repo.

Change-Id: If75748306a8086b2abbe2f912dbb2ec9f1a6895f
Issue-on: https://gem5.atlassian.net/browse/GEM5-439
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27807
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Fix compareVersions for python 3.

When the internal utility function make_version_list sees a string, it
tries to convert it into a list using the map() function. In python 3,
that returns an iterator. The following call to zip() will consume those
iterators, and then the following calls to len() will die because they
don't work on map iterators.

This is only a problem if all the common components of the version lists
are equal, and the comparison needs to then check if one of the lists
was equal to the other but with more components. When versions are
equal, for instance when compiling with the oldest supported version of
gcc (4.8.0) this error surfaces and breaks our scons build.

A simple fix is to just wrap the call to map() with list() to convert
the iterator to a flat list, making the other logic work as before.

Change-Id: If9dc5cd7fff70c21229ac3dd9a017edeccd26148
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28309
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix priority of multi compressor

The priority queue comparator orders such that false gives the
entry a higher priority. Therefore, if it is desired to make
the entry with lowest decompression latency have higher priority,
the comparison must be inverted.

Can be tested with:
  MultiCompressor(compressors=[
    PerfectCompressor(decompression_latency=1),
    PerfectCompressor(decompression_latency=2)])

Where it is expected that compressor0 (the one with decomp lat
of 1) is always chosen.

Change-Id: I44acbf5f51c6e47efdd2a16fba9596935cf2eb69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28367
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Token port implementation

Adds a TokenPort which uses tokens for flow control rather than the
standard retry mechanism in gem5. The port is intended to be used
for flow control where speculatively sending packets is not possible.
For example, GPU instructions require this to send memory requests
to the cache coalescer.

Change-Id: Id0d55ab65b7c773e97752b8514a780cdf7d88707
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27428
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add build opts for GCN3 GPU ISA

Change-Id: I5f2662fe72d876b7bf816b0353aaefb85fc6c1c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28130
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: add option to set the timeouts for the TCPs and SQCs

Change-Id: Icff2bd0237ddcc0d21db17208df8e53ff6f43e86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28129
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-hsa: Add HSA device and HSA packet processor

This change adds support for HSA devices, which are
DMA devices that have an HSA packet processor (HSAPP).

An HSA packet processor model is also included. The
HSAPP is a DMA device that matains AQL packet queues
and handles extraction of AQL packets, scheduling
of AQL queues, and initiates kernel launch for HSA
devices.

Because these devices directly interact with low-level
software and aid in the implementation of the HSA ABI
we also include some headers from the ROCm runtime:
the hsa.h and kfd_ioctl.h headers. These aid with
support ROCm for the HSA devices and drivers.

Change-Id: I24305e0337edc6fa555d436697b4e607a1e097d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28128
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
    The decoder is defined in these files. The decoder
    is implemented as a lookup table of function pointers
    where each decode function will decode to a unique
    ISA instruction, or do some sub-decoding to infer
    the next decode function to call.

    The format for each OP encoding is defined in the
    header file.

Registers:
    registers.[hh|cc] define the special registers and
    operand selector values, which are used to map
    operands to registers/special values. many
    convenience functions are also provides to determine
    the source/type of an operand, for example vector
    vs. scalar, register operand vs. constant, etc.

GPU ISA:
    Some special GPU ISA state is maintained in gpu_isa.hh
    and isa.cc. This class is used to hold some special
    registers and values that can be used as operands
    by ISA instructions. Eventually more ISA-specific
    state should be moved here, and out of the WF class.

Vector Operands:
    The operands for GCN3 instructions are defined in
    operand.hh. This file defines both scalar and
    vector operands wth GCN3 specific semantics. The
    vector operand class is desgned around the generic
    vec_reg.hh that is already present in gem5.

Instructions:
    The GCN3 instructions are defined and implemented
    throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
    op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
    all fall under one of the OP encoding types; for example
    scalar memory operands are of the type SMEM, vector
    ALU instructions can be VOP3, VOP2, etc. The base code
    common to all instructions of a certain OP encoding type
    is implemented in the OP encodings files, which includes
    operand information, disassembly methods, encoding type,
    etc.

    Each individual ISA isntruction is implemented as
    a class object in instructions.[hh|cc] and are derived
    from one of the OP encoding types. The instructions.cc
    file is primarily for the execute() methods of each
    individual instruction, and the header file provides
    the class definition and a few instruction specific
    API calls.

    Note that these instruction classes were auto-generated
    but not using the gem5 ISA description language. A
    custom ISA description was used and that cannot be released
    publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Inheritance fixes in varargs

Change-Id: I3c6027223893363df098d1990a4ad3d07c2ff5ff
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28250
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Avoid const from member due to &Message::operator=(...)

Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix access modifier in Arm*ProcessBits class

Change-Id: Ie983abc94dd9e62bbec3f584b70b0d04d6e8305d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28248
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Disable unsupported -Wl,--as-needed in MacOS

Change-Id: Id6f8199b818217c4fcf4b80efdb7cc9e1d14e32b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28173
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix inconsistency in variable name

Change-Id: I091a2d0cc8bfa7b8d98c4f508d175868d0fd7249
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28172
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Removed the unused parameter m_id from VirtualChannel

Change-Id: Ie6f8db9b1cb0d0e0ca694c631c6662413fd833c1
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28171
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix function signature inconsistencies in semihosting

Change-Id: Icb1aa30cb67b676d49681f68e1d62b3af409e26b
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28170
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix mismatch between #ifndef and #define in varargs.hh

Change-Id: I558b6c3c69a5003a77cc95b414e620715c3dbbae
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28169
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm, mem-ruby, sim: Add missing overrides

Change-Id: I5ab18960bd61953e68777746426adb657818f825
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28168
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Downgrade constexpr causing build errors to const

Change-Id: Idf5ae62603b6181d44aaaef91b774fa7b26eb718
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28167
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add an option to suppress the return value in invokeSimcall.

Sometimes when using the GuestABI mechanism, gem5 wants to know that a
function was called and with what arguments to do its own processing,
but doesn't want to return its own value since it will still let the
simulated system execute its own function. There are also situations
where gem5 wants to return a value, but not through the normal
mechanism. That happens when, for instance, a gem5 op is triggered by a
memory access, and that access is what should return the value, not a
particular fixed register.

This option is a template parameter rather than a function argument so
that if it's not going to be used, no "Return" type needs to be defined
since it's not present at all in the chain of functions invokeSimcall
expands to.

This will also make it easier to reuse generic ABIs in those situations
without having to make custom wrappers.

Change-Id: I969e78495c8f4e73f4de1a3dfb4d74c9b30f5af5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28288
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use the protobuf version to choose between ByteSize(Long).

Older versions of protobuf are apparently still what's provided with
some current versions of some distributions. To avoid breaking the build
on those distributions and to avoid an annoying deprecation warning on
newer systems, check GOOGLE_PROTOBUF_VERSION to choose which to use.

According to the CHANGES.txt file here:

https://github.com/protocolbuffers/protobuf/blob/master/CHANGES.txt

The new ByteSizeLong function was introduced in version 3.1.0 in 2016.

Change-Id: I7f8eeda144bf9556d17d7a0a741996f3137b48b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28287
Reviewed-by: Tommaso Marinelli <tommarin@ucm.es>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Addition of PowerDomains

PowerDomains group multiple objects together to regulate their power
state. There are 2 types of objects in a PowerDomain: leaders and
followers. The power state of a PowerDomain is the most performant
power state of any of the leaders. The power state of the followers is
determined by the power state of the PowerDomain they belong to: they
need to be in a power state which is more or equally performant to the
power state of the PowerDomain.

Leaders can be ClockedObjects or other PowerDomains. Followers can
only be ClockedObjects. PowerDomains can be be nested but a
PowerDomain can only be a leader of another PowerDomain, NOT a
follower. PowerDomains are not present in the hierarchy by default,
the user needs to create and configure them in the configuration file.

The user can add an hierachy by setting the led_by parameter. gem5
will then create leaders and followers for each domain and calculate
the allowed power states for the domain.

Objects in a PowerDomain need to have at least the ON state in the
possible_states.

An example of a powerDomain config is:

pd = PowerDomain()
cpu0 = BaseCPU()
cpu1 = BaseCPU()
shared_cache = BaseCache()
cache.power_state.led_by = pd
pd.led_by = [cpu0, cpu1]

This will create a PowerDomain, where the CPUs determine their own
power states and the shared cache (via the PowerDomain) follows those
power states (when possible).

Change-Id: I4c4cd01f06d45476c6e0fb2afeb778613733e2ff
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28051
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Specify the states a PowerState object can be in

This commit adds the concept of possible power states to the
PowerState SimObject. This is a list of the power states a specific
object can be in. Before transitioning to a power state, a PowerState
object will first check if the requested power states is actually an
allowed state. The user can restricted the power states a
ClockedObject can go to during configuration. In addition, this change
sets the power states, a CPU can be in.

Change-Id: Ida414a87554a14f09767a272b54b5d19bfc8e911
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28050
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Creation of PowerState class

This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Change fs_power.py to use absolute paths for stats

fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.

Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27893
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-power: Fix the way the power model accesses stats

With the introduction of StatGroups the organization of stats has
changed and the power modeling framework has been broken. This CL uses
the new function Stats::resolve to retrieve pointers to the necesary
stats and use them in the power estimation formulas.

Change-Id: Iedaa97eeddf51f7a0a1f222918715da309943be3
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27892
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base, python, sim: Add support for resoving a stat using its name

This CL adds resolve, a function in the Stats namespace that allows
access to a stat as specified by its name.

Change-Id: I4fa8bed394b4cb35d9c6cf5d8db062b8d6bb9ca5
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27891
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add support for resolving stats within groups by name

This change adds a member function to the Group class that returns a
stat given its name. The function will go through all stats in the
group and its subgroups and will return the stat that matches the
name. For example, if g is the Group system.bigCluster.cpus then a
call to

p = g.resolveStat("ipc")

will return a pointer to the stat system.bigCluster.cpus.ipc.

Change-Id: I5af8401b38b41aee611728f6d1a595f99d22d9de
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27890
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add function that returns all variables in a MathExpr

This changes adds support for retrieving all variables in a math
expression. The added function can be called in all valid expressions
and will return the variables in a vector of strings.

Change-Id: I086ba04aa1f798400c97a0b6bf982018a2457c64
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27889
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: create tests for various traffic generators on NULL

New tests were added for:

- garnet_synth_traffic.py
- ruby_random_test.py
- ruby_direct_test.py

These tests are factored out with the tests for:

- memcheck.py
- ruby_mem_test.py

Each new test was calibrated to last about 5 seconds on a Lenovo ThinkPad
P51.

Change-Id: Ie13d3963e1163cffae5dce329b623fbebbf2b983
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26808
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: fix the memcheck test

The file was raising due to the undefined constant `verifiers`, leading
the test to be ignored.

./main.py list -v

would show this as:

```
Traceback (most recent call last):
  File "/gem5/tests/../ext/testlib/loader.py", line 239, in load_file
    execfile(path, newdict, newdict)
  File "/gem5/tests/gem5/memcheck/test_memcheck.py", line 32, in <module>
    verifiers=verifiers,
NameError: name 'verifiers' is not defined

Exception thrown while loading "/gem5/tests/gem5/memcheck/test_memcheck.py"
Ignoring all tests in this file.
```

The test has been modified to have an empty verifiers list, which should
still catch bugs since src/mem/mem_checker.cc has several asserts already
which would be caught by the test system due to the exit status.

Also make the following changes to the test:

-   move it to tests/gem5/memory/test.py with other memory tests.

    This makes it easier to see all the tests in the source in one go, and
    might make it easier to factor certain memory things out later on.

-   reduce --maxtick to a value that finishes in 7 seconds on a Lenovo
    ThinkPad P51.

    The previous value would take 50x longer, which feels too long for a
    single test.

-   enable --prefetchers to also stress a prefetcher in the test

Change-Id: I58bd598b1142f349d25fa4fa4a8e41529e61a9ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26807
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: make MemTest panic on a packet error

Before this change, running:

./build/NULL/gem5.opt configs/example/ruby_mem_test.py -m 20000000 \
  --functional 10

would only print warning for memory errors such as:

warn: Read access failed at 0x107a00

and there was no way to make the simulation fail.

This commit makes those warnings into errors such as:

panic: Read access failed at 0x107a00

unless --suppress-func-errors is given.

This will be used to automate MemTest testing in later commits.

Change-Id: I1840c1ed1853f1a71ec73bd50cadaac095794f91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26804
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: remove exec of Options.py from ruby_mem_test.py

The removed exec statement does not appear to be needed however,
since Options is already imported above with:

from common import Options

Change-Id: I934a65d21fa5099a786224a5476d609e4d707205
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: report that we don't have debugging support.

According to the debugging spec (page 47), a debugger can test which
triggers are enabled by writing 0 to TSELECT and reading it back. If a
different value is read, the trigger is not supported.

Therefore, we currently always set a different value to indicate that
we do not support any triggers.

Change-Id: If222e913c4517adb2da4f6f0ffeedb4e4808a586
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25659
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.

Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.

Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25658
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: let FPU instructions fault if status.FS = off.

These checks are required for some tests in the RISC-V test suite.
However, actually we also need to set the INITIAL/CLEAN/DIRTY flags
accordingly, which is not done yet.

Change-Id: If5d6ac22069b51a57b6353cd6d45b77ee51a4d55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25657
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: make uret,sret,mret SerializeAfter,NonSpeculative.

These instructions potentially change the privilege level, upon which
the execution of other instructions depends. For that reason, we need to
make *ret SerializeAfter and we also don't want to execute them
speculatively.

Change-Id: If3b5ba6ec3b4102d53c51cf723eba5d5da3eaa2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25656
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: make accesses to CSRs SerializeAfter.

According to page 57 in the RISC-V manual, CSR accesses "need to be
performed in program order with respect to those instructions whose
execution behavior is affected by the state of the accessed CSR".

Thus, we need to make them SerializeAfter to ensure that the following
instructions are executed with the potential changes to the CSR. In
theory, we could be smarter here by only considering write accesses to
CSRs and considering the following instructions, but for now we simply
serialize for every CSR access.

Change-Id: I69391fccaec31c34d944c55bac2f04d37947ebfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25655
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fault according to status.{TVM,TSK,TW}.

Change-Id: I38dddadb3373d2156b8fc57eabff861a062021cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25654
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added dummy implementation of wfi instruction.

Change-Id: I7ca86f57c7d794bf544e34e747875049a3f29d6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25653
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fault on mstatus accesses from lower privilege modes.

Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added (un)serialization of miscRegFile.

Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: show names of MiscRegs on accesses.

Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: added bare metal FS support for RISC-V.

Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,configs: let RISC-V use the PT walker cache.

Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fixed formatting.

Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26986
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: implement RemoteGDB::acc for FS mode.

Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26985
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: implement sfence.vma to flush TLBs.

Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26984
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: make sure only supported modes can be set in SATP.

Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added TLB and page table walker.

That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11.

Both the TLB and PT walker are based on x86 (the code duplication of the
page table walkers will be reduced by a separate commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25647
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Add a unit test for some aspects of the aapcs64 ABI.

This test covers the templates which attempt to classify types, but not the
actual gathering of arguments of distribution of return values. As before, we
can't really use standard C++ to accurately test for HFAs and HVAs, so we stick
with approximating them by detecting arrays of the right types.

For example, I think technically we should also accept a struct with only 4
float members, but c++ templates aren't able to match against types in that way
as far as I know.

Change-Id: I1d7756a964a86c0c5ea13e068a5fc74603e14e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28268
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Fix some bugs in the aapcs64 implementation.

The templates which checked for short vectors, and our approximation of
HFA, HVA and HXA types were not correct. This change actually simplifies
them along with getting them to produce correct results. In the case of
HXA, there was a logic bug where an && was used where an || was
intended.

There may still be bugs in the actual collection of arguments and
setting of return values since those aspects are harder to test.

Change-Id: Ice3177205a98c678ecb43ba600813b3909c44e6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28267
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add missing requestToMemory MessageBuffers

In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28187
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix clasta/b and lasta/b simd&fp instructions

The simd&fp version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Do not require args.kernel to be set in baremetal.py

This is allowing to us run baremetal.py with the --dtb-gen option
without needing to specify a --kernel argument

Change-Id: I98f1bc865d2f4e2230b1a85453efe83d95ec8a55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28148
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim, arch-arm: Restore capability of running without a kernel

The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/24283

Removed the capability of starting a gem5 simulation without
a kernel object. This patch is restoring it

Change-Id: I6d751bac386cbb250b3593bb12463140dc964ab3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28147
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add an abstraction layer for call types in the m5 utility.

These make the calling code in m5.c a little bit more generic. Each call
type will have a function to check the arguments and see if that type is
being requested and/or has any additional options set in the arguments.
If so, those are processed, and argc and argv are adjusted.

Then another function returns the appropriate dispatch table to use for
that invocation scheme. This is behind a function instead of, for
instance, a global variable because it gives the call type a little bit
more control over what's happening, for instance if it would use
different implementations in slightly different circumstances.

Change-Id: I661cf202ec657466496767cbdf331fe27995ab26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27241
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Add a helpful macro for merging two tokens to m5ops.h.

I've needed this type of macro often when writing code which uses the
M5OP_FOREACH macro, and so rather than re-write it each time, lets just
put a version here. This is such a common type of macro to need that
you'd think it would be part of a standard header somewhere, but to my
knowledge it isn't.

Change-Id: I0df0d9d2fd7ce1b9e6c355d6e4db197ccfff7c35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27239
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Use a dispatch table to call ops in the m5 utility.

This way different implementations can be substituted in depending on
how the low level ops should actually be triggered (inst, addr,
semihosting, (etc?)).

Change-Id: I7c6eab7d87cc973d0bc9c1889037a0f89ce057e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27238
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,util: Remove explicit ';'s from M5OP_FOREACH.

It may be the case that each item M5OP_FOREACH iterates over should end
in a ',' and not a ';', for instance when putting each item into an
array or initializing a structure. If the caller still wants a ';', they
can add it into the definition of the M5OP macro.

Change-Id: Idd6538b0aad27df39658c3f749c6ff5e4fe55e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27237
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add the SE mode m5 ops to m5ops.h.

These shouldn't be called in fs mode through the m5 utility and
probably shouldn't be called directly either, but this makes them
consistent with the other functions which are mentioned in
asm/generic/m5ops.h.

Change-Id: I80df8b4d507350bc6d2763e770e38e0370931632
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,misc: Rename M5OP_ANNOTATE to M5OP_RESERVED1.

The M5OP_ANNOTATE constant is unused and treated as a reserved op in
gem5. Rename it to make it official and consistent.

Change-Id: Id5fe6a3aa402a2e0cd187503abff9b09e81b3724
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Tidy up M5OP_FOREACH and the constants in m5ops.h.

Make sure all the operations that have constants (and aren't deprecated
or reserved) and present in M5OP_FOREACH in order of their constants.
Also move M5OP_ANNOTATE up so that all the constants are also in order.

Change-Id: I8d9f69b020aeb39311a24606a286a76de10a51cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Delete the execfile m5 utility command.

This command was just a thin wrapper around the readfile command, and
can be easily duplicated by piping the output of that command to
/tmp/execfile and then running it.

Change-Id: Ib77166ee9f07571d57e4d21e9615def55e5391a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27233
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Eliminate the sw99param m5 utility command.

This is a small additional layer on top of the initparam command and
just breaks the returned value into 12 bit chunks. It presumes that
there is some particular meaning to the default initparam value which
may or may not be true. It's not entirely clear what the 12 bit chunks
that this command returns are actually good for, and it's been around
long enough that there isn't really any good documentation about what
it's intended purpose was.

Change-Id: I21af0e0cf7501f47026a6dd31920d46cfccff167
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27232
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Improve the usage text of the m5 utility.

Make sure there *is* help text for every command, alphabetize the
commands, explain all the arguments and what the command as a whole
does.

Change-Id: Icf74f8c638545c8658c99169dce728f7b1127806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27231
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Further simplify the initParam implementation.

Take advantage of string comparisons when looking up what to do with a
given key.

Convert the key_str[12] registers from little endian to host endian.
This matches a corresponding change in the m5 utility to pack the
registers in little endian order, regardless of what the actual guest
endianness is.

Absorb the initparam_keys.hh header into sim/pseudo_inst.cc, and convert
its constants to c++ strings. The constants defined in it might be
useful to guest code calling into the m5 ops, but not for gem5 itself.
By merging them into the .cc file, we also don't have to do any tricks to
try to avoid them having multiple definitions.

Change-Id: I3a450ad7f9c4dca25f79c7835d7f9c167c02ae98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27230
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Replace a deprecated method in protoio.cc.

A warning says that ByteSize is now deprecated, and should be replaced
with ByteSizeLong. This change does that.

Change-Id: I0b1aef733c509a73a0af9c39b359d39579d1fd37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28185
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Refactor the string->register packing function in the m5 utility.

This change removes the responsibility for checking the number of
arguments and handing the default of no string back into init_param and
out of the function which packs strings into registers. It also renames
the function to more closely match its purpose, and rewrites it to be a
bit simpler and (IMHO) easier to follow.

Importantly, rather than doing a hand implemented strcpy which would
follow the endianness of the target/simulated platform, this change
makes this function pack the registers explicitly in little endian byte
order. This way on the consuming end in gem5, the initParam function
doesn't have to care what the guest endianness is, it can just translate
them from little endian to whatever the host endianness is (very likely
also little endian).

Change-Id: Ie9f79ecb8d4584c6e47a2793a31ccaa8c7c15986
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27229
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Simplify collecting the key value in initParam.

If the first register is all zeroes, it doesn't really matter what the
other register is. If the first register has the entire string, we still
don't care what the other register has in it. There's no reason to
complicate the code with these extra checks.

Change-Id: I22ad521b9ace915ccb75f15934fc6b3d650d5293
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27228
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

util: Correct some help text for the initparam m5 utility command.

The "key" value passed to the initparam command can be at most 16
characters long, but the text said it had to be shorter than 16
characters.

Change-Id: Ic98dc87feb868b44c4210ae16cb5b0dad2a67d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27227
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove the "pin" command from the m5 utility.

This command did not use any m5 ops, does the same thing as the
"taskset" command under Linux:

https://linux.die.net/man/1/taskset

and might even have introduced a build error if compiled for any other
OS since that would have left a trailing comma in the mainfuncs array.

While the last problem would be easy to correct, this is not related to
the purpose of this utility (giving access to m5 ops), and is redundant
with an existing standard utility provided with Linux.

Change-Id: Ie72b9310f5e6264f6035013f47ebe74a27464abb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27226
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add missing functions to the java wrapper for m5 ops.

Change-Id: I9bdef3cb78cc01b0743ea38eec6f6d28cd2f6765
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27225
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use a const char * in the m5op m5_add_symbol.

The symbol name is not modified by the m5 op, so a const char * is more
accurate and gives the caller more flexibility as far as what they can
pass in.

Change-Id: Iee567bceef501643175dd5c65551a4c8554a6e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27224
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

util: Update the java wrapper names for m5 ops.

These were regularized a while ago, but not updated in the java wrapper.
There are also missing ops, but these will be added in another change.

Change-Id: Iaef281249c26d446709ba2b214ee37d574f6b72c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27223
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

misc: Get rid of constants used for critical path annotation.

The constant for the critical path annotation function itself is still
used in gem5 along with the M5OP_RESERVED opcodes to signal
unimplemented functions.

Change-Id: I71c7a56d0346f8aafe23e733a1eea703dda1af92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27222
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Get rid of the m5op_flags.h header.

This held flags for use with the critical path annotation instructions
which are no longer accessible through the m5 utility and so not used.

Change-Id: Ifee85ce78bb33c4a3e8c0db845974f17d8867199
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27221
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Remove m5a_ (critical path annotation) prototypes from m5ops.h.

This mechanism is still available within gem5 as far as I can tell, but
it's not accessible through the pseudo instruction interface.

Change-Id: I69bd3c92239721a6d1049cee66eb7a0c1bdbc272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27220
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Convert the other architecture's m5 utility builds to scons.

Because I don't have a canonical toolchain to set SPARC's defaults to,
it will by default build for Linux instead of Solaris like it used to.
This will make it hard to test, but without a compiler there's not much
I can do.

This also coincidentally brings the SPARC version more in line with the
other variants which all target Linux.

Change-Id: Ie19217e988782da124306160920f40ef168840e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27219
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

arch-arm: Fix Sve Fcmla indexed instruction

Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.

Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: SVE instructions do not use AHP format

SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28108
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Do not increment exponent if FPSCR.FZ in fplib

If flushing to zero, the exponent shouldn't be incremented since
we are supposed to produce a 0 value and not a denormal number

Change-Id: Ib6dd594a6555b2fd9a20a52b59cbf1f5f94c2eb5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28107
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add some additional flags for files in the m5 util.

When compiling static objects, disable pie with the -no-pie linker flag.
This is necessary for x86, and doesn't seem to hurt anything for the
other variants.

When compiling shared objects, particularly the assembly files which
can't rely on the compiler to generate position independent code, define
M5OP_PIC so that the assembly code can configure itself correctly.

Change-Id: I80d1ea7a7704666027e74228036af5e0e4b9eac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27218
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>