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Megan Wachs [Sat, 25 Mar 2017 00:28:21 +0000 (17:28 -0700)]
Merge remote-tracking branch 'origin/debug-0.13' into spi_delay_hack
Megan Wachs [Sat, 25 Mar 2017 00:27:55 +0000 (17:27 -0700)]
JTAG: make TRSTn optional for all helpers as well to match the IO.
Megan Wachs [Fri, 24 Mar 2017 20:24:45 +0000 (13:24 -0700)]
SPI: TEMP HACK do not merge!
Hard code 3-cycle synchronizer for SPI input without Pinmux.
Megan Wachs [Thu, 23 Mar 2017 02:16:20 +0000 (19:16 -0700)]
Merge remote-tracking branch 'origin/master' into debug-0.13
Yunsup Lee [Wed, 22 Mar 2017 05:12:37 +0000 (22:12 -0700)]
update TLRegisterNode to take Seq of AddressSet
Megan Wachs [Wed, 22 Mar 2017 00:51:28 +0000 (17:51 -0700)]
TLSPI: address parameter must now be a sequence.
Megan Wachs [Tue, 14 Mar 2017 21:52:39 +0000 (14:52 -0700)]
Adjust JTAG for rocket-chip changes
Megan Wachs [Fri, 10 Mar 2017 22:09:24 +0000 (14:09 -0800)]
Merge remote-tracking branch 'origin/master' into debug-0.13
Wesley W. Terpstra [Fri, 3 Mar 2017 05:22:41 +0000 (21:22 -0800)]
xilinx pcie: add the high PCIe address bits (physical path)
The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
Wesley W. Terpstra [Fri, 3 Mar 2017 05:00:44 +0000 (21:00 -0800)]
Merge pull request #4 from sifive/periphery-keys
DTS
Wesley W. Terpstra [Fri, 3 Mar 2017 04:28:38 +0000 (20:28 -0800)]
devices: include DTS meta-data
Wesley W. Terpstra [Thu, 23 Feb 2017 02:42:47 +0000 (18:42 -0800)]
devices: create periphery keys for all devices
Standardize how they are connected to the periphery bus
Megan Wachs [Thu, 2 Mar 2017 22:46:34 +0000 (14:46 -0800)]
jtag: The jtag interfaces have moved to a different package.
Megan Wachs [Fri, 17 Feb 2017 02:45:48 +0000 (18:45 -0800)]
Merge pull request #2 from sifive/homogenous_bag_peripherals
Use HeterogenousBag to handle lists of peripherals
Megan Wachs [Fri, 17 Feb 2017 01:52:24 +0000 (17:52 -0800)]
Use HomogenousBag to handle lists of peripherals
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
solomatnikov [Fri, 10 Feb 2017 22:30:01 +0000 (14:30 -0800)]
Merge pull request #1 from sifive/i2c
I2c implementation
Alex Solomatnikov [Fri, 10 Feb 2017 02:45:35 +0000 (18:45 -0800)]
Merge remote-tracking branch 'origin/master' into i2c
Alex Solomatnikov [Thu, 9 Feb 2017 19:37:40 +0000 (11:37 -0800)]
Flipped polarity of output enables to match Guava pins logic
Alex Solomatnikov [Thu, 9 Feb 2017 19:36:19 +0000 (11:36 -0800)]
Made regs 32-bit word aligned to match the rest of the system
Alex Solomatnikov [Wed, 8 Feb 2017 00:14:28 +0000 (16:14 -0800)]
Added note: WISHBONE interface replaced by Tilelink2
Alex Solomatnikov [Tue, 7 Feb 2017 23:58:04 +0000 (15:58 -0800)]
Added license
Alex Solomatnikov [Mon, 6 Feb 2017 18:39:47 +0000 (10:39 -0800)]
Renamed i2cDevices to i2c
Wesley W. Terpstra [Sat, 4 Feb 2017 02:17:58 +0000 (18:17 -0800)]
xilinx mig: track changes in rocket-chip
Alex Solomatnikov [Sat, 4 Feb 2017 02:10:03 +0000 (18:10 -0800)]
Addressing comments: bool style, comments, removed suggestName
Alex Solomatnikov [Sat, 4 Feb 2017 00:41:59 +0000 (16:41 -0800)]
Bug fixes: passing OC WB test
Wesley W. Terpstra [Wed, 1 Feb 2017 21:53:54 +0000 (13:53 -0800)]
sifive-blocks: trust diplomacy to get names right
Alex Solomatnikov [Wed, 1 Feb 2017 01:20:53 +0000 (17:20 -0800)]
Completed Chisel RTL (not tested yet)
Wesley W. Terpstra [Tue, 31 Jan 2017 22:03:14 +0000 (14:03 -0800)]
spi: work around ucb-bar/chisel3#472
Wesley W. Terpstra [Mon, 30 Jan 2017 19:33:30 +0000 (11:33 -0800)]
xilinx ip: adjust to new diplomacy API
Alex Solomatnikov [Tue, 24 Jan 2017 22:58:01 +0000 (14:58 -0800)]
Initial (compilable) version of I2C (no actual logic yet)
Wesley W. Terpstra [Sat, 21 Jan 2017 06:38:27 +0000 (22:38 -0800)]
xilinx pcie: put buffers before the outputs to the controller
Wesley W. Terpstra [Fri, 20 Jan 2017 03:53:03 +0000 (19:53 -0800)]
mig: track change to Blind port API in rocket
Wesley W. Terpstra [Wed, 7 Dec 2016 21:21:20 +0000 (13:21 -0800)]
LazyModule: provide Parameters
This tracks PR #478 in rocketchip.
Wesley W. Terpstra [Wed, 7 Dec 2016 00:13:12 +0000 (16:13 -0800)]
xilinx pcie: bytes, not bits
This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
Wesley W. Terpstra [Sat, 3 Dec 2016 01:48:17 +0000 (17:48 -0800)]
RegMapFIFO: amoor.w can do thread-safe TX
Richard Xia [Wed, 30 Nov 2016 21:29:54 +0000 (13:29 -0800)]
Add /target to .gitignore.
SiFive [Tue, 29 Nov 2016 12:08:44 +0000 (04:08 -0800)]
Initial commit.