gallium/r600: Don't let h/w do endian swap for colorformat

Since the rework on gallium pipe formats, there is no more need to do
endian swap of the colorformat in the h/w, because the conversion between
mesa format and gallium (pipe) format takes endianess into account (see
the big #if in p_format.h).

v2: return ENDIAN_NONE only for four 8-bits components
(V_0280A0_COLOR_8_8_8_8)

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: remove separate BE path in r600_translate_colorswap

After further testing, it appears there is no need for
separate BE path in r600_translate_colorswap()

The only fix remaining is the change of the last if statement, in the 4
channels case. Originally, it contained an invalid swizzle configuration
that never got hit, in LE or BE. So the fix is relevant for both systems.

This patch adds an additional 120 available visuals for LE and BE,
as seen in glxinfo

v2:
Tested for regressions by running piglit gpu.py with CAICOS (r600g) on
x86-64 machine. No regressions found.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nv50/ir: emit VOTE instruction

Changes from v2:
 - add missing NOT modifier for GK110/GM107

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gk110/ir: add ld lock/st unlock emission

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50,nvc0: bump minimum texture buffer offset alignment

It appears that it actually needs to be aligned to the datum size, so it
was 1 when testing with R8, but it can be as high as 16 with RGBA32.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>

mesa: add GL_OES_gpu_shader5 and GL_EXT_gpu_shader5 support

The two extensions are identical, and are largely taking bits of already
existing desktop functionality. We continue to do a poor job of
supporting the 'precise' keyword, just like we do on desktop.

This passes the relevant dEQP tests that I could find.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

mesa: expose GL_EXT_texture_sRGB_decode on GLES 3.0+

Could be exposed on earlier GLES versions if we supported EXT_sRGB, but
we don't, for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

i965/cfg: Fix comment list punctuation

Trivial

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>

i965/cfg: Split out dead control flow paths to simplify both paths

v2: Fix some bad indentation.  Suggested by Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Don't handle fully empty if/else/endif

This will now never occur.  The empty if-else part would have already
been removed leaving an empty if-endif part.

No shader-db changes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Eliminate an empty then-branch of an if/else/endif

On BDW,

total instructions in shared programs: 8448571 -> 8448367 (-0.00%)
instructions in affected programs: 21000 -> 20796 (-0.97%)
helped: 116
HURT: 0

v2: Remove spurious attempt to combine the if_block with the (removed!)
else_block.  Suggested by Matt and Curro.  Correct the comment
describing what the new pass does.  Suggested by Matt.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Track prev_block and prev_inst explicitly in the whole function

This provides a trivial simplification now, and it makes some future
changes more straight forward.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/cfg: Slightly rearrange dead_control_flow_eliminate

'git diff -w' is a bit more illustrative.  A couple declarations were
moved, the continue was removed, and the code was reindented.  This will
simplify future changes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Simplify brw_nir_lower_vue_inputs() slightly.

The same code appeared in both branches; pull it above the if statement.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Avoid recalculating the normal VUE map for IO lowering.

The caller already computes it.  Now that we have stage specific
functions, it's really easy to pass this in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Avoid recalculating the tessellation VUE map for IO lowering.

The caller already computes it.  Now that we have stage specific
functions, it's really easy to pass this in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Eliminate brw_nir_lower_{inputs,outputs,io} functions.

Now that each stage is directly calling brw_nir_lower_io(), and we have
per-stage helper functions, it makes sense to just call the relevant one
directly, rather than going through multiple switch statements.

This also eliminates stupid function parameters, such as the two that
only apply to vertex attributes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Split brw_nir_lower_inputs/outputs into per-stage functions.

These functions are both giant switch statements where most cases don't
overlap at all.  Let's put the bulk of the work in per-stage helpers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Remove catch-all nir_lower_io call with specific cases.

Most cases already call nir_lower_io explicitly for input and output
lowering.  This catch all isn't very useful anymore - we can just add it
to the remaining cases.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Move optimizations from brw_nir_lower_io to brw_postprocess_nir.

This simplifies things.  Every caller of brw_nir_lower_io() immediately
calls brw_postprocess_nir().  The only real change this will have is
that we get an extra brw_nir_optimize() call when compiling compute
shaders, but that seems fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Always do NIR IO lowering at specialization time.

We've now hit literally every case other than geometry shaders (and
compute shaders, but those are a no-op).  So, let's just move geometry
shaders over too and be done with it.

The only advantage to doing this at link time was to save the expense
of running the pass on recompiles.  But we're already running a lot of
passes, and the extra code complexity isn't worth it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Make an is_scalar boolean in brw_compile_gs().

Shorter than compiler->scalar_stage[MESA_SHADER_GEOMETRY], which can
help with line-wrapping.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/nir: Do lower_io late for fragment shaders

The Vulkan driver wants to be able to delete fragment outputs that are
beyond key.nr_color_regions; this is a lot easier if we lower outputs at
specialization time rather than link time.

(Rationale added to commit message by Ken)

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Set dest type to UW for several send messages

Without this, on SIMD 16 the send instruction destination will appear
to write more than one destination register, causing the simulator to
report an error.

Of course, the send instruction can actually write more than one
destination register regardless of the type set for the destination,
so this is a bit strange.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

nvc0: rework nvc0_compute_validate_program()

Reduce the amount of duplicated code by re-using
nvc0_program_validate(). While we are at it, change the prototype
to return void and remove nvc0_compute.h which is now useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: make sure to validate compute global buffers on Fermi

No reason to not validate those global buffers and this might avoid
fails if someone try to use the global memory from compute programs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: move nvc0_validate_global_residents() to nvc0_compute.c

While we are at it, rename it to nvc0_compute_validate_globals() and
update its prototype.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

egl/wayland: Try to use wl_surface.damage_buffer for SwapBuffersWithDamage

Since commit d1314de293e9e4a63c35f094c3893aaaed8580b4 we ignore
damage passed to SwapBuffersWithDamage.

Wayland 1.10 now has functionality that allows us to properly
process those damage rectangles, and a way to query if it's
available.

Now we can use wl_surface.damage_buffer and interpret the incoming
damage as being in buffer co-ordinates.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>

virgl: add missing CAP turned off.

program: Remove extra reference_program()

It was already done in get_mesa_program()

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

automake: add nine to make distcheck

Will allow us to catch/prevent issues, like the one in mesa 11.2.0-rc1.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

st/nine: don't forget to bundle the nine_limits.h file

Without this mesa 11.2.0-rc1 ended up busted :-(

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Repored-by: Ondřej Súkup <mimi.vx@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

i965/fs: Allow saturate propagation to propagate negations into MADs.

Allows us to transform

   mad      res  src0   src1   src2
   mov.sat  dst  -res

into

   mad.sat  dst  -src0 -src1   src2

instructions in affected programs: 3712 -> 3688 (-0.65%)
helped: 24

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Allow saturate propagation to propagate negations into ADDs.

Allows us to transform

   add      res  src0   src1
   mov.sat  dst  -res

into

   add.sat  dst  -src0 -src1

No shader-db changes.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Allow saturate propagation to propagate negations into MULs.

Allows us to transform

   mul      res  src0   src1
   mov.sat  dst  -res

into

   mul.sat  dst  src0  -src1

instructions in affected programs: 45246 -> 45054 (-0.42%)
helped: 162

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Don't CSE negated multiplies with saturation.

It's not correct to CSE these multiplies

   mul.sat dst1, -a, b
   mul.sat dst2,  a, b

by emitting a negated MOV from dst1 to dst2:

   mul.sat dst1, -a, b
   mov     dst2, -dst1

Take 2.0*2.0 for example. The first multiply would produce 0.0 and the
second would produce 1.0.

Fixes bad generated code in 18 to 22 shaders:

instructions in affected programs: 432 -> 464 (7.41%)
helped: 4
HURT: 18

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Consider ubo_load to be a horizontal operation.

Unclear to me whether it actually is a horizontal operation that cannot
be vectorized, but the fact that i965 generates the same code in either
case makes me less interested in finding out.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94199
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/ast: Implicit conversion from double to float is not allowed

Also, renamed get_conversion_operation to avoid
future misunderstandings.

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium/radeon: return correct values for BE in r600_translate_colorswap

Because I changed the swizzle check, I also need to adapt the return
values for each check.

It's basically almost the same as before, we just cross between STD and
STD_REV, and cross between ALT and ALT_REV

This fixes the rgba test in gl-1.0-readpixsanity (piglit) and also
fixes tri-flat (mesa demos).

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: remove duplicate define from enum pipe_format

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

glsl: Detect do-while-false loops and unroll them

Previously loops like

   do {
      // ...
   } while (false);

that did not have any other loop-branch instructions would not be
unrolled.  This is commonly used to wrap multiline preprocessor macros.

This produces IR like

    (loop (
       ...
       break
    ))

Since limiting_terminator was NULL, the loop unroller would
throw up its hands and say, "I don't know how many iterations.  How
can I unroll this?"

We can detect this another way.  If there is no limiting_terminator
and the only loop-branch is a break as the last IR, there's only one
iteration.

On my very old checkout of shader-db, this removes a loop from Orbital
Explorer, but it does not otherwise affect the shader.  The loop removed
is the one the compiler inserts surrounding the switch statement.

This change does prevent some seriously bad code generation in some
patches to meta shaders that I recently sent out for review.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Enable tiled mem_copy with sRGB-formatted resources

RGBA8 and BGRA8 unorm formats are compatible with the various
mem_copy functions. Their sRGB counterparts are also compatible
because they're also color-renderable (of importance when the
specified resource is a readbuffer) and they share the same
physical layout.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: replace for loop with bitshifting in supported_buffer_bitmask()

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: updates some comments in buffers.c

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: make _mesa_draw_buffers() static

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: make _mesa_draw_buffer() static

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: make _mesa_read_buffer() static

Not called from any other file.  Remove _mesa_ prefix and update comments.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: move declaration of buffer var in handle_first_current()

Declare the var in the scopes where it's used.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: use gl_buffer_index in a few places

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: remove useless break statement

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: rename st_readpixels to st_ReadPixels

To match the convention of other device driver functions.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: fix frontbuffer glReadPixels regressions

The change "mesa/readpix: Don't clip in _mesa_readpixels()" caused a
few piglit regressions.  The failing tests use glReadPixels to read
from the front color buffer.  The problem is we were trying to read
from a non-existant front color buffer.  The front color buffer is
created on demand in st/mesa.  Since the missing buffer bounds were
effectively 0 x 0 the glReadPixels was totally clipped and returned
early.

The fix involves creating the real front color buffer when we're about
to try reading from it.

Tested with llvmpipe and VMware driver on Linux, Windows.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94253
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94254
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94257
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium/radeon: Correctly translate colorswaps for big endian

The current code in r600_translate_colorswap uses the swizzle information
to determine which colorswap to use.

This works for BE & LE when the nr_channels is <4, but when nr_channels==4
(e.g. PIPE_FORMAT_A8R8G8B8_UNORM), this method can not be used for both BE
and LE, because the swizzle info is the same for both of them.

As a result, r600g doesn't support 24bit color formats, only 16bit, which
forces the user to choose 16bit color in X server.

This patch fixes this bug by separating the checks for LE and BE and
adapting the swizzle conditions in the BE part of the checks.

Tested on an Evergreen GPU (Cedar GL FirePro 2270) running inside POWER7
Big-Endian Machine.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "11.2" "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: use sizeof on the correct type

Before the luminance stride was based on the size of GL_FLOAT
which is just the type constant (0x1406). Change it to use the
size of GLfloat.

Reviewed-by: Brian Paul <brianp@vmware.com>

tgsi/scan: handle holes between VS inputs, assert-fail in other cases

"st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap"
added a vertex shader declaring IN[0] and IN[2], but not IN[1].

Drivers relying on tgsi_shader_info can't handle holes in declarations,
because tgsi_shader_info doesn't track that.

This is just a quick workaround meant for stable that will work for vertex
shaders.

This fixes radeonsi DrawPixels and CopyPixels crashes.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>

docs: Mark off GL_OES_shader_image_atomic as done.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/fs: Return result of image atomic in a register of the expected type.

So the result is of float type if we're implementing the float
overload of imageAtomicExchange.  This is the only back-end change
required to support OES_shader_image_atomic AFAICT.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Implement the required built-in functions when OES_shader_image_atomic is enabled.

This is basically just the same atomic functions exposed by
ARB_shader_image_load_store, with one exception:

    "highp float imageAtomicExchange(
         coherent IMAGE_PARAMS,
         float data);"

There's no float atomic exchange overload in the original
ARB_shader_image_load_store or GL 4.2, so this seems like new
functionality that requires specific back-end support and a separate
availability condition in the built-in function generator.

v2: Move image availability predicate logic into a separate static
    function for clarity.  Had to pull out the image_function_flags
    enum from the builtin_builder class for that to be possible.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Add usual extension boilerplate for OES_shader_image_atomic.

v2: No need for extension enable bits (Ilia).

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: Add extension table entry for OES_shader_image_atomic.

v2: No need for extension enable bits (Ilia).

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: rename 3d binding points to NVC0_BIND_3D_XXX

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: rename 3d dirty flags to NVC0_NEW_3D_XXX

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: prefix compute macros with _CP_ instead of _COMPUTE_

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: rename NVXX_COMPUTE to NVXX_CP

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: rename nvc0_context::dirty to nvc0_context::dirty_3d

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: add missing emission of locked load predicate

Like unlocked store on shared memory, locked store can fail and the
second dest which is a predicate must be emitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nvc0/ir: add ld lock/st unlock emission on GK104

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: restore OP_SELP to be a regular instruction

Actually OP_SELP doesn't need to be a compare instruction. Instead we
just need to set the NOT modifier when building the instruction.
While we are at it, fix the dst register type and use a GPR.

Suggested by Ilia Mirkin.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

svga: unbind index buffer when drawing non-indexed primitives

Silences a warning reported by the svga3d device.

v2: also null-out the index buffer pointer

Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: add GL_EXT_texture_border_clamp support

This extension is identical to GL_OES_texture_border_clamp. But dEQP has
tests that want the EXT variant.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

mesa: add GL_OES_texture_border_clamp support

Only minor differences to the existing ARB_texture_border_clamp support.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

mesa: bump version

11.2 has been branched, we're on 11.3 now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

nouveau: update the Makefile.sources list

Reflect the nv50->g80 change and the new gm107_texture header.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

radeonsi: implement binary shaders & shader cache in memory (v2)

v2: handle _mesa_hash_table_insert failure
    other cosmetic changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: remove unused radeon_shader_binary_free_* functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: make radeon_shader_reloc name string fixed-sized

This will simplify implementations of binary shaders.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move some struct si_shader members to new struct si_shader_info

This will be part of shader binaries.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use smaller types for some si_shader members

in order to decrease the shader size for a shader cache.

v2: add & use SI_MAX_VS_OUTPUTS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable compiling one variant per shader

Shader stats from VERDE:

Default scheduler:

Totals:
SGPRS: 491272 -> 488672 (-0.53 %)
VGPRS: 289980 -> 311093 (7.28 %)
Code Size: 11091656 -> 11219948 (1.16 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch: 1732608 -> 2246656 (29.67 %) bytes per wave
Max Waves: 78063 -> 77352 (-0.91 %)
Wait states: 0 -> 0 (0.00 %)

Looking at some of the worst regressions, I get:
- The VGPR increase seems to be caused by the fact that if PS has used less
  than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20.
  However, the wave count remains at 10 if VGPRs <= 24, so no harm there.
- The scratch increase seems to be caused by SGPR spilling.
  The unnecessary SGPR spilling has been an ongoing issue with the compiler
  and it's completely fixable by rematerializing s_loads or reordering
  instructions.

SI scheduler:

Totals:
SGPRS: 374848 -> 374576 (-0.07 %)
VGPRS: 284456 -> 307515 (8.11 %)
Code Size: 11433068 -> 11535452 (0.90 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch: 509952 -> 522240 (2.41 %) bytes per wave
Max Waves: 79456 -> 78217 (-1.56 %)
Wait states: 0 -> 0 (0.00 %)

VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much
and generally spills way less than the default scheduler.
(522240 spills vs 2246656 spills)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: print full shader name before disassembly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: compile non-GS middle parts of shaders immediately if enabled

Still disabled.

Only prologs & epilogs are compiled in draw calls, but each variant of those
is compiled only once per process.

VS is always compiled as hw VS.
TES is always compiled as hw VS.

LS and ES stages are always compiled on demand.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rework polygon stippling for PS prolog

Don't use the pstipple module.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add PS prolog

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add PS epilog

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add TCS epilog

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add VS epilog

It only exports the primitive ID.
Also used by TES when it's compiled as VS.

The VS input location of the primitive ID input is v2.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add VS prolog

This is disabled with use_monolithic_shaders = true.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: first bits for non-monolithic shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add code for dumping all shader parts together (v2)

v2: unify some code into si_get_shader_binary_size

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: add code for combining and uploading shaders from 3 shader parts

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fail compilation if non-GS non-CS shaders have rodata

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate 2 pieces of code from create_function

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add samplemask parameter to si_export_mrt_color

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add start_instance parameter to get_instance_index_for_fetch

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out shader key bits for prologs & epilogs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: compute how many input VGPRs fragment shaders have

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: compute how many input SGPRs and VGPRs shaders have

Prologs (shader binaries inserted before the API shader binary) need to
know this, so that they won't change the input registers unintentionally.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add basic code for setting shader return values

LLVMBuildInsertValue will be used on return_value.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nvc0: enable compute shaders on Fermi

Kepler compute support is really different than Fermi and it's not
ready yet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: add atomics support on shared memory for Fermi

Changes from v3:
 - move the previous OP_SELP change to the previous commit

Changes from v2:
 - make sure the op is OP_SELP when emitting the predicate and add one
   assert
 - use bld.getSSA() for mkOp2()
 - add cross edge between tryLockAndSetBB and joinBB

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>