arch-riscv: fix incorrect interrupt checking logic

Whether global interrupt enabling or not is not simply decided by
xIE bit in mstatus, it also depends on current privilige level.
All level lower/higher than current should be disabled/enabled
regardless of the xIE bit. xIE bit is only control the enabling
of interrupt in current privilige level.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-883

Change-Id: I37f83ab77af2efbf1da9b81845828d322e49bf5f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39035
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix some includes

Fix some missing and extra includes around the codebase.

Change-Id: Ibf314b43a966943a8096958f68382e1e245f29e3
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38738
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Fix gem5_within_systemc and tlm coupling

Adapt the code to changes introduced with commits 3fb9139 and 392c1ce.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-874

Change-Id: I0023157f1a2e5935f624c0a12e61f6b3e0d98b97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39215
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix race related to atomics in VIPER

There is a race condition in VIPER where an atomic issued to the same
address can occur resulting in multiple trigger messages signalling the
compleition of the atomic operation. The first message was deallocating
the TBE causing the second message to dereference a nullptr when looking
up the TBE.

A counter is added to track the number of in flight AtomicDone trigger
messages. The AtomicDone is not called until the last in flight message
arrives at the trigger queue. The remaining messages call AtomicNotDone
which simply pops the message from the queue and keeps the TBE
allocated.

Change-Id: Ie1de0436861a7c393ad6d2fb2faceb83c18d4cc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39175
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util-docker: Add gdb to gcn-gpu Dockerfile

gdb is generally useful.

Change-Id: Ic73822a5f61914cafba0699949dccabc81c03d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39096
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Rename Flag status to enabled

The semantic of "The status of a flag is true/false" may be
confusing. Rename `status` to `enabled`, so that queries
become "Is this flag enabled?".

Change-Id: I8cdd76766d80d65007a9f204abcf71b18211ab42
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38711
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base: Add unit test for debug.hh

Add unit tests for the functions and classes in debug.hh.

breakpoint() is not being tested.

Change-Id: I1ae7318a043aa9dc479d4f970c1fd6c9946f4357
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38710
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Fix LGKM decrementing for flat atomic insts

A prior commit (f6ec145fc0) fixed early LGKM decrementing for flat loads
and stores, but failed to address flat atomics.

Per the GCN3 ISA, LGKM count is decremented on flat atomics with return
when the data has been returned. This patch checks if the flat
instruction is an atomic with return, and decrements LGKM count if so.

Change-Id: I5c0c2c205a8b21327d4c42ba71c59842c15bd63b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39155
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Rename the root stats group to RootStats

Currently, the name of the stats group of thr Root object is
Stats, which is likely to be confused with the Stats namespace.

This commit renames the struct to RootStats. This allows the
Stats namespace to be expressed as `Stats::`, which is
consistent with how the namespace is accessed in other part of
gem5.

Change-Id: Ieb425c3df1f5c0d5f11b1a467a36b2e0e07b2771
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38915
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove the curTick prototype from base/statistics.hh.

This prototype might convince the compiler that it should refer to
curTick indirectly through the linker, but curTick is inline (and making
it not has very high overhead), so there's a decent chance no non-inline
version will be emitted.

Change-Id: Iab5aacb145d4a974bc1bc0abdf7275c40fbb9c38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38997
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Break the eventq.hh dependency in core.hh.

The original implementation of curTick used a thread local variable,
_curEventQueue, and its getCurTick() method, to retrieve the curTick for
the currently active event queue. That meant that core.hh needed to
include eventq.hh so that the EventQueue type was available, which also
indirectly brought in a lot of other dependencies.

Unfortunately this couldn't easily be fixed by making curTick()
non-inline since this added a significant amount of overhead when
tested.

Instead, this change makes the code in core.hh/core.cc keep a pointer
directly to a Tick. The code which sets _curEventQueue now also sets
that pointer when _curEventQueue changes.

The way curTick() now reaches into the guts of the current EventQueue
directly is not great from a modularity perspective, but if curTick is
considered an extension of the EventQueue, then it's just odd that this
part is broken out into a different file.

Change-Id: I8341b40fe75e90672eb1d70e1a368975fcbfe926
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38996
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

gpu-compute: Support for dynamic register alloc

SimplePoolManager doesn't allow mapping of two WGs
simultaneously on the same Compute Unit (provided
the previous WG has been mapped to all the SIMDs)
even if there is sufficient VRF and SRF space
available.

DynPoolManager takes care of that by dynamically
allocating and deallocating register file space
to wavefronts

Change-Id: I2255c68d4b421615d7b231edc05d3ebb27cbd66c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32034
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>

cpu-o3: Add missing tid in Rename's debug message

These arguments were missing.

Change-Id: I8a76e46b2bcfc57f299145954fe72196f5969f29
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39075
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: CSR registers support in RISC-V remote GDB.

Note:
Some less frequently needed CSR registers (e.g. hpm and pmp registers)
are commented out on purpose. Instructions to add them back are
described in remote_gdb.hh comments. This is to avoid spamming the
remote GDB log when using `info reg all`.

Changes:
1. Added GDB XML files to the ext/ directory (mostly from QEMU)
2. Modified RiscvGdbRegCache
- struct r: added CSR registers
- getRegs, setRegs: reading / setting CSR registers
3. Modified RemoteGDB
- availableFeatures: indicate support for XML registers
- getXferFeaturesRead: return XML blobs

Change-Id: Ica03b63edb3f0c9b6a7789228b995891dbfb26b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38955
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Let the pixel pump bypass the DMA FIFO in non-caching mode.

When in non-caching mode, performance metrics are not meaningful, and
we're just interested in functional level behavior. Going through the
DMA FIFO in the HDLCD controller is very inefficient, and prevents
reading a batch of pixels from memory all in one go.

Change-Id: I3fb6d4d06730b5a94b5399f01aa02186baa5c9b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38721
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests, base: Added GTests for base/amo.hh

Issue-on: https://gem5.atlassian.net/browse/GEM5-231

Change-Id: Ia915f9c8bd0732c6c918e8056253bd2fdcdf6b5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26944
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: inform bootloader of kernel position with a register

Before the commit, the bootloader had a hardcoded entry point that it
would jump to.

However, the Linux kernel arm64 v5.8 forced us to change the kernel
entry point because the required memory alignment has changed at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee

Therefore the only way to have a single bootloader that boots both
pre-v5.8 and post-v5.8 kernels is to pass that information from gem5
to the bootloader, which we do in this patch via registers.

This approach was already used by the 32-bit bootloader, which passed
that value via r3, and we try to use the same register x3 in 64-bit.

Since we are now passing this information, the this patch also removes
the hardcoding of DTB and cpu-release-addr, and also passes those
values via registers.

We store the cpu-release-addr in x5 as that value appears to have a
function similar to flags_addr, which is used only in 32-bit arm and
gets stored in r5.

This commit renames atags_addr to dtb_addr, since both are mutually
exclusive, and serve a similar purpose, DTB being the newer recommended
approach.

Similarly, flags_addr is renamed to cpu_release_addr, and it is moved
from ArmSystem into ArmFsWorkload, since it is not an intrinsic system
property, and should be together with dtb_addr instead.

Before this commit, flags_addr was being set from FSConfig.py and
configs/example/arm/devices.py to self.realview.realview_io.pio_addr
+ 0x30. This commit moves that logic into RealView.py instead, and
sets the flags address 8 bytes before the start of the DTB address.

JIRA: https://gem5.atlassian.net/browse/GEM5-787
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add documentation to flags.hh

Add documentation to the Flags class. Use this opportunity
to rename some arguments to make their intention clearer.

Finally, the constructors have been merged using a default
value of 0.

Change-Id: I924b1d5c20a3e2066be64ab124ae1a5d96d4b3bf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38735
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove Flags<U> assignment

Currently unused and broken. Since these are templated classes,
and _flags is private, the assignment is a compilation error.
Furthermore, assignment of flags of different types is likely
undefined behavior.

Change-Id: I8430045c42c003efc74e343cc5b4a4350bc2ad92
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38713
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Assert Flags' type is unsigned

Operations rely on the use of unsigned integers.

Change-Id: I825a88f81b54577585976d6558b1409870897721
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38712
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove flag from allFlags on destruction

When a flag is destroyed it must be removed from the list
containing all flags.

Use this opportunity to remove "using namespace std" since
it is barely used.

Change-Id: I201371a770c56e11b92532e146d577c6ecb29d34
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38709
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove negation operator in Flag

There is already a bool conversion operator, so there
is no need to provide a negation operator.

Change-Id: If5f99f8a0bb1707c115d139417aedd47bd162963
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38708
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix uninitialized variable in Flag

This was uninitialized, and was breaking expected values
under certain situations.

Change-Id: If51ab6ae038c7c397bc83de1c73af348c1db4ef8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38707
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix update of useful prefetches

The probe notification must be parsed on every hit, even if
the prefetcher is set not to generate prefetches on accesses.
This fixes the calculation of useful prefetches.

Change-Id: Iff298f7bea11013f411f4ba39dba705fd81a0cd4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38177
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix missing includes.

Change-Id: I545ff03041e8fe66dc489c6aa95c009e54df0970
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Remove begin() and end() from CircleBuf.

These functions return iterators which are inconsistent with the usage
model for this type. It should be accessed using the peek, push, and pop
methods and not iterators. If you need a class with iterators which is
oriented around accessing individual elements at a time, the
CircularQueue type is likely a better choice.

Change-Id: I9f37eab12e490b63d870d378a91f601dad353f25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38998
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Use regular atomic accesses for DMA in bypass mode.

These are now accelerated with backdoor accesses and should be at least
as fast as functional accesses. This removes a dependency on port
proxies, and also stops the HDLCD from using functional accesses.

Change-Id: I5e959288eb533d09cffa7b79938aa2f61e4aff7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38720
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Teach the DmaPort to use atomic memory backdoors.

This is implemented similary to the NonCachingSimpleCPU, except that
both the normal atomic and noncaching atomic behaviors are implemented
by the same class. The sendDma function now dispatches to a method which
implements one or the other behavior since that function was getting too
big and complex.

Change-Id: I7972971ef41d1373424e587cf67c8444d50de748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38719
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Generate DMA packets as needed.

Instead of generating all of the DMA packets when a request is
initiated, keep track of the necessary properties and generate them as
needed.

The primary benefit of this approach is that if we don't actually need
packets, for instance if we can satisfy the request using a memory
backdoor, we can just skip them. Otherwise we'll have wasted time
creating them, and then have to clean them up.

Change-Id: I04d399fb7bce1ff9a44979c311be356baf2db555
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Re-implement CircleBuf without using CircularQueue.

CircularQueue provides iterators which make it easier for users to
interact with it and helps abstract its internal state, but at the same
time it prevents standard algorithms like std::copy from recognizing
opportunities to use bulk copies to speed up execution. It also hides
the seams when wrapping around the buffer happens which std::copy
wouldn't know how to handle.

CircleBuf seems to be intended as a simpler type which doesn't hold
complex entries like the CircularQueue does, and instead just acts as a
wrap around buffer, like the name suggests. This change reimplements it
to not use CircularQueue, and to instead use an underlying vector.

The way internal indexing is handled CircularQueue was simplified
recently, and using the same scheme here means that this code is
actually not much more verbose than it was before. It also intrinsically
handles indexing and bulk accesses, and uses std::copy_n in a way that
lets it recognize and take advantage of contiguous storage and bulk
copies.

Change-Id: I78e7cfe174c52f60c95c81e5cd3d71c6052d4d41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38896
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add a setNext method to the ChunkGenerator.

This method lets you stretch the current chunk, if you want to skip over
some of the upcoming chunks since you've already handled their bytes.

For instance, if you were iterating over pages in a range of virtual
addresses, you might be able to handle multiple page sized chunks at
once if they were represented by a single large sized page table entry.
This mechanism would let you move past all the pages you had just
handled without having to walk through them all one by one.

Change-Id: I7d962f548947b77f0aa1b725036dbcc9e1b28659
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38718
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Fix FLAT insts decrementing lgkm count early

FLAT instructions used to decrement lgkm count on execute, while the
GCN3 ISA specifies that lgkm count should be decremented on data being
returned or data being written.

This patch changes it so that lgkm is decremented after initiateAcc (for
stores) and after completeAcc (for loads) to better reflect the ISA
definition.

This fixes a bug where waitcnts would be satisfied even though the
memory access wasn't completed, which lead to instructions using the
wrong data.

Change-Id: I596cb031af9cda8d47a1b5e146e4a4ffd793d36c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38696
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove default bootscript option for fs_bigLITTLE.py

Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: SMMUv3, enable interrupt interface

Users can set "irq_interface_enable" to allow software to program
SMMU_IRQ_CTRL and SMMU_IRQ_CTRLACK. This is required to boot Linux v5.4+
in a reasonable time. Notice the model does not implement architectural
interrupt sources, so no assertions will happen.

Change-Id: Ie138befdf5a204fe8fce961081c575c2166e22b9
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38555
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Remove the return type from DmaPort::dmaAction.

This function had a comment claiming that returning an arbitrary request
from the call was necessary for page table walker statistics, but
looking at the actual code, the return type was never used. Also
returning whatever the last request happens to be seems arbitrary, and a
bad boundary for modularization. The page table walker should not depend
on the internal implementation of the DMA port.

Change-Id: I00281fbaf6aeb85b15baf54f3d4a23ca1ac72b8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38716
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Fix style in the pixel pump base class.

Change-Id: I8aa25911b367d36d6862780b39781f13724e79dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38715
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Style fixes in the ARM HDLCD device.

Change-Id: I230e0e0db879a56bc23c3ed439b9722e76cdd8e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38484
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: fix the wrong cause register setting

The most significant bit should be set based on interrupt or
exception. I assume in current RV64 implementation the bit should
be 63rd, rather than 31st. This causes interrupt handler to get
invalid cause code.

Minor bug is for the mpie is suppossed to be set to the value of
old mie.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-858

Change-Id: I1cc166c254b35f5c1acb3f5774c43149c61cc37a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add a mechanism to pad the src or dest reg index arrays.

ARM reaches in and pads out the source register index list behind the
parser's back to force dest regs to also be sources in case an
instruction fails predication and needs to forward the original register
values. It shouldn't be hacking up these values in that way, but since
it is, this will let it continue to do so while still fitting in the new
system where each instruction allocates its src/dest reg index arrays to
size.

Change-Id: Ia296be9f63123f18f6cdc0d3bb1314d33e759b3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38380
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Cache the cacheLineSize in the DMA read FIFO.

This is a minor simplification which decouples the FIFO from the system
object at run time, although it does need to read the cache line size
out at construction time.

Change-Id: I57d96a676b9604663b6c9ed7c662640f507c5305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38482
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Make DMA devices use their own ports for functional accesses.

DMA devices already have ports they use for non-functional accesses. We
can just attach a port proxy to that instead of getting one from the
system object.

Change-Id: I5e9adee43c7fe07b4c90978dbb7ec71468caadbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38481
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>

dev: Style fixes in src/dev/dma_device.(cc|hh).

Change-Id: Ie72f30d95e7f889f9a440d0fed57a5940747b40d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38480
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Style fixes in the CircleBuf and Fifo classes.

Change-Id: Ia08548027973e2b18e09bc3f05a6498855bdd7f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38479
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

base,cpu: Simplify the CircularQueue class significantly.

This class had been trying to keep all indices within the modulus of the
queue size, and to use all elements in the underlying storage by making
the empty and full conditions alias, differentiated by a bool. To keep
track of the difference between a storage location on one trip around
the queue vs other times around, ie an alias once the indices had
wrapped, it also keep track of a "round" value in both the queue itself,
and any iterators it created.

All this bookkeeping significantly complicated the data structure.
Instead, this change modifies it to keep track of a monotonically
increasing index which is wrapped at the time it's used. Only the head
index and current size need to be tracked in the queue itself, and only
a pointer to the queue and an index need to be tracked in the iterators.

Theoretically, it's possible that this value could overflow eventually
since it increases forever, unlike before where the index wrapped and
was never larger than the queue's capacity. In practice, the type of the
index was changed from a uint32_t to a size_t, probably a 64 bit value
in modern systems, which will hold much larger values. Also, the round
counter and the index values together acted like a smaller than 64 bit
value anyway, since the round counter would overflow after 2^32 times
around a less than 2^32 entry queue.

One minor interface difference is that the head() and tail() values
returned by the queue are no longer pre-wrapped to be modulo the queue's
capacity. As long as consumers don't try to be overly clever and feed in
fixed values, do their own bounds checking, etc., something that would
be cumbersome considering the wrapping nature of the structure, this
shouldn't be an issue.

Also, since external consumers no longer need to worry about wrapping,
since only one of them was used in only one place, and because they
weren't even marked as part of the interface, the modulo helper
functions have been eliminated from the queue. If other code wants to
perform modulo arithmetic for some reason (which the queue no longer
requires) they can accomplish basically the same thing in basically the
same amount of code using normal math.

Also, rather than inherit from std::vector, this change makes the vector
internal to the queue. That prevents methods of the vector that aren't
aware of the circular nature of the structure from leaking out if
they're not overridden or otherwise proactively blocked.

On top of simplifying the implementation, this also makes it perform
*slightly* better. To measure that, I ran the following command:

$ time build/ARM/base/circular_queue.test.opt --gtest_repeat=100000 > /dev/null

and found a few percent improvement in total run time. While this
difference was small and not measured against realistic usage of the
data structure, it was still measurable, and at minimum doesn't seem to
have hurt performance.

Change-Id: Ic2baa28de135be7086fa94579bbec451d69b3b15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38478
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix style issues in the circular queue.

Change-Id: I61da587d760019a338522f098745f375a5ce429e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38477
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: fix MIE csr register setting bugs

Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: googletest: upgrade to googletest 1.10

Upgrade googletest to 1.10
upstream commit: 703bd9caab50b139428cea1aaff9974ebee5742e
tag: release-1.10.0

sha1sum c4bb446ee3f8a730168097f44c31c90b62c63287 generated by command:
find . -type f ! -name SConscript ! -path "./.git/*" ! -name ".*" -print0 \
| sort -z | xargs -0 sha1sum | sha1sum

Change-Id: I6500e13e9c094efd99ebc72b3ae564861e67c159
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38577
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Fix the scons script failing to install git hooks

A recent change,
https://gem5-review.googlesource.com/c/public/gem5/+/38616,
removed the 'root' environment variable, while the git hooks
installation script relies on the variable. This commit
addresses this problem.

Change-Id: I2d27861794021a6a60ef8668461e4127cb1db261
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38655
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Generate error on compression misconfiguration

Compressed caches must use the compressed tags, otherwise a
seg fault will be generated. Besides, if no compressor is
assigned; yet compressed tags are used, data is not compressed.

Generate an error for the first case, and a warning for the
second.

Change-Id: Iac5474ed919163ce38a8c4e8efd9727e5b3d8417
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38635
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Update stats style for SimpleNetwork

Change-Id: I7d54ed02d01a3811b41dce794e308b8b77576c92
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38055
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Update stats style of System and Process

Change-Id: I3af072a61a18f4fbba3f7d4b632c58501e7b7ae8
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37995
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: Update stats of AbstractController and derived classes

This commit moves stats of AbstractController and its derived
classes to a Stats::Group struct.

Also, one of the controllers needs access to the ruby system profiler
stats, and Profiler's stats is now made public as a result.

Change-Id: Ibe04e33a6cf09b453564592d29293b354d0d33c9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38075
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Move CacheMemory stats used in SLICC to a Stats group

This change moves some stats that are used in SLICC to a
separate Stats::Group.

In order to use stats in SLICC, new functions are added in
CacheMemory:
        - profileDemandHit()
        - profileDemandMiss()

The functions increase the corresponding stat by 1.

Change-Id: I52b6fefdf6579a49f626f2fca400641f90800017
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37815
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: Update stats style

This commit makes move stats from several classes in mem/ruby
to corresponding Stats::Group's.

For ruby's Profiler, additional changes are made: there are stats that
are profiled for each of RequestType, for each of MachineType, and for
each of combinations of RequestType and MachineType. The current naming
scheme is ...<stat_name>.<request_type_name>.<machine_type_name>. To make
it easier for stats parser to know whether the stat is of RequestType, or
is of MachineType, or is of (RequestType, MachineType), a prefix is added
as follows,
...<meta>.<stat_name>.<request_type_name>.<machine_type_name>
where <meta> is one of {RequestType, MachineType, RequestTypeMachineType}.

Another point of using this naming scheme is that the parser doesn't
need to know all of RequestType and MachineType.

Change-Id: I8b8bdd771c7798954f984d416f521e8eb42d01ed
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36478
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add reviewers using account ID's when possible

Currently, there are some accounts that cannot be added as a
reviewer due to unknown conflicts associated with the email address.

This commit adds the ability for the bot to use
ReviewerInfo._account_id when possible, and to use email addresses
otherwise.

To reduce the number of queries to the server, a json file will be
created in .data/ to store known account ID's.

Change-Id: I9887bec12d14279e61119a615687a339e3f9c994
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

python: Improve SimObject's warning when parent specified twice

SimObject outputs a warning when its parent is specified more than
once. The cause is most likely that there is unexpected param
specified in the constructor called in the Python interface.

This commit adds a note about this probable cause of this potential
error to the warning message.

Change-Id: I9b6bf5d5fb0c77bfdad5fde42e88f814e8a4b72b
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38359
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Force the m5 utility to be built using c++14.

Otherwise, the version of the standard being used will depend on the
version of the compiler, and may not build consistently on different
machines.

Change-Id: I3a031a2dfe97df3dd83926abb517781069c1c6a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38216
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Break up some unit tests in the m5 utility.

Some unit tests for the inst and semi call types in the m5 utility were
too big and testing multiple scenarioes. This change breaks them up into
individual tests, like in the addr call type unit test.

Change-Id: I764d9edfbe4f6bdcc5907173247f7511c68aa1d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36855
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Use the std namespace for memcpy and memset in the m5 util.

The C++ versions of those functions are technically in the std
namespace, and while they may work without it (the C version leaking
through from somewhere?), they should still use it.

Change-Id: Ib53a7f0c41d7f5776221e7661c616ea51e8ed528
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31834
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

util: Expose addr config mechanisms in the gem5 op java wrapper.

These allow you to set the target physical address, and map or unmap the
region of physical memory. This is not automatic for two reasons. First,
the address needs to be configured before the mapping is done, and
there's no way to ensure that ordering when everything is handled
automatically. Second, if the user isn't going to use the address based
mechanism, then the mapping and access to /dev/mem isn't necessary and
may prevent using the other call types.

Change-Id: I0f9c32d6bfa402ba59ea1bf5672fb7f11003568d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28184
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Embed the JNI library (.so) in the jar file for the gem5 ops.

This makes it easier to manage the java wrapper since there's only one
file. This change also splits up the command builder which builds the
java jar since we need to run one step which produces the .h, then a
second step to build the library, and then finally the step that
produces the jar. The first step is left as a command builder since the
scons Java builder still doesn't know about the -h option, but the
second step now uses the Jar builder.

Change-Id: I76e2e5e86bb3153f2ba69a75ad94cd4e065cd33d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28183
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Enable using different call types in the gem5 ops java wrapper.

Convert the native implementation from C to C++. Also expand the test to
cycle through the different call mechanisms and call "sum" using each
one. This test should primarily be run on a gem5 native CPU which will
support all call types.

To access a particular call type, get an instance of the gem5.Ops class
from the callTypes static map, using the name of the call type you want
as the key. If you just want whatever the default is, use the additional
key "default".

Change-Id: If4ef812c9746fbf974e54cc9fe515e2b581e9939
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28182
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,fastmodel: Change how ARM license slots are throttled.

To limit the number of license slots used by SCons when building fast
model components, the fastmodel SConscript set up a group of nodes
which are attached to each simgen run using the SCons SideEffect
method using one of the library files it generates.

To create each unique node, the SCons Value() method was used, passing
it the counter for the loop. In at least version 4 of SCons, what this
ended up doing was setting that library file as a source for each of
the Value() nodes it corresponds to.

That doesn't *seem* like a problem, but then when creating config
include files, files which expose SCons configuration values to C++,
they also create Value() nodes using the value of the config variable.
In cases where that variable is boolean, the value might be 0 or 1.

The result was that the config header depended on Value(0) (for
instance), and then Value(0) depended on a collection of static library
files.

When scons tried to determine whether the config file was up to date,
it tried to check if if its sources had changed. It would check
Value(0), and then Value(0) would try to compute a checksum for its own
source. To do that, it seems to assume that the value can be
interpreted as a string and tries to decode it as utf8. Since the
library is a binary file, that would fail and break the build with a
cryptic message from within the guts of SCons.

To address this, this change replaces the loop index with a call to
object(). Each instance created in that way will be different from
every other, and there will be no way (purposefully or otherwise) to
create a collision with it when creating Value() nodes for some other
purpose.

Change-Id: I56bc842ae66b8cb36d3dcbc25796b708254d6982
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38617
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Ahbong Chang <cwahbong@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Stop auto including the git tool from the default too override.

SCons has a system of "tools", which basically detect versions of build
tools (compilers, linkers, etc) and set up an environment with the
appropriate build variable substitutions for that tool to be used.

For instance, there would be a "tool" for gcc, and it would detect if
gcc is present on the system, and if so would set the "CC" variable to
"gcc". An actually tool as defined by SCons would be a lot more
sophisticated than that and set more variables, but that's the basic
idea.

To help modularize the gem5 SConstruct file, I moved code which would
set up git commit hooks into a "tool" which helped modularize it and
reduce the size of SConstruct.

This isn't quite right since, while the code does detect if git was
used to check out the source (if there is a .git file at the root), it
doesn't really modify the environment at all. It will also be invoked
every time any environment is set up, although right now that will only
be the DefaultEnvironment, what's used when loose functions like
Builder or Command are called with, and the "main" environment which
all the others are Clone-d from.

Normally, when SCons sets up a new environment, either implicitly or
when Environment() is called, it sets up a bunch of built in tools
which are fixed within SCons itself. If you want, you can add a "tools"
argument to Environment (or to the DefaultEnvironment() function) which
will replace that list of tools. That can be used to make an
environment use the new "git" tool, but it isn't automatic.

SCons also lets you override default tools by creating your own with
the same name as the default. To make loading the git tool automatic,
I added an override "default" tool which, in addition to setting some
defaults which should apply to all environments, also pulled in other
tools, at that time "git" and "mercurial" (RIP).

Unfortunately, that meant that today, apparently particularly with
SCons version 4, *any* Environment would pull in "git", and all of
"git"'s dependencies, even if SCons wasn't set up enough for those to
work.

To break that dependency, this change stops the default tool from
automatically loading the git tool, although it does continue to set
other defaults which have very minimal external dependencies. When
creating the "main" Environment in the SConstruct, the "git" tool is
now added in explicitly. Since the list of tools replaces the original
and doesn't extend it, we have to add in "default" explicitly as well.

Really, the "git" tool should be converted from the tool interface into
something more appropriate, like perhaps a small module under
site_scons which site_init.py can import and call. When that happens,
main can be declared like normal again.

While making this change, I also got rid of a few nonstandard additions
to the main environment that were little used and not really necessary.
When reading the SConstruct, it wasn't very obvious where those extra
values were coming from, and they didn't really add any value.

Change-Id: I574db42fc2196bf62fc13d6754357c753ceb9117
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38616
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,python: Updated maintainers.py to fix deprecation warning

The following warning was being thrown:

```
util/maint/lib/maintainers.py:120: YAMLLoadWarning: calling yaml.load() without Loader=... is deprecated, as the default Loader is unsafe. Please read https://msg.pyyaml.org/load for full details.
```

This is fixed by adding `Loader=yaml.SafeLoader` when calling
`yaml.load()`.

Change-Id: I3b79115379a45409967a8848175658ab3c13bfc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38476
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,python: Updated git-pre-commit.py to use Python3

Change-Id: I3897a57237637a55e75b3c9c4cb43918b39cf7d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38475
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Use BitUnions and a RegisterBank in the Uart8250.

Change-Id: I139db4f08f9e6addfed4906ea6c49ee67439d30e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36818
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix some comments in x86 KVM process initialization.

These comments did not reflect what the code was actually doing.

Change-Id: I2bcd23bd68c870e364bdfd0b9b0eb5dcb560e713
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38537
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Change some CR0 settings when setting up kvm x86 processes.

These values were (seemingly) arbitrarily changed from the original,
non-KVM settings, and no longer matched the comments which were also
copied over. These two bits enable alignment checking on memory accesses
(not normally used on x86), and whether kernel code can write to read
only pages.

Change-Id: I48e560e448e4849607f12e9336d1ab0458ad9407
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38536
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Fix style in the ISA templates.

Change-Id: I3014d26c8649efaf6227f2e3a798cc6c4183a0c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38379
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Implement a frequency-sampling compressor

Implementation of a generic frequency-based sampling
compressor. The compressor goes through a sampling stage,
where no compression is done, and the values are simply
sampled for their frequencies. Then, after enough samples
have been taken, the compressor starts generating
compressed data.

Compression works by comparing chunks to the table of
most frequent values. In theory, a chunk that is present
in the frequency table has its value replaced by the
index of its respective entry in the table. In practice,
the value itself is stored because there is no straight-
forward way to acquire an index from an entry.

Finally, the index can be encoded so that the values
with highest frequency have smaller codeword representation.
Its Huffman coupling can be used similar to the approach
taken in "SC 2 : A Statistical Compression Cache Scheme".

Change-Id: Iae0ebda08e8c08f3b62930fd0fb7e818fd0d141f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37335
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add a data-update probe to cache

This probe is responsible for notifying any changes to the
data contents of a block. This includes fills, overwrites,
and invalidations/evictions.

Jira: https://gem5.atlassian.net/browse/GEM5-814

Change-Id: I1ff3c09c63d5402765c2125c4d76d95b614877d6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37096
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a listener checker to probes

Add a function to check if a probe has listeners. This can be
used to avoid performing costly tasks when no one is listening.

Change-Id: I8996a0ea298cb7cf97ac8aa9e627331a22bea26e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38175
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

util: m5ops, optional extra build flags

This increases compilation control for users. Main use case is building
m5ops as part of an image distribution. Specifying a different sysroot
or dynamic linker may be required when the cross toolchain is built as
part of the process.

Change-Id: Icbd3faa92ea6e084fc4a9b2db83129bce73faf21
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38416
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Use the right register type when initializing x86 kvm processes.

Functionally this doesn't matter, since no bitfields are used in the
type and it devolves into just being a uint64_t, but we should use CR8
and not CR4 when initializing the CR8 register.

Change-Id: Ifc7dc9072d552f7010afce9115427c8ed624ebb9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38535
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

x86: Set the effective base of the TSS when initializing a process.

For some segments, there are two base registers. One is the
architecturally visible base, and the other is the effective base used
when actually referencing memory relative to that segment. The process
initialization code was setting the architecturally visible base,
presumably because that's the value used by KVM, but was setting the
effective base to zero.

Change-Id: I06e079f24fa63f0051268437bf00c14578f62612
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38488
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Some small style fixes in arch/x86/process.hh.

Moved two single line functions to be all on one line, and added some
consts.

Change-Id: Iecfa3a9c2bde69ce2f26e9531864a7cb92b0a1df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,sim: Remove special handling for KVM in the clone syscall.

When a gem5 op is triggered using a KVM MMIO exit event, the PC has
already been advanced beyond the offending instruction. Normally when
a system call or gem5 op is triggered, the PC has not advanced because
the instruction hasn't actually finished executing. This means that if
a gem5 op, and by extension a system call in SE mode, want to advance
the PC to the instruction after the gem5 op, they have to check whether
they were triggered from KVM.

To avoid having to special case these sorts of situations (currently
only in the clone system call), we can have the code which dispatches to
gem5 ops from KVM adjust the next PC so that it points to what the
current PC is. That way the PC can be advanced unconditionally, and will
point to the instruction after the one that triggered the call.

To be fully consistent, we would also need to adjust the current PC.
That would be non-trivial since we'd have to figure out where the
current instruction started, and that may not even be possible to
unambiguously determine given x86's instruction structure. Then we would
also need to restore the original PC to avoid confusing KVM.

Change-Id: I9ef90b2df8e27334dedc25c59eb45757f7220eea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38486
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove full system checks from some pseudo insts.

These pseudo insts are less useful outside of full system, but they
should all still work. Removing this check makes it possible to, for
instance, test them in syscall emulation mode, and removes another
difference between the two styles of simulation.

Change-Id: Ia7d29bfc6f7c5c236045d151930fc171a6966799
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38485
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix const copy of addr range in AbstractController

Clang 10 throws the following error:
  loop variable 'addr_range' of type 'const AddrRange' creates a
  copy from type 'const AddrRange' [-Werror,-Wrange-loop-construct]

  note: use reference type 'const AddrRange &' to prevent copying

Issue introduced by c7fabb979c09864ab47ae848381d6797b45a4cc6.

Change-Id: I43e8d613eb5069d5ce9cb12ddec18cba0a3847f6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38495
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Align the Substream naming in Request

Change-Id: Iac6a18d8872c7df4ade8ecf8914fa807cc3584e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38457
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Change assert to use flag test functions in Request

Change-Id: Id999d39959557196877be9b6469be332391c7dae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38456
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add missing flag test functions to Request

Change-Id: I800c45c855332a2dd1ec5f31b135db62181e5204
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38455
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Update stats for LTAGE bpred

Updated stats in ltage.hh and ltage.cc to use new style stats.

Change-Id: I5f676381fce6f3a0b6abc6044577540e561dcd7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36335
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Number of TLBs equal to number of CUs

The n_cu variable in GPUTLBConifig.py did not take
the number of CUs into consideration and instead
calculated the number of TLBs using cu_per_sa,
sa_per_complex, num_gpu_complexes. Thus changing
the number of cus (n_cus) and none of the other flags
resulted in a  segmentation fault since the required
TLBs were not being instantiated

Change-Id: I569a4e6dc7db9b7a81aeede5ac68aacc0f400a5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32035
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm,kvm: missed rename of MISCREG_HYP in kvm/armv8_cpu.cc

A recent checkin changed the names of some of the MISCREGs.
One of them was missed and wont compile. This fixes to the new name.

Change-Id: I746f9dea44bc50819a0d30f62dcc3a46380f80c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38358
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,stats: Update stats for tage_sc_l to new style stats

Updated tage_sc_l.hh and tage_sc_l.cc to use new style stats.

Change-Id: If172c95bb728c7c3748269469781212ef1da6f32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36336
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Trivikram Reddy <tvreddy@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a simple junit test for the gem5 ops java wrapper.

If possible, this gets built into the jar which also holds the wrapper.
It can be run on its own through its own main function, or through the
junit mechanism directly.

Change-Id: Iaec7f6deb26bbad75da027c71edca50ef25697cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28181
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

util: Rework some checks in the m5 util scons to use Configure().

This is the official scons way to check for things on the system. This
adds two custom checks, one for java packages and one for pkg-config
packages. This change also adds a check for the org.junit java package
which is/will be used for a test for the java wrapper.

Change-Id: I59ca559f257a4c671e9b72a50b5635b5eb61ee69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28180
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

base-stats: Print the name of stats sharing the same name

Having stats of the same name within the same group result in an error.
This commit adds the name to the error message to make it easier to find
the Stats::Group caused the error.

Change-Id: I4010d5d949d1c943d2dd1e2fca0aafcbf62e3ee1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38337
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: term, remove install target

Installing the term utility within the host filesystem is an unlikely
scenario. Most times, the utility will be used in place or trivially
copied to a local directory within the PATH.

Furthermore, the install target hardcoded a privileged installation,
which is a non-standard and insecure technique.

Change-Id: I1592a304017c6b24a9421aa353229fb5a5baae43
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38415
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,arch-gcn3,arch-x86: Changed X86 testlib tests to GCN3_X86

In an effort to get better test coverage, we've changed all X86 tests to
use GCN3_X86. This will, as a minimum, ensure that GCN3 is regularly
compiled. GCN3_X86 is a superset of X86 and all X86 tests should pass on
GCN3_X86.

Change-Id: I2684edfc4e48c3e311a400231293a9e04c701130
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38279
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Standardized used of the ISA constants tags

Change-Id: I4a3966168a1d159bf4ac4cc3148e9c7a43c880e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38278
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Removing cloudbuild_presubmit.yaml

This is not used. It can be removed.

Change-Id: I2e25a5407ca70a18b4e619f4e65b69b98c873511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38375
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: MinorCPU not updating cycle counter value

By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.

For more info check the following email thread in gem5-users:

https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html

Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util: More doc for the Gerrit bot, add padding time to query age

The following changes were made:
- Improve the wording of comments in the Python files and of the
documentation in the README file.
- Add 10 seconds to the query age so that the bot wouldn't miss
any new changes that could be missed due to time difference between
the Gerrit server and the bot.

Change-Id: Ic75f9572653a248230a8b4b0bd360a8d22efd371
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38155
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: able to define resource stalls handlers

Input ports can specify a custom handler that is called
on resource stalls. The handler should return 'true' to
indicate the stall was handled and new messages from that
queue can be processed on that cycle. When it returns
'false' or no handler is defined, a resource stall is
generated.

Handlers are defined using the 'rsc_stall_handler' (for
resource stalls) and the 'prot_stall_handler' (for
protocol stalls) parameters. For example:

in_port(mandatory_in, RubyRequest, mandatoryQueue,
        rsc_stall_handler=mandatory_in_stall_handler) {
    ...
}

bool mandatory_in_stall_handler() {
    // Do something here to handle the stall !
    return true;
    // or return false if we don't want to do anything
}

Note: this patch required a change to the generate()
functions interface in the SLICC compiler, so we
could propagate a reference to the in_port to the
appropriate generate() functions. The updated interface
allows passing and forwarding of keyword arguments.

Change-Id: I3481d130d5eb411e6760a54d098d3da5de511c86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31265
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,tests: use Sequencer port connect methods

This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.

Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
and scripts in which the obj connected to the RubySequencer is not a
BaseCPU (e.g. the tests scripts) were not changed as they require a
non-standard port wireup.

Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31418
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: functions for connecting sequencer ports

Added functions for connecting the sequencer and cpu ports.
Using these functions instead of wiring up the ports directly allow
protocols to provide specialized sequencer implementations. For
instance, connecting the cpu icache_port and dcache_port to
different sequencer ports or to different sequencers.

A follow-up patch will update the configurations to use these
functions.

Change-Id: I2d8db8bbfb05c731c0e549f482a9ab93f341474b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31417
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Convert RISCV to use local reg index storage.

This was mostly straightforward, except that the micro and macro op
classes need to be seperated for AMO classes so that the reg_idx_arr_decl
will have the right sizes.

Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36881
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>