git.libre-soc.org Git - gem5.git/commit

author	Shivani Parekh <shparekh@ucdavis.edu>
	Mon, 24 Aug 2020 18:47:44 +0000 (11:47 -0700)
committer	Shivani Parekh <shparekh@ucdavis.edu>
	Thu, 10 Sep 2020 23:02:28 +0000 (23:02 +0000)
commit	392c1ced53827198652f5eda58e1874246b024f4
tree	70afdd0c6a34a5ca8973f24454d852faf0a23d9e	tree
parent	468b343837b3d9e1d638a09d80125371c0836013	commit \| diff

misc: Replaced master/slave terminology

Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

257 files changed:

configs/common/FSConfig.py		diff \| blob \| history
src/arch/arm/fastmodel/FastModel.py		diff \| blob \| history
src/arch/arm/fastmodel/GIC/FastModelGIC.py		diff \| blob \| history
src/arch/arm/isa.cc		diff \| blob \| history
src/arch/arm/stage2_lookup.hh		diff \| blob \| history
src/arch/arm/stage2_mmu.cc		diff \| blob \| history
src/arch/arm/stage2_mmu.hh		diff \| blob \| history
src/arch/arm/table_walker.cc		diff \| blob \| history
src/arch/arm/table_walker.hh		diff \| blob \| history
src/arch/arm/tlb.cc		diff \| blob \| history
src/arch/arm/tlb.hh		diff \| blob \| history
src/arch/arm/tracers/tarmac_parser.cc		diff \| blob \| history
src/arch/gcn3/gpu_mem_helpers.hh		diff \| blob \| history
src/arch/gcn3/insts/op_encodings.hh		diff \| blob \| history
src/arch/generic/BaseTLB.py		diff \| blob \| history
src/arch/isa_parser.py		diff \| blob \| history
src/arch/riscv/pagetable_walker.cc		diff \| blob \| history
src/arch/riscv/pagetable_walker.hh		diff \| blob \| history
src/arch/x86/X86LocalApic.py		diff \| blob \| history
src/arch/x86/interrupts.cc		diff \| blob \| history
src/arch/x86/interrupts.hh		diff \| blob \| history
src/arch/x86/pagetable_walker.cc		diff \| blob \| history
src/arch/x86/pagetable_walker.hh		diff \| blob \| history
src/cpu/BaseCPU.py		diff \| blob \| history
src/cpu/base.cc		diff \| blob \| history
src/cpu/base.hh		diff \| blob \| history
src/cpu/base_dyn_inst.hh		diff \| blob \| history
src/cpu/checker/cpu.cc		diff \| blob \| history
src/cpu/checker/cpu.hh		diff \| blob \| history
src/cpu/checker/cpu_impl.hh		diff \| blob \| history
src/cpu/kvm/base.cc		diff \| blob \| history
src/cpu/kvm/x86_cpu.cc		diff \| blob \| history
src/cpu/minor/fetch1.cc		diff \| blob \| history
src/cpu/minor/lsq.cc		diff \| blob \| history
src/cpu/o3/commit_impl.hh		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/fetch_impl.hh		diff \| blob \| history
src/cpu/o3/lsq.hh		diff \| blob \| history
src/cpu/o3/lsq_impl.hh		diff \| blob \| history
src/cpu/simple/atomic.cc		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history
src/cpu/simple/probes/simpoint.cc		diff \| blob \| history
src/cpu/simple/timing.cc		diff \| blob \| history
src/cpu/testers/directedtest/DirectedGenerator.cc		diff \| blob \| history
src/cpu/testers/directedtest/DirectedGenerator.hh		diff \| blob \| history
src/cpu/testers/directedtest/InvalidateGenerator.cc		diff \| blob \| history
src/cpu/testers/directedtest/RubyDirectedTester.py		diff \| blob \| history
src/cpu/testers/directedtest/SeriesRequestGenerator.cc		diff \| blob \| history
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc		diff \| blob \| history
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh		diff \| blob \| history
src/cpu/testers/memtest/memtest.cc		diff \| blob \| history
src/cpu/testers/memtest/memtest.hh		diff \| blob \| history
src/cpu/testers/rubytest/Check.cc		diff \| blob \| history
src/cpu/testers/rubytest/RubyTester.cc		diff \| blob \| history
src/cpu/testers/rubytest/RubyTester.hh		diff \| blob \| history
src/cpu/testers/rubytest/RubyTester.py		diff \| blob \| history
src/cpu/testers/traffic_gen/BaseTrafficGen.py		diff \| blob \| history
src/cpu/testers/traffic_gen/base.cc		diff \| blob \| history
src/cpu/testers/traffic_gen/base.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/base_gen.cc		diff \| blob \| history
src/cpu/testers/traffic_gen/base_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/dram_gen.cc		diff \| blob \| history
src/cpu/testers/traffic_gen/dram_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/dram_rot_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/exit_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/hybrid_gen.cc		diff \| blob \| history
src/cpu/testers/traffic_gen/hybrid_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/idle_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/linear_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/nvm_gen.cc		diff \| blob \| history
src/cpu/testers/traffic_gen/nvm_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/random_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/trace_gen.hh		diff \| blob \| history
src/cpu/testers/traffic_gen/traffic_gen.hh		diff \| blob \| history
src/cpu/trace/trace_cpu.cc		diff \| blob \| history
src/cpu/trace/trace_cpu.hh		diff \| blob \| history
src/dev/arm/RealView.py		diff \| blob \| history
src/dev/arm/SConscript		diff \| blob \| history
src/dev/arm/SMMUv3.py		diff \| blob \| history
src/dev/arm/UFSHostDevice.py		diff \| blob \| history
src/dev/arm/amba.hh		diff \| blob \| history
src/dev/arm/gic_v3_its.cc		diff \| blob \| history
src/dev/arm/gic_v3_its.hh		diff \| blob \| history
src/dev/arm/smmu_v3.cc		diff \| blob \| history
src/dev/arm/smmu_v3.hh		diff \| blob \| history
src/dev/arm/smmu_v3_deviceifc.cc	[new file with mode: 0644]	blob
src/dev/arm/smmu_v3_deviceifc.hh	[new file with mode: 0644]	blob
src/dev/arm/smmu_v3_events.cc		diff \| blob \| history
src/dev/arm/smmu_v3_events.hh		diff \| blob \| history
src/dev/arm/smmu_v3_ports.cc		diff \| blob \| history
src/dev/arm/smmu_v3_ports.hh		diff \| blob \| history
src/dev/arm/smmu_v3_proc.cc		diff \| blob \| history
src/dev/arm/smmu_v3_proc.hh		diff \| blob \| history
src/dev/arm/smmu_v3_slaveifc.cc	[deleted file]	blob \| history
src/dev/arm/smmu_v3_slaveifc.hh	[deleted file]	blob \| history
src/dev/arm/smmu_v3_transl.cc		diff \| blob \| history
src/dev/arm/smmu_v3_transl.hh		diff \| blob \| history
src/dev/arm/vgic.cc		diff \| blob \| history
src/dev/dma_device.cc		diff \| blob \| history
src/dev/dma_device.hh		diff \| blob \| history
src/dev/mips/Malta.py		diff \| blob \| history
src/dev/net/dist_iface.cc		diff \| blob \| history
src/dev/net/dist_iface.hh		diff \| blob \| history
src/dev/net/tcp_iface.cc		diff \| blob \| history
src/dev/pci/CopyEngine.py		diff \| blob \| history
src/dev/serial/terminal.cc		diff \| blob \| history
src/dev/sparc/T1000.py		diff \| blob \| history
src/dev/storage/Ide.py		diff \| blob \| history
src/dev/storage/ide_ctrl.cc		diff \| blob \| history
src/dev/storage/ide_ctrl.hh		diff \| blob \| history
src/dev/storage/ide_disk.hh		diff \| blob \| history
src/dev/x86/I82094AA.py		diff \| blob \| history
src/dev/x86/Pc.py		diff \| blob \| history
src/dev/x86/SouthBridge.py		diff \| blob \| history
src/dev/x86/i82094aa.cc		diff \| blob \| history
src/dev/x86/i82094aa.hh		diff \| blob \| history
src/dev/x86/i8259.cc		diff \| blob \| history
src/dev/x86/i8259.hh		diff \| blob \| history
src/dev/x86/intdev.hh		diff \| blob \| history
src/gpu-compute/GPU.py		diff \| blob \| history
src/gpu-compute/X86GPUTLB.py		diff \| blob \| history
src/gpu-compute/compute_unit.cc		diff \| blob \| history
src/gpu-compute/compute_unit.hh		diff \| blob \| history
src/gpu-compute/fetch_unit.cc		diff \| blob \| history
src/gpu-compute/gpu_tlb.cc		diff \| blob \| history
src/gpu-compute/shader.cc		diff \| blob \| history
src/gpu-compute/tlb_coalescer.cc		diff \| blob \| history
src/gpu-compute/tlb_coalescer.hh		diff \| blob \| history
src/learning_gem5/part2/SimpleCache.py		diff \| blob \| history
src/learning_gem5/part2/simple_cache.cc		diff \| blob \| history
src/learning_gem5/part2/simple_cache.hh		diff \| blob \| history
src/mem/AddrMapper.py		diff \| blob \| history
src/mem/Bridge.py		diff \| blob \| history
src/mem/CommMonitor.py		diff \| blob \| history
src/mem/DRAMSim2.py		diff \| blob \| history
src/mem/MemChecker.py		diff \| blob \| history
src/mem/MemCtrl.py		diff \| blob \| history
src/mem/MemDelay.py		diff \| blob \| history
src/mem/SerialLink.py		diff \| blob \| history
src/mem/SimpleMemory.py		diff \| blob \| history
src/mem/XBar.py		diff \| blob \| history
src/mem/abstract_mem.cc		diff \| blob \| history
src/mem/abstract_mem.hh		diff \| blob \| history
src/mem/addr_mapper.cc		diff \| blob \| history
src/mem/addr_mapper.hh		diff \| blob \| history
src/mem/bridge.cc		diff \| blob \| history
src/mem/bridge.hh		diff \| blob \| history
src/mem/cache/base.cc		diff \| blob \| history
src/mem/cache/base.hh		diff \| blob \| history
src/mem/cache/cache.cc		diff \| blob \| history
src/mem/cache/cache_blk.cc		diff \| blob \| history
src/mem/cache/cache_blk.hh		diff \| blob \| history
src/mem/cache/noncoherent_cache.cc		diff \| blob \| history
src/mem/cache/prefetch/Prefetcher.py		diff \| blob \| history
src/mem/cache/prefetch/base.cc		diff \| blob \| history
src/mem/cache/prefetch/base.hh		diff \| blob \| history
src/mem/cache/prefetch/queued.cc		diff \| blob \| history
src/mem/cache/prefetch/queued.hh		diff \| blob \| history
src/mem/cache/prefetch/stride.cc		diff \| blob \| history
src/mem/cache/prefetch/stride.hh		diff \| blob \| history
src/mem/cache/tags/base.cc		diff \| blob \| history
src/mem/cache/tags/base.hh		diff \| blob \| history
src/mem/cache/tags/sector_blk.cc		diff \| blob \| history
src/mem/cache/tags/sector_blk.hh		diff \| blob \| history
src/mem/coherent_xbar.cc		diff \| blob \| history
src/mem/coherent_xbar.hh		diff \| blob \| history
src/mem/comm_monitor.cc		diff \| blob \| history
src/mem/comm_monitor.hh		diff \| blob \| history
src/mem/dramsim2.cc		diff \| blob \| history
src/mem/dramsim2.hh		diff \| blob \| history
src/mem/dramsim3.cc		diff \| blob \| history
src/mem/dramsim3.hh		diff \| blob \| history
src/mem/external_master.cc		diff \| blob \| history
src/mem/external_master.hh		diff \| blob \| history
src/mem/external_slave.hh		diff \| blob \| history
src/mem/hmc_controller.cc		diff \| blob \| history
src/mem/hmc_controller.hh		diff \| blob \| history
src/mem/mem_checker_monitor.cc		diff \| blob \| history
src/mem/mem_checker_monitor.hh		diff \| blob \| history
src/mem/mem_ctrl.cc		diff \| blob \| history
src/mem/mem_ctrl.hh		diff \| blob \| history
src/mem/mem_delay.cc		diff \| blob \| history
src/mem/mem_delay.hh		diff \| blob \| history
src/mem/mem_interface.cc		diff \| blob \| history
src/mem/mem_interface.hh		diff \| blob \| history
src/mem/mem_master.hh	[deleted file]	blob \| history
src/mem/mem_requestor.hh	[new file with mode: 0644]	blob
src/mem/noncoherent_xbar.cc		diff \| blob \| history
src/mem/noncoherent_xbar.hh		diff \| blob \| history
src/mem/packet.hh		diff \| blob \| history
src/mem/packet_queue.cc		diff \| blob \| history
src/mem/packet_queue.hh		diff \| blob \| history
src/mem/port.cc		diff \| blob \| history
src/mem/port_proxy.cc		diff \| blob \| history
src/mem/probes/MemTraceProbe.py		diff \| blob \| history
src/mem/probes/mem_trace.cc		diff \| blob \| history
src/mem/qos/QoSMemCtrl.py		diff \| blob \| history
src/mem/qos/QoSPolicy.py		diff \| blob \| history
src/mem/qos/mem_ctrl.cc		diff \| blob \| history
src/mem/qos/mem_ctrl.hh		diff \| blob \| history
src/mem/qos/mem_sink.cc		diff \| blob \| history
src/mem/qos/mem_sink.hh		diff \| blob \| history
src/mem/qos/policy.cc		diff \| blob \| history
src/mem/qos/policy.hh		diff \| blob \| history
src/mem/qos/policy_fixed_prio.cc		diff \| blob \| history
src/mem/qos/policy_fixed_prio.hh		diff \| blob \| history
src/mem/qos/policy_pf.cc		diff \| blob \| history
src/mem/qos/policy_pf.hh		diff \| blob \| history
src/mem/qos/q_policy.cc		diff \| blob \| history
src/mem/qos/q_policy.hh		diff \| blob \| history
src/mem/qport.hh		diff \| blob \| history
src/mem/request.hh		diff \| blob \| history
src/mem/ruby/network/MessageBuffer.py		diff \| blob \| history
src/mem/ruby/network/Network.py		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.cc		diff \| blob \| history
src/mem/ruby/slicc_interface/AbstractController.hh		diff \| blob \| history
src/mem/ruby/system/CacheRecorder.cc		diff \| blob \| history
src/mem/ruby/system/DMASequencer.cc		diff \| blob \| history
src/mem/ruby/system/GPUCoalescer.cc		diff \| blob \| history
src/mem/ruby/system/GPUCoalescer.hh		diff \| blob \| history
src/mem/ruby/system/GPUCoalescer.py		diff \| blob \| history
src/mem/ruby/system/HTMSequencer.cc		diff \| blob \| history
src/mem/ruby/system/RubyPort.cc		diff \| blob \| history
src/mem/ruby/system/RubyPort.hh		diff \| blob \| history
src/mem/ruby/system/RubySystem.cc		diff \| blob \| history
src/mem/ruby/system/RubySystem.hh		diff \| blob \| history
src/mem/ruby/system/Sequencer.py		diff \| blob \| history
src/mem/ruby/system/VIPERCoalescer.cc		diff \| blob \| history
src/mem/serial_link.cc		diff \| blob \| history
src/mem/serial_link.hh		diff \| blob \| history
src/mem/simple_mem.cc		diff \| blob \| history
src/mem/simple_mem.hh		diff \| blob \| history
src/mem/snoop_filter.cc		diff \| blob \| history
src/mem/snoop_filter.hh		diff \| blob \| history
src/mem/token_port.cc		diff \| blob \| history
src/mem/token_port.hh		diff \| blob \| history
src/mem/tport.cc		diff \| blob \| history
src/mem/tport.hh		diff \| blob \| history
src/mem/translating_port_proxy.cc		diff \| blob \| history
src/mem/xbar.cc		diff \| blob \| history
src/mem/xbar.hh		diff \| blob \| history
src/python/m5/SimObject.py		diff \| blob \| history
src/python/m5/params.py		diff \| blob \| history
src/python/m5/util/dot_writer.py		diff \| blob \| history
src/sim/cxx_config.hh		diff \| blob \| history
src/sim/cxx_manager.cc		diff \| blob \| history
src/sim/cxx_manager.hh		diff \| blob \| history
src/sim/probe/mem.hh		diff \| blob \| history
src/sim/system.cc		diff \| blob \| history
src/sim/system.hh		diff \| blob \| history
src/systemc/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h		diff \| blob \| history
src/systemc/tlm_bridge/TlmBridge.py		diff \| blob \| history
src/systemc/tlm_bridge/gem5_to_tlm.cc		diff \| blob \| history
src/systemc/tlm_bridge/gem5_to_tlm.hh		diff \| blob \| history
src/systemc/tlm_bridge/tlm_to_gem5.cc		diff \| blob \| history
src/systemc/tlm_bridge/tlm_to_gem5.hh		diff \| blob \| history
tests/gem5/x86-boot-tests/system/system.py		diff \| blob \| history

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