src/mem/ruby/system/Sequencer.py

   1 # Copyright (c) 2009 Advanced Micro Devices, Inc.
   2 # Copyright (c) 2020 ARM Limited
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27
  28 from m5.params import *
  29 from m5.proxy import *
  30 from m5.objects.ClockedObject import ClockedObject
  31
  32 class RubyPort(ClockedObject):
  33    type = 'RubyPort'
  34    abstract = True
  35    cxx_header = "mem/ruby/system/RubyPort.hh"
  36    version = Param.Int(0, "")
  37
  38    response_ports = VectorResponsePort("CPU response port")
  39    slave     = DeprecatedParam(response_ports,
  40                         '`slave` is now called `response_ports`')
  41    request_ports = VectorRequestPort("CPU request port")
  42    master    = DeprecatedParam(request_ports,
  43                         '`master` is now called `request_ports`')
  44    pio_request_port = RequestPort("Ruby pio request port")
  45    pio_master_port  = DeprecatedParam(pio_request_port,
  46                         '`pio_master_port` is now called `pio_request_port`')
  47    mem_request_port = RequestPort("Ruby mem request port")
  48    mem_master_port  = DeprecatedParam(mem_request_port,
  49                         '`mem_master_port` is now called `mem_request_port`')
  50    pio_response_port = ResponsePort("Ruby pio response port")
  51    pio_slave_port    = DeprecatedParam(pio_response_port,
  52                         '`pio_slave_port` is now called `pio_response_port`')
  53
  54    using_ruby_tester = Param.Bool(False, "")
  55    no_retry_on_stall = Param.Bool(False, "")
  56    ruby_system = Param.RubySystem(Parent.any, "")
  57    system = Param.System(Parent.any, "system object")
  58    support_data_reqs = Param.Bool(True, "data cache requests supported")
  59    support_inst_reqs = Param.Bool(True, "inst cache requests supported")
  60    is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
  61
  62 class RubyPortProxy(RubyPort):
  63    type = 'RubyPortProxy'
  64    cxx_header = "mem/ruby/system/RubyPortProxy.hh"
  65
  66 class RubySequencer(RubyPort):
  67    type = 'RubySequencer'
  68    cxx_class = 'Sequencer'
  69    cxx_header = "mem/ruby/system/Sequencer.hh"
  70
  71    icache = Param.RubyCache("")
  72    dcache = Param.RubyCache("")
  73
  74    max_outstanding_requests = Param.Int(16,
  75        "max requests (incl. prefetches) outstanding")
  76    deadlock_threshold = Param.Cycles(500000,
  77        "max outstanding cycles for a request before deadlock/livelock declared")
  78    garnet_standalone = Param.Bool(False, "")
  79    # id used by protocols that support multiple sequencers per controller
  80    # 99 is the dummy default value
  81    coreid = Param.Int(99, "CorePair core id")
  82
  83 class RubyHTMSequencer(RubySequencer):
  84    type = 'RubyHTMSequencer'
  85    cxx_class = 'HTMSequencer'
  86    cxx_header = "mem/ruby/system/HTMSequencer.hh"
  87
  88 class DMASequencer(RubyPort):
  89    type = 'DMASequencer'
  90    cxx_header = "mem/ruby/system/DMASequencer.hh"
  91    max_outstanding_requests = Param.Int(64, "max outstanding requests")