src/dev/arm/SMMUv3.py

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  35
  36 from m5.params import *
  37 from m5.proxy import *
  38 from m5.util.fdthelper import *
  39 from m5.SimObject import *
  40 from m5.objects.ClockedObject import ClockedObject
  41
  42 class SMMUv3DeviceInterface(ClockedObject):
  43     type = 'SMMUv3DeviceInterface'
  44     cxx_header = 'dev/arm/smmu_v3_deviceifc.hh'
  45
  46     device_port = ResponsePort('Device port')
  47     slave     = DeprecatedParam(device_port,
  48                                 '`slave` is now called `device_port`')
  49     ats_mem_side_port = RequestPort('ATS mem side port,'
  50                                 'sends requests and receives responses')
  51     ats_master   = DeprecatedParam(ats_mem_side_port,
  52                         '`ats_master` is now called `ats_mem_side_port`')
  53     ats_dev_side_port  = ResponsePort('ATS dev_side_port,'
  54                                 'sends responses and receives requests')
  55     ats_slave     = DeprecatedParam(ats_dev_side_port,
  56                         '`ats_slave` is now called `ats_dev_side_port`')
  57
  58     port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
  59     wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
  60     xlate_slots = Param.Unsigned(16, 'Translation slots')
  61
  62     utlb_entries = Param.Unsigned(32, 'Micro TLB size (entries)')
  63     utlb_assoc = Param.Unsigned(0, 'Micro TLB associativity (0=full)')
  64     utlb_policy = Param.String('rr', 'Micro TLB replacement policy')
  65     utlb_enable = Param.Bool(True, 'Micro TLB enable')
  66     utlb_lat = Param.Cycles(1, 'Micro TLB lookup latency')
  67     utlb_slots = Param.Cycles(1, 'Micro TLB lookup slots')
  68
  69     tlb_entries = Param.Unsigned(2048, 'Main TLB size (entries)')
  70     tlb_assoc = Param.Unsigned(4, 'Main TLB associativity (0=full)')
  71     tlb_policy = Param.String('rr', 'Main TLB replacement policy')
  72     tlb_enable = Param.Bool(True, 'Main TLB enable')
  73     tlb_lat = Param.Cycles(3, 'Main TLB lookup latency')
  74     tlb_slots = Param.Cycles(3, 'Main TLB lookup slots')
  75
  76     prefetch_enable = Param.Bool(False,
  77         'Enable prefetch')
  78     prefetch_reserve_last_way = Param.Bool(True,
  79         'Reserve last way of the main TLB for prefetched entries')
  80
  81 class SMMUv3(ClockedObject):
  82     type = 'SMMUv3'
  83     cxx_header = 'dev/arm/smmu_v3.hh'
  84
  85     request = RequestPort('Request port')
  86     walker = RequestPort(
  87         'Request port for SMMU initiated HWTW requests (optional)')
  88     control = ResponsePort(
  89         'Control port for accessing memory-mapped registers')
  90     sample_period = Param.Clock('10us', 'Stats sample period')
  91     reg_map = Param.AddrRange('Address range for control registers')
  92     system = Param.System(Parent.any, "System this device is part of")
  93
  94     device_interfaces = VectorParam.SMMUv3DeviceInterface([],
  95                                         "Responder interfaces")
  96
  97     # RESPONDER INTERFACE<->SMMU link parameters
  98     ifc_smmu_lat = Param.Cycles(8, 'IFC to SMMU communication latency')
  99     smmu_ifc_lat = Param.Cycles(8, 'SMMU to IFC communication latency')
 100
 101     # SMMU parameters
 102     xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
 103     ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
 104
 105     request_port_width = Param.Unsigned(16,
 106         'Request port width in bytes (= 1 beat)')
 107
 108     tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
 109     tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
 110     tlb_policy = Param.String('rr', 'TLB replacement policy')
 111     tlb_enable = Param.Bool(False, 'TLB enable')
 112     tlb_lat = Param.Cycles(3, 'TLB lookup latency')
 113     tlb_slots = Param.Cycles(3, 'TLB lookup slots')
 114
 115     cfg_entries = Param.Unsigned(64, 'Config cache size (entries)')
 116     cfg_assoc = Param.Unsigned(4, 'Config cache associativity (0=full)')
 117     cfg_policy = Param.String('rr', 'Config cache replacement policy')
 118     cfg_enable = Param.Bool(True, 'Config cache enable')
 119     cfg_lat = Param.Cycles(3, 'Config cache lookup latency')
 120     cfg_slots = Param.Cycles(3, 'Config cache lookup slots')
 121
 122     ipa_entries = Param.Unsigned(128, 'IPA cache size (entries)')
 123     ipa_assoc = Param.Unsigned(4, 'IPA cache associativity (0=full)')
 124     ipa_policy = Param.String('rr', 'IPA cache replacement policy')
 125     ipa_enable = Param.Bool(False, 'IPA cache enable')
 126     ipa_lat = Param.Cycles(3, 'IPA cache lookup lantency')
 127     ipa_slots = Param.Cycles(3, 'IPA cache lookup slots')
 128
 129     walk_S1L0 = Param.Unsigned(4, 'Walk cache S1L0 size (entries)')
 130     walk_S1L1 = Param.Unsigned(28, 'Walk cache S1L1 size (entries)')
 131     walk_S1L2 = Param.Unsigned(348, 'Walk cache S1L2 size (entries)')
 132     walk_S1L3 = Param.Unsigned(4, 'Walk cache S1L3 size (entries)')
 133     walk_S2L0 = Param.Unsigned(4, 'Walk cache S2L0 size (entries)')
 134     walk_S2L1 = Param.Unsigned(28, 'Walk cache S2L1 size (entries)')
 135     walk_S2L2 = Param.Unsigned(92, 'Walk cache S2L2 size (entries)')
 136     walk_S2L3 = Param.Unsigned(4, 'Walk cache S2L3 size (entries)')
 137     walk_assoc = Param.Unsigned(4, 'Walk cache associativity (0=full)')
 138     walk_policy = Param.String('rr', 'Walk cache replacement policy')
 139     walk_enable = Param.Bool(True, 'Walk cache enable')
 140     wc_nonfinal_enable = Param.Bool(False,
 141         'Nonfinal translations use walk cache')
 142     wc_s1_levels = Param.Unsigned(7,
 143         'S1 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 144     wc_s2_levels = Param.Unsigned(7,
 145         'S2 PT levels cached in walk cache (bit 0 is L0, bit 1 is L1, etc)')
 146
 147     walk_lat   = Param.Cycles(4, 'Walk cache lookup latency')
 148     walk_slots = Param.Cycles(4, 'Walk cache lookup slots')
 149
 150     # [28:27] ST_LEVEL = 0b01, 2-level Stream Table supported in addition
 151     # to Linear Stream table.
 152     # [25:24] STALL_MODEL = 0b01, Stall is not supported, all faults
 153     # terminate transaction.
 154     # [22:21] TTENDIAN = 0b10, Endianness support for translation table walks
 155     # (0b10 = Little-endian).
 156     # [19] CD2L = 0b1, 2-level CD table supported.
 157     # [18] VMID16 = 0b1, 16-bit VMID supported.
 158     # [12] ASID16 = 0b1, 16-bit ASID supported.
 159     # [3:2] TTF = 0b10, Translation Table Formats (Stage 1/2)
 160     # (0b10 = AArch64).
 161     # [1] S1P = 0b1, Stage 1 translation supported.
 162     # [0] S2P = 0b1, Stage 2 translation supported.
 163     smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");
 164
 165     # [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
 166     # as log 2 (entries) (0b00101 = 32 entries).
 167     smmu_idr1 = Param.UInt32(0x00A00000, "SMMU_IDR1 register");
 168
 169     smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
 170     smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");
 171     smmu_idr4 = Param.UInt32(0, "SMMU_IDR4 register");
 172
 173     # [6] GRAN64K = 0b1, 64KB translation granule supported.
 174     # [4] GRAN4K = 0b1, 4KB translation granule supported.
 175     # [2:0] OAS = 0b101, Output Address Size (0b101 = 48-bit).
 176     smmu_idr5 = Param.UInt32(0x55, "SMMU_IDR5 register");
 177     smmu_iidr = Param.UInt32(0, "SMMU_IIDR register");
 178
 179     # [7:0] (0 = SMMUv3.0) (1 = SMMUv3.1)
 180     smmu_aidr = Param.UInt32(0, "SMMU_AIDR register");
 181
 182     def generateDeviceTree(self, state):
 183         reg_addr = self.reg_map.start
 184         reg_size = self.reg_map.size()
 185         node = FdtNode("smmuv3@%x" % long(reg_addr))
 186         node.appendCompatible("arm,smmu-v3")
 187         node.append(FdtPropertyWords("reg",
 188             state.addrCells(reg_addr) +
 189             state.sizeCells(reg_size)))
 190         node.append(FdtPropertyWords("#iommu-cells", [1]))
 191
 192         node.appendPhandle(self)
 193         yield node
 194
 195     def connect(self, device):
 196         """
 197         Helper method used to connect the SMMU. The requestor could
 198         be either a dma port (if the SMMU is attached directly to a
 199         dma device), or to a request port (this is the case where the SMMU
 200         is attached to a bridge).
 201         """
 202
 203         device_interface = SMMUv3DeviceInterface()
 204
 205         if hasattr(device, "request_port"):
 206             device_interface.device_port = device.request_port
 207         elif hasattr(device, "dma"):
 208             device_interface.device_port = device.dma
 209         else:
 210             print("Unable to attach SMMUv3\n")
 211             sys.exit(1)
 212
 213         self.device_interfaces.append(device_interface)
 214
 215         # Storing a reference to the smmu to be used when generating
 216         # the binding in the device DTB.
 217         device._iommu = self