summary |
shortlog | log |
commit |
commitdiff |
tree
first ⋅ prev ⋅ next
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:47:42 +0000 (11:47 +0000)]
convert boot rom to bootmem and get first hello_world firmware loaded
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:36:01 +0000 (11:36 +0000)]
add IBM microwatt CC4 license and copyright notices
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 11:33:20 +0000 (11:33 +0000)]
add first cut of verilator simulation, over from microwatt
Luke Kenneth Casson Leighton [Mon, 14 Feb 2022 10:34:48 +0000 (10:34 +0000)]
add verilog build option, make DDR3 PHY optional, add UART pins
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 15:33:58 +0000 (15:33 +0000)]
add future sim option (needs Simulated DDR PHY)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:29 +0000 (14:26 +0000)]
add build to gitignore
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:26:07 +0000 (14:26 +0000)]
rename examples to src
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:25:44 +0000 (14:25 +0000)]
not for any good reason, separate adding the uart16550 verilog source
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:13:51 +0000 (14:13 +0000)]
add MemoryMap to UART16550 (TODO, put that into UART16550 class)
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 14:03:30 +0000 (14:03 +0000)]
start adding uart16550
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:53:08 +0000 (12:53 +0000)]
select a firmware file
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:48:51 +0000 (12:48 +0000)]
allow selection of alternative FPGAs at commandline
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:42:14 +0000 (12:42 +0000)]
add blinky lights so we know FPGA is alive
Luke Kenneth Casson Leighton [Sun, 13 Feb 2022 12:39:11 +0000 (12:39 +0000)]
make firmware and cpu optional for now to get a basic compile
Luke Kenneth Casson Leighton [Sat, 12 Feb 2022 20:57:05 +0000 (20:57 +0000)]
begin a tidyup on the example
core, put addresses of peripherals at the microwatt-expected addresses
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:37:39 +0000 (12:37 +0000)]
resolve imports, whitespace, add Copyright
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:36:33 +0000 (12:36 +0000)]
add crg.py
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:32:32 +0000 (12:32 +0000)]
update contributors
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 12:31:27 +0000 (12:31 +0000)]
sort out license and headers for NLnet and NGI POINTER funded work
Luke Kenneth Casson Leighton [Thu, 10 Feb 2022 11:59:39 +0000 (11:59 +0000)]
add gram soc example and license and contributors
Luke Kenneth Casson Leighton [Wed, 9 Feb 2022 13:24:08 +0000 (13:24 +0000)]
empty first commit