i965/fs: implement i2d and u2d

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: implement d2i and d2u

These need the same treatment as d2f, so generalize our d2f lowering to cover
these too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: implement d2b

v2: Use subscript() instead of stride() (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: implement fsign() for doubles

v2 (Sam):
  - Fix indentation (Kenneth)
  - Simplify code (Kenneth)

v3: Use subscript() instead of stride() (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add null_reg_df

Probably not needed since we fix the dst type of comparisons
automatically, but for consistency with the rest of null_reg_*
functions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: We only support 32-bit integer ALU operations for now

Add asserts so we remember to address this when we enable 64-bit
integer support, as suggested by Connor and Jason.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: handle fp64 opcodes in brw_do_channel_expressions

In the case of the pack opcode we are already doing the
lowering in NIR, so no need to do it here. The unpack opcode
operates on scalars, so it should not be lowered.

In the case of frexp_sig and frexp_exp, they are lowered in
lower_instructions, so we don't have to care about them.

All the remaining opcodes involve conversions from and to doubles
and are business as usual.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add support for f2d and d2f

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add a pass for legalizing d2f

We need to do this late, in order to avoid partial writes during the
optimization loop.

v2: Use subscript() instead of stride().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: fix dst width calculation in CSE

v2 (Sam):
- Fix line width (Topi).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: fix regs_written in LOAD_PAYLOAD for doubles

v2: Account for the stride of the dst (Iago)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: fix is_copy_payload() for doubles

v2 (Sam):
- LOAD_PAYLOAD treats each header source as a 32B block
  regardless of the datatype. Drop the change (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/fs: fix compares for doubles

The destination has to have the same source as the type, or else the
simulator will complain. As a result, we need to emit a CMP that
outputs a 64-bit wide result and then do a strided MOV to pick out the
low 32 bits of each channel.

v2: Use subscript() instead of stride() (Curro)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: extend exec_size halving in the generator

The HW has a restriction that only vertical stride may cross register
boundaries. Previously, this only mattered for SIMD16 instructions where
we needed to use the same regioning parameters as the equivalent SIMD8
instruction but double the exec size. But we need to do the same
splitting for 64-bit instructions as well as instructions with a stride
of 2 (which effectively consume 64 bits per element). Fix up the code to
do the right thing instead of special-casing SIMD16.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: fix assign_constant_locations() for doubles

Uniform doubles will read two registers, in which case we need to mark
both as being live.

v2 (Sam):
  - Use a formula to get the number of registers read with proper
    units (Curro).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: use byte_offset() in offset() for uniforms

This makes things more consistent, and also fixes the offset calculation
for double uniforms.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: handle uniforms in byte_offset()

v2: Do it only for uniforms (Iago)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: fix type_size() for doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: optimize unpack double

When we are actually unpacking from a double that we have previously
packed from its 32-bit components we can bypass the pack operation
and source from its arguments directly.

v2 (Sam):
- Fix line overflow (Topi)
- Bail if the parent instruction's source is not SSA (Connor)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: optimize pack double

When we are actually creating a double using values obtained from a
previous unpack operation we can bypass the unpack and source from
the original double value directly.

v2:
- Style changes (Topi)
- Bail is parent instruction's src is not SSA (Connor)

v3: Use subscript() instead of stride() (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs/nir: translate double pack/unpack

v2 (Sam):
- Fix line overflow (Topi).

v3: Use subscript() instead of stride() (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add a pass for lowering PACK opcodes

v2: Use subscript() instead of stride() (Curro)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add PACK opcode

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Introduce helper to extract a field from each channel of a register.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965/fs: always pass the bitsize to brw_type_for_nir_type()

v2 (Sam):
- Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float()

v3 (Sam):
- Fix line width (Topi).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: add support for printing double immediates

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: don't propagate 64-bit immediates

They can only be used with 1-src instructions, which practically (since
we should've constant-propagated away all 1-src instructions with 64-bit
immediates in NIR) means that they must be kept in separate MOV's and
can't be propagated.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: use the NIR bit size when creating registers

v2 (Iago):
  - Squashed bits from 'support double precission constant operands for
    the implementation of 64-bit emit_load_const'.
  - Do not use BRW_REGISTER_TYPE_D for all 32-bit registers since that breaks
    asserts and functionality for some piglit tests. Just keep 32-bit types
    untouched and add 64-bit support.
  - Use DF instead of Q for 64-bit registers. Otherwise the code we generate
    will use Q sometimes and DF others and we hit unwanted DF/Q conversions,
    so always use DF.

v3 (Sam):
  - Mark 'reg_type' occurrences as const (Topi).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani Palli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: fixup uniform setup for doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: two-argument instructions can only use 32-bit immediates

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: fix brw_abs_immediate() for doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: fix brw_saturate_immediate() for doubles

v2 (Sam):
  - Mark 'size' as const (Topi).
  - Add comment to explain that we do copies 64-bits regardless of the
    type (Topi)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: fix is_zero(), is_one() and is_negative_one() for doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: fix brw_negate_immediate() for doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/eu: add support for DF immediates

v2 (Sam):
  - Remove 'however' from the comment (Topi)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: add support for disassembling DF immediates

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: add support for getting/setting DF immediates

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: add brw_imm_df

v2 (Iago)
  - Fixup accessibility in backend_reg

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/eu: Allow 3-src float ops with doubles

v2:
  - set 3src_src_type for BRW_REGISTER_TYPE_DF (Connor)

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/disasm: fix disasm of 3-src doubles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Tell backend register about double precision type

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani P\344lli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Determine size of double precision float register

This is used to determine how many registers an instruction reads and
writes as well as for offseting register region into a desired component.

v2 (Connor): rebase on master

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Tapani P\344lli <tapani.palli@intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Lower DFRACEXP/DLDEXP

v2 (Connor): rebase on master which moved this to brw_link.cpp
v3 (Sam):
- Only enable DFREXP_DLDEXP_TO_ARITH in process_glsl_ir(). This is
used for doubles. Single floating point op is lowered by NIR.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: use pack/unpackDouble lowering

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: use double lowering pass

v2: also lower trunc, ceil, floor, fract and roundEven (Iago)
v3: also lower mod for doubles (Sam)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

freedreno/ir3: lower lrp when operating with double operands

Lower lrp when operating with double operands because float version of
lrp is also lowered.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: enable lrp lowering for doubles

Broadwell and previous generations does not support lrp instruction
operating with doubles.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

st/glsl_to_tgsi: brown paper bag for the input offsets fix.

Oops, thanks compiler.

Signed-off-by: Dave Airlie <airlied@redhat.com>

glsl: check geometry output vertices limits.

This fixes:
GL45-CTS.geometry_shader.limits.max_output_vertices

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa/vbo: fix check for zero aliases with 2/10/10/10

This fixes:
GL33-CTS.gtf33.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_attrib

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir/print: Print memory qualifiers in a variable declaration

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Apply memory qualifiers to vars inside named block interfaces

This is missing and memory qualifiers are currently being ignored for SSBOs.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

st/glsl_to_tgsi: handle offsets from inputs

This fixes:
GL45-CTS.gpu_shader5.texture_gather_offset_color_repeat

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

scripts: bump git_reviewer.pl --git-min-percent default

Bump up default percentage of commits required to be auto-picked for CC.
Seems from a bit of trial-and-error to come up with a more reasonable
list of CC's this way.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Revert "Revert "i965: Switch to scalar TCS by default.""

This reverts commit bd326c229c528a214c9fda705e7a961cfa49ac9e.

Now that we've fixed the GPU hangs, let's turn it back on.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Actually assign binding table offsets for the TCS.

As far as I can tell, this was just entirely missing...honestly, I'm
not sure how anything worked at all.

Caught by noticing GPU hangs in image load store tests with scalar TCS,
but probably has broader implications.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Clamp "Maximum VP Index" to 1 when gl_ViewportIndex isn't written.

fs_visitor::emit_urb_writes skips writing the VUE header for shaders
that don't write gl_PointSize, gl_Layer, or gl_ViewportIndex.  This
leaves their values uninitialized.  Kristian's nearby comment says:

"But often none of the special varyings that live there are written
 and in that case we can skip writing to the vue header, provided the
 corresponding state properly clamps the values further down the
 pipeline."

However, we were clamping gl_ViewportIndex to [0, 15], so we would end
up using a random viewport.  To fix this, detect when the shader doesn't
write gl_ViewportIndex, and clamp it to [0, 0].

The vec4 backend always writes zeros to the VUE header, so it doesn't
suffer from this problem.  With vec4-style HWord writes, we can write
the header and position together in a single message.  In the FS world,
we would need 4 extra MOVs of 0 and a longer message, or a separate
OWord write.  It's likely cheaper to just clamp the value.

Fixes DiRT Showdown and Bioshock Infinite, which only rendered half of
the screen - the lower left of two triangles.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93054
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/hsw: Fix brw_store_data_imm*

For Gen6 through Haswell dword 1 is MBZ. In gen 8 it becomes part of
the 64-bit address.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Reimplement ARB_transform_feedback2 on Haswell and later.

My old implementation accumulated <start, end> pairs in a buffer,
and eventually processed that data on the CPU.  This meant flushing
the batchbuffer and waiting for it to completely execute before we
could map it, resulting in really long stalls.  We could also run out
of space in the buffer, and have to do this early.

Instead, we can use Haswell's MI_MATH command to do the (end - start)
subtraction, as well as the multiplication by 2 or 3 to convert from
the number of primitives written to the number of vertices written.
We still need to CS stall to read the counters, but otherwise everything
is completely pipelined - there's no CPU<->GPU synchronization required.
It also uses only 80 bytes in the buffer, no matter what.

Improves performance in Manhattan on Skylake GT3e at 800x600 by
6.1086% +/- 0.954166% (n=9).  At 1920x1080, improves performance
by 2.82103% +/- 0.148596% (n=84).

v2: Fix number of primitives -> number of vertices calculation for
    GL_TRIANGLES (I was multiplying by 4 instead of 3.)  Caught by
    Jordan Justen.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Add a brw_load_register_reg64 helper.

It appears that we can't do this in a single command (like we do for
MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about
the command length if I try to combine them.  No matter.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Only enable ARB_query_buffer_object for newer kernels on Haswell.

On Haswell, we need version 6 of the kernel command parser in order to
write the math registers.  Our implementation of ARB_query_buffer_object
heavily relies on MI_MATH, so we should only advertise it when MI_MATH
is available.  We also need MI_LOAD_REGISTER_REG, which requires version
7 of the command parser.

To make these checks easier, introduce a screen->has_mi_math_and_lrr
flag that will be set when both commands are supported.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/objectlabel: don't return info on genned but never bound textures.

This fixes some cases in the CTS KHR debug tests where it uses
glIsTexture to find an invalid ID and then call GetObjectLabel.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

mesa: don't use genned but unnamed xfb objects.

If we try to draw or query an XFB object that hasn't been bound,
we shouldn't return any information.

This fixes a couple if cases in:
GL33-CTS.transform_feedback.api_errors_test

The ObjectLabel test is inspired by another test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*

We don't need them for compute shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/compute: Fix indirect dispatch buffer size check on 32-bit systems

2655265fcba9017e793026c76e490e04db088c8f, but for compute.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

freedreno/ir3: fix fallout from new block iterators

Since this is potentially modifying the block structure of the shader,
it needs the _safe() version of the iterator.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

radeonsi: workaround for tesselation on SI

We request more than 32KB of LDS here, which SI doesn't have. Since LLVM
recently started checking the size of declared LDS allocations, all shaders
involved in tesselation fail to compile on SI.

Note that the entire calculation here seems wrong, given how we calculate
indices for generic attributes, so the number ends up wrong on CI+ as well.
A proper solution is clearly needed, but this patch should serve as a band-aid
for SI in the meantime.

Also note that the real size of the LDS allocation in hardware is independent
from what we tell LLVM, so this is really more of a "cosmetic" change.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95198
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: always allocate export memory for pixel shaders

Experiments with framebuffer-no-attachments type draw calls have shown that
NULL exports stall terribly unless we ensure that export memory is allocated
by the SPI.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: expose performance counters as 64 bit

This is useful for shader-related counters, since they tend to quickly
exceed 32 bits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir/search: fix typo

Signed-off-by: Rob Clark <robclark@freedesktop.org>

gallium: enable intel jitevents profiling

LLVM when configured with "intel jitevents" enabled can inform
VTune about dynamic code, so individual shaders are attributed
profiling data and the resulting assembly can be examined.

Acked-by: Roland Scheidegger <sroland@vmware.com>

swr: Add missing break in query switch statement.

Missed a switch break in query stat collection when refactoring queries.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

freedreno/ir3: allow for additional VS sysval inputs

There are a total of four possible currently, rather than 2.  So we need
to be prepared for the input array to grow by 16 components.  We could
get away with less if we could pack sysval inputs..  and the way this is
handled currently isn't really the nicest thing.  But it's a tactical
fix for an issue hit in:

GL31-CTS.gtf30.GL3Tests.transform_feedback.transform_feedback_vertex_id

Signed-off-by: Rob Clark <robclark@freedesktop.org>

docs: add news item and link release notes for 11.1.4/11.2.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 11.2.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add release notes for 11.2.2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add sha256 checksums for 11.1.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

docs: add release notes for 11.1.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

scons: Improve Python module dependency discovery.

Several NIR scripts were using `from ... import ...` syntax, which wasn't
supported.

Using Python standard libary's modulefinder solves the problem with less
effort and hacks.

Reviewed-by: Brian Paul <brianp@vmware.com>

r300g: add support for PIPE_FORMAT_x8R8G8B8_*

And set endian swap for packed formats the way it should be done
in theory.

This allows big endian to work again, but it can still be buggy.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789

Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

Revert "i965: Always use Y-tiled buffers on SKL+"

This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS.

In order to use Y-tiled buffers, the kernel requires the tiling mode to
be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
it disallows any attempt to infer the buffer's tiling mode.

As the GBM API does not have a way to extract modifiers for a buffer,
this commit broke all users of GBM on SKL+. Revert it for now, until we
get a way to extract modifier information from GBM, and also let GBM
users inform the implementation that it intends to use the modifiers.

This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Hans de Goede <hdegoede@redhat.com>

mesa/shader_query: add missing subroutines cases

ARRAY_SIZE and LOCATION should accept the SUBROUTINE_UNIFORM types.

Fixes:
GL43-CTS.program_interface_query.subroutines-vertex
GL43-CTS.program_interface_query.subroutines-tess-control
GL43-CTS.program_interface_query.subroutines-tess-eval
GL43-CTS.program_interface_query.subroutines-geometry
GL43-CTS.program_interface_query.subroutines-fragment
GL43-CTS.program_interface_query.subroutines-compute

Reviewed-by: Antia Puentes <apuentes@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

spirv: Fix structure splitting with per-vertex interface arrays.

We want to use interface_type, not vtn_var->type.  They're normally
equivalent, but for geometry/tessellation per-vertex interface arrays,
we need to unwrap a level.

Otherwise, we tried to iterate a structure members but instead used
an array length.  If the array length was longer than the number of
fields in the structure, we'd crash.

Fixes the CreatePipelineGeometryInputBlockPositive layer validation
test.

v2: Just use glsl_without_array() on the vtn_var type
    (requested by Jason Ekstrand).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

compiler: Add a C wrapper for glsl_type::without_array().

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: fix some reported undefined left-shifts

One of these is an unsigned bitfield, which I suspect is a false positive, but
gcc 5.3.1 complains about it with -fsanitize=undefined.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: clean left-shift undefined behavior

Shifting into the sign bit of a signed int is undefined behavior.
Unfortunately, there are potentially many places where this happens using
the register macros.

This commit is the result of running

sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g"

on all header files in gallium/{r600,radeon,radeonsi}.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: fix various undefined left shifts into sign bit

Funnily enough, some of these were turned into a compile-time error by gcc
with -fsanitize=undefined ("initializer is not a constant").

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

compiler/glsl: do not downcast list sentinel

This crashes gcc's undefined behaviour sanitizer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/main: fix another undefined left shift

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/main: define _NEW_xxx flags as unsigned shifts

Since 1 << 31 complains about undefined behaviour; the others are changed
only for consistency.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Compute correct LDS size for fragment shaders.

No sure where the 36 came from, but we clearly need at least
48 bytes per attribute per primitive.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

vc4: Add support for loading immediate values in QIR.

This will be used for resetting the uniform stream in the presence of
branching, but may also be useful as an optimization to reduce how many
uniforms we have to copy out per draw call (in exchange for increasing
icache pressure).

vc4: Make vc4_qpu_validate() produce more verbose failures.

Seeing the expansion of a QPU_GET_FIELD in an assert isn't very
informative, and it's hard find what's going wrong without getting a dump
of the instruction that failed.

vc4: Add a small QIR validate pass.

This has caught a couple of bugs during loop development so far, and I
should probably have written it long ago.

vc4: Fix the src count on exp2/log2.

Found by the upcoming QIR validate pass.

vc4: Reuse QPU disasm's cond flags in QIR.

In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.

vc4: When emitting an instruction to an existing temp, mark it non-SSA.

Prevents a bug in the later control-flow support series.

vc4: Make sure that we don't overwrite the signal for PROG_END.

We should have already emitted a NOP due to the last instruction being a
TLB or VPM write.  However, if you disable dead code elimination then you
might get dead code at the end, and that dead code might have the signal
bits set to something non-default, at which point you die in assertion
failure.

nvc0: unreference images when the context is destroyed

Like other resources, we need to unreference all images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>