Chris Wilson [Fri, 1 May 2015 10:25:20 +0000 (11:25 +0100)]
i965: Move pipecontrol workaround bo to brw_pipe_control
With the exception of gen8, the sole user of the workaround bo are for
emitting pipe controls. Move it out of the purview of the batchbuffer
and into the pipecontrol.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Chris Wilson [Wed, 10 Jun 2015 07:28:13 +0000 (08:28 +0100)]
loader: Look for any version of currently linked libudev.so
Since there was an ABI break and linking twice against libudev.so.0 and
libudev.so.1 causes the application to quickly crash, we first check if
the application is currently linked against libudev before dlopening a
local handle. However for backwards/forwards compatability, we need to
inspect the application for current linkage against all known versions
first. Not doing so causes a crash when both libraries are present and
so mesa chooses libudev.so.1 but the application was linked against
libudev.so.0.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Emil Velikov:
I'm ever so slightly conserned that RTLD_NOLOAD is not part of the POSIX
standard, thus it's missing on some platforms (*BSD seems ok, while
Solaris, MacOS are not).
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Chris Wilson [Wed, 29 Apr 2015 12:32:38 +0000 (13:32 +0100)]
i965: Query whether we have kernel support for the TIMESTAMP register once
Move the query for the TIMESTAMP register from context init to the
screen, so that it is only queried once for all contexts.
On 32bit systems, some old kernels trigger a hw bug resulting in the
TIMESTAMP register being shifted and the low 32bits always zero. Detect
this by repeating the read a few times and check the register is
incrementing every 80ns as expected and not stuck on zero (as would be
the case with the buggy kernel/hw.).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Wed, 8 Jul 2015 03:05:45 +0000 (23:05 -0400)]
nvc0: turn sample counts off during blit
Fixes the following piglits:
occlusion_query_meta_fragments
occlusion_query_meta_no_fragments
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Timothy Arceri [Tue, 7 Jul 2015 23:20:40 +0000 (09:20 +1000)]
mesa: use implementation specified MAX_VERTEX_ATTRIBS rather than hardcoded value
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Thu, 2 Jul 2015 03:13:00 +0000 (20:13 -0700)]
i965/vs: Fix matNxM vertex attributes where M != 4.
Matrix vertex attributes have their columns padded out to vec4s, which
I was failing to account for. Scalar NIR expects them to be packed,
however.
Fixes 1256 dEQP tests on Broadwell.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Marek Olšák [Tue, 7 Jul 2015 16:28:31 +0000 (18:28 +0200)]
st/dri: don't set PIPE_BIND_SCANOUT for MSAA surfaces
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91231
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Tue, 7 Jul 2015 19:17:01 +0000 (13:17 -0600)]
gallium/hud: display percentages with % suffix
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 7 Jul 2015 15:15:59 +0000 (09:15 -0600)]
gallium/hud: add PIPE_DRIVER_QUERY_TYPE_MICROSECONDS for HUD
This allows drivers to report queries in units of microseconds and
have the HUD display "us" (microseconds), "ms" (milliseconds) or "s"
(seconds) on the graph.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 7 Jul 2015 15:13:02 +0000 (09:13 -0600)]
gallium/hud: replace byte units flag with pipe_driver_query_type
Instead of using a boolean 'is bytes' value, use the pipe_driver_query_type
enum type. This will let is add support for time values in the next patch.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Mon, 6 Jul 2015 21:28:59 +0000 (15:28 -0600)]
gallium/os: minor whitespace fixes in os_time.h
Trivial.
Francisco Jerez [Mon, 6 Jul 2015 15:55:26 +0000 (18:55 +0300)]
i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.
This was probably disabled due to a combination of several bugs in the
generator code (fixed earlier in this series) and a misunderstanding
of the hardware spec. The documentation for most control flow
instructions mentions among other restrictions:
"Instruction compression is not allowed."
This however doesn't have any implications on 16 wide not being
supported, because none of the control flow instructions have
multi-register operands (control flow instructions are not compressed
on more recent hardware either, except maybe SNB's IF with inline
compare). In fact Gen4-5 had 16-wide control flow masks and stacks,
and the spec mentions in several places that control flow instructions
push and pop 16 channels worth of data -- Otherwise there doesn't seem
to be any indication that it shouldn't work.
Causes no piglit regressions, and gives the following shader-db
results on ILK:
total instructions in shared programs:
4711384 ->
4711384 (0.00%)
instructions in affected programs: 0 -> 0
helped: 0
HURT: 0
GAINED: 1215
LOST: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 6 Jul 2015 16:11:54 +0000 (19:11 +0300)]
i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.
From the hardware docs for the DO instruction:
"Execution size is ignored for this instruction."
My observation on ILK hardware contradicts the spec though, channels
over the execution size of a DO instruction won't enter the loop, and
channels over the execution size of a WHILE instruction will exit the
loop after the first iteration -- The latter is consistent with the
spec though, there's no claim about the execution size being ignored
for the WHILE instruction so it's not completely unexpected that it
has an influence on the evaluation of EMask.
The execute_size argument of brw_DO() shouldn't have any effect on
Gen6 and newer hardware. On Gen4-5 WHILE instructions inherit the
execution size from the matching DO, so this patch should fix them
too. The execution size of BREAK and CONT instructions was already
being set correctly.
Fixes some 50 piglit tests on Gen4-5 when forced to run shaders with
conditional and loop instructions 16-wide,
e.g. shaders/glsl-fs-continue-inside-do-while.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 6 Jul 2015 15:23:57 +0000 (18:23 +0300)]
i965/gen4-5: Set ENDIF dst and src0 fields to the null register.
The hardware docs don't mention explicitly what these fields should
be, but I've verified experimentally on ILK that using a GRF as
destination causes the register to be corrupted when the execution
size of an ENDIF instruction is higher than 8 -- and because the
destination we were using was g0, eventually a hang.
Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with
if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Michel Dänzer [Mon, 6 Jul 2015 08:23:07 +0000 (17:23 +0900)]
radeonsi: Use param export count from si_llvm_export_vs in si_shader_vs
This eliminates the error prone logic in si_shader_vs recalculating this
value.
It also fixes TGSI_SEMANTIC_CLIPDIST outputs incorrectly not being
counted for VS exports. They need to be counted because they are passed
to the pixel shader as parameters as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91193
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Matt Turner [Thu, 25 Jun 2015 23:57:20 +0000 (16:57 -0700)]
mesa: Convert some asserts into STATIC_ASSERT.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Roland Scheidegger [Sat, 4 Jul 2015 01:03:33 +0000 (03:03 +0200)]
gallivm: fix lp_build_compare_ext
The expansion should always be to the same width as the input arguments
no matter what, since these functions should work with any bit width of
the arguments (the sext is a no-op on any sane simd architecture).
Thus, fix the caller expecting differently.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=91222
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Kenneth Graunke [Mon, 6 Jul 2015 18:04:19 +0000 (11:04 -0700)]
mesa: Add a MUST_CHECK macro for __attribute__((warn_unused_result)).
In the kernel, this is called __must_check; all our attribute macros in
Mesa appear to be uppercase, so I went with that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Neil Roberts [Sat, 4 Jul 2015 21:40:59 +0000 (22:40 +0100)]
glsl: Make sure not to dereference NULL
In this bit of code point_five can be NULL if the expression is not a
constant. This fixes it to match the pattern of the rest of the chunk
of code so that it checks for NULLs.
Cc: Matt Turner <mattst88@gmail.com>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Neil Roberts [Sat, 4 Jul 2015 21:40:58 +0000 (22:40 +0100)]
glsl: Add missing check for whether an expression is an add operation
There is a piece of code that is trying to match expressions of the
form (mul (floor (add (abs x) 0.5) (sign x))). However the check for
the add expression wasn't checking whether it had the expected
operation. It looks like this was just an oversight because it doesn't
match the pattern for the rest of the code snippet. The existing line
to check whether add_expr!=NULL was added as part of a coverity fix in
3384179f.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91226
Cc: Matt Turner <mattst88@gmail.com>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 4 Mar 2015 23:46:57 +0000 (15:46 -0800)]
i965: Reserve more batch space to accomodate Gen6 perfmonitors.
Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's
actually 5 DWords on Gen6-7. We've been reserving insufficient space
for performance monitoring on Sandybridge, which means it would likely
break if you used that functionality. (Thankfully, no one does...)
Also, the existing number of 146 was the result of me flubbing up the
arithmetic: it should have actually been 140.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Neil Roberts [Fri, 3 Jul 2015 12:15:21 +0000 (13:15 +0100)]
i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRA
On Gen9+ there is a new bit in 3DSTATE_PS_EXTRA that must be set if
the shader sends a message to the pixel interpolator. This fixes the
interpolateAt* tests on SKL, apart from interpolateatsample-nonconst
but that is not implemented anywhere so it's not a regression.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
Marek Olšák [Fri, 26 Jun 2015 17:01:04 +0000 (19:01 +0200)]
winsys/radeon: use os_wait_until_zero in radeon_bo_set_tiling
Marek Olšák [Sat, 27 Jun 2015 12:03:46 +0000 (14:03 +0200)]
radeonsi: don't flush an empty IB if the only thing we need is a fence
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 26 Jun 2015 22:05:26 +0000 (00:05 +0200)]
gallium/os: add conversion and wait functions for absolute timeouts
Absolute timeouts are used with the amdgpu kernel driver.
It also makes waiting for several variables and fences at the same time
easier (the timeout doesn't have to be recalculated after every wait call).
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 25 Jun 2015 18:39:34 +0000 (20:39 +0200)]
gallium/os: add os_wait_until_zero (v2)
This will be used by radeon and amdgpu winsyses.
Copied from the amdgpu winsys.
v2: use volatile and p_atomic_read
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 26 Jun 2015 17:01:23 +0000 (19:01 +0200)]
gallium/radeon: mark the gpu load thread stop trigger as volatile
Marek Olšák [Sat, 27 Jun 2015 11:57:06 +0000 (13:57 +0200)]
st/mesa: if a fence isn't returned, assume it's signalled
The reason might be that no commands have been submitted before the flush
and the GPU is idle.
Marek Olšák [Fri, 26 Jun 2015 14:34:31 +0000 (16:34 +0200)]
gallium: remove redundant pipe_context::fence_signalled
fence_finish(timeout=0) does the same thing
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Fri, 26 Jun 2015 14:28:53 +0000 (16:28 +0200)]
gallium: use fence_finish instead of fence_signalled in state trackers
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Fri, 26 Jun 2015 11:13:16 +0000 (13:13 +0200)]
gallium: handle fence_finish timeout in various drivers
I copied what fence_signalled does.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Fri, 26 Jun 2015 11:19:45 +0000 (13:19 +0200)]
gallium/docs: remove out-of-date document about D3D11 features
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 24 Jun 2015 09:58:50 +0000 (11:58 +0200)]
radeonsi: fix a hang with DrawTransformFeedback on 4 SE chips
Cc: 10.6 10.5 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christain.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Emil Velikov [Sat, 4 Jul 2015 11:53:22 +0000 (12:53 +0100)]
docs: add news item and link release notes for mesa 10.5.9
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sat, 4 Jul 2015 11:48:39 +0000 (12:48 +0100)]
docs: Add sha256sums for the 10.5.9 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
4a0bd3dcff3c07965828e648e14d89314d262169)
Emil Velikov [Sat, 4 Jul 2015 11:09:10 +0000 (12:09 +0100)]
Add release notes for the 10.5.9 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
7f40d083748f3a8276e08a2fa0ae7149269ea379)
Timothy Arceri [Sat, 14 Mar 2015 01:40:20 +0000 (12:40 +1100)]
glsl: update types for unsized arrays of members
Assigns a new array type based on the max access of
unsized array members. This is to support arrays of arrays.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Sun, 22 Feb 2015 12:35:43 +0000 (23:35 +1100)]
glsl: update assert to support arrays of arrays
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Timothy Arceri [Wed, 27 May 2015 02:02:40 +0000 (12:02 +1000)]
glsl: allow precision qualifiers for AoA
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Jul 2015 23:09:09 +0000 (19:09 -0400)]
nv50/ir: UCMP arguments are float, so make sure modifiers are applied
The first argument to UCMP needs to be compared against 0, but the
latter arguments are treated as float and need to be able to properly
apply neg/abs arguments. Adjust the inferSrcType function accordingly.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Erik Faye-Lund [Fri, 3 Jul 2015 07:46:01 +0000 (09:46 +0200)]
glsl: add a missing call to _mesa_locale_init
After
c61bc6e ("util: port _mesa_strto[df] to C"), "make check"
fails due to a missing _mesa_locale_init. Fixup this oversight,
by moving the stand-alone compiler initializer inside
initialize_context_to_defaults().
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Mario Kleiner [Sun, 28 Jun 2015 01:02:31 +0000 (03:02 +0200)]
winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.
Same problem and fix as for nouveau's ZaphodHeads trouble.
See patch ...
"nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads."
... for reference.
Cc: "10.3 10.4 10.5 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Fri, 3 Jul 2015 14:20:32 +0000 (16:20 +0200)]
r600g: disable single-sample fast color clear due to hangs
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73528
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82186
Cc: 10.4 10.5 10.6 <mesa-stable@lists.freedesktop.org>
Marek Olšák [Wed, 29 Apr 2015 15:57:46 +0000 (17:57 +0200)]
docs/relnotes: document create_context_robustness extensions
Marek Olšák [Wed, 29 Apr 2015 13:27:50 +0000 (15:27 +0200)]
r600g,radeonsi: implement get_device_reset_status
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Wed, 10 Jun 2015 00:50:42 +0000 (02:50 +0200)]
dri/common: allow BGRX sRGB visuals
Marek Olšák [Wed, 10 Jun 2015 00:53:33 +0000 (02:53 +0200)]
mesa: fix sRGB rendering for GLES1
Marek Olšák [Tue, 9 Jun 2015 21:08:57 +0000 (23:08 +0200)]
egl: sort extension lists alphabetically
and add the missing KHR_gl_colorspace case.
Anatoli Antonovitch [Wed, 10 Jun 2015 12:42:31 +0000 (14:42 +0200)]
egl: implement EGL_KHR_gl_texture_3D_image
Most of the code has been in place already.
Rob Clark [Thu, 2 Jul 2015 19:38:34 +0000 (15:38 -0400)]
freedreno/ir3: don't be confused by eliminated indirects
If an instruction using address register value gets eliminated, we need
to remove it from the indirects list, otherwise it causes mayhem in
sched for scheduling address register usage.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 2 Jul 2015 18:59:08 +0000 (14:59 -0400)]
freedreno/ir3: sched fixes for addr register usage
A handful of fixes and cleanups:
1) If we split addr/pred, we need the newly created instruction to
end up in the unscheduled_list
2) Avoid scheduling a write to the address register if there is no
instruction using the address register that is otherwise ready
to schedule. Note that I currently don't bother with the same
logic for predicate register, since the only instructions using
predicate (br/kill) don't take any other src registers, so this
situation should not arise.
3) few other cosmetic cleanups
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 2 Jul 2015 17:52:38 +0000 (13:52 -0400)]
freedreno/ir3: fix indirects tracking
cp would update instr->address but not update the indirects array
resulting in sched getting confused when it had to 'spill' the address
register. Add an ir3_instr_set_address() helper to set instr->address
and also update ir->indirects, and update all places that were writing
instr->address to use helper instead.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Sat, 27 Jun 2015 21:38:57 +0000 (17:38 -0400)]
gallium/ttn: mark location specially in nir for color0-writes-all
We need to distinguish a shader that has separate writes to each MRT
from one which is supposed to write the data from MRT 0 to all the MRTs.
In TGSI this is done with a property. NIR doesn't have that, so encode
it as a funny location and decode on the other end.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Fri, 26 Jun 2015 19:05:32 +0000 (15:05 -0400)]
nir/lower_phis_to_scalar: undef is trivially scalarizable
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Rob Clark [Fri, 26 Jun 2015 23:11:53 +0000 (19:11 -0400)]
gallium/ttn: IN/OUT are only array if ArrayID != 0
Fixes issue with gallium HUD. See this thread for details:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Fri, 26 Jun 2015 23:04:39 +0000 (19:04 -0400)]
tgsi: update docs for ArrayID usage
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Thu, 2 Jul 2015 16:49:19 +0000 (17:49 +0100)]
i965/fs: Don't disable SIMD16 when using the pixel interpolator
There was a comment saying that in SIMD16 mode the pixel interpolator
returns coords interleaved 8 channels at a time and that this requires
extra work to support. However, this interleaved format is exactly
what the PLN instruction requires so I don't think anything needs to
be done to support it apart from removing the line to disable it and
to ensure that the message lengths for the send message are correct.
I am more convinced that this is correct because as it says in the
comment this interleaved output is identical to what is given in the
thread payload. The code generated to apply the plane equation to
these coordinates is identical on SIMD16 and SIMD8 except that the
dispatch width is larger which implies no special unmangling is
needed.
Perhaps the confusion stems from the fact that the description of the
PLN instruction in the IVB PRM seems to imply that the src1 inputs are
not interleaved so it wouldn't work. However, in the HSW and BDW PRMs,
the pseudo-code is different and looks like it expects the interleaved
format. Mesa doesn't seem to generate different code on IVB to
uninterleave the payload registers and everything is working so I can
only assume that the PRM is wrong.
I tested the interpolateAt tests on HSW and did a full Piglit run on
IVB on there were no regressions.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Jason Ekstrand [Wed, 1 Jul 2015 23:00:08 +0000 (16:00 -0700)]
nir: Don't allow copying SSA destinations
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Ilia Mirkin [Wed, 1 Jul 2015 22:22:23 +0000 (18:22 -0400)]
mesa/prog: relative offsets into constbufs are not constant
The optimization logic relies on being able to read out constbuf values
from program parameters. However that only works if there's no relative
addressing involved.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Mike Stroyan [Wed, 1 Jul 2015 16:16:28 +0000 (10:16 -0600)]
i965: allocate at least 1 BLEND_STATE element
When there are no color buffer render targets, gen6 and gen7 still
use the first BLEND_STATE element to determine alpha test.
gen6_upload_blend_state was allocating zero elements when
ctx->Color.AlphaEnabled was false.
That left _3DSTATE_CC_STATE_POINTERS or _3DSTATE_BLEND_STATE_POINTERS
pointing to random data from some previous brw_state_batch().
That sometimes suppressed depth rendering when those bits
happened to mean COMPAREFUNC_NEVER.
This produced flickering shadows for dota2 reborn.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80500
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 29 Jun 2015 08:44:52 +0000 (10:44 +0200)]
mesa/st: Add checks for signed/unsigned integer conversions in ReadPixels
These checks were in Mesa prior to commit
fbba25bba, but they were
not necessary for the purpose that Mesa intended (check if we could
resolve ReadPixels via memcpy), so that commit took them away.
Unfortunately, it seems that some Gallium drivers rely on these
checks to make the decision of whether they should fallback to Mesa's
implementation of ReadPixels correctly. Michel Dänzer reported that
the following piglit test would fail on radeonsi after commit
fbba25bba:
spec@ext_texture_integer@fbo_integer_readpixels_sint_uint
This patch puts the checks back in Gallium, where they are needed.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Ilia Mirkin [Thu, 2 Jul 2015 04:13:36 +0000 (00:13 -0400)]
nv50/ir: don't emit src2 in immediate form
In the immediate form, src2 == dst, so it does not need to be emitted.
Otherwise it overlaps with the immediate value's low bits.
Fixes: 09ee907266 (nv50/ir: Fold IMM into MAD)
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Alexandre Courbot [Thu, 2 Jul 2015 02:36:55 +0000 (11:36 +0900)]
nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability
Prefer blit-based texture transfers only if the chip has dedicated VRAM
since it would translate to a copy into the same memory on shared-memory
chips.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 1 Jul 2015 19:18:47 +0000 (15:18 -0400)]
mesa: reset the source packing when creating temp transfer image
Commit
4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated temporary image neglected to reset the source packing. Set it
to the default which should be appropriate for the floats used.
Fixes: 4b249d2ee (mesa: Handle transferOps in texstore_rgba)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Alexandre Courbot [Tue, 30 Jun 2015 13:37:40 +0000 (22:37 +0900)]
nvc0: create screen fence objects with coherent attribute
This is required on non-coherent architectures to ensure the value of
the fence is correct at all times. Failure to do this results in the
display freezing for a few seconds every now and then on Tegra.
The NOUVEAU_BO_COHERENT is a no-op for coherent architectures, so behavior
on x86 should not be affected by this patch.
Also bump the required libdrm version to 2.4.62, which introduced this
flag.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>
Nanley Chery [Wed, 24 Jun 2015 17:59:13 +0000 (10:59 -0700)]
i965/gen9: use an unreserved surface alignment value
Although the horizontal and vertical alignment fields are ignored here,
0 is a reserved value for them and may cause undefined behavior. Change
the default value to an abitrary valid one.
v2: add comment about chosen value (Topi).
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Wed, 1 Jul 2015 00:04:52 +0000 (17:04 -0700)]
i965/fs: Use the builder directly for the gen6 interpolation add(32)
Now that we can create builders with a bigger width than their parent as
long as it's exec_all, we don't need to create the instruction manually.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Francisco Jerez [Tue, 30 Jun 2015 12:15:44 +0000 (15:15 +0300)]
i965/fs: Relax fs_builder channel group assertion when force_writemask_all is on.
This assertion was meant to catch code inadvertently escaping the
control flow jail determined by the group of channel enable signals
selected by some caller, however it seems useful to be able to
increase the default execution size as long as force_writemask_all is
enabled, because force_writemask_all is an explicit indication that
there is no longer a one-to-one correspondence between channels and
SIMD components so the restriction doesn't apply.
In addition reorder the calls to fs_builder::group and ::exec_all in a
couple of places to make sure that we don't temporarily break this
invariant in the future for instructions with exec_size higher than
the dispatch width.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Ilia Mirkin [Wed, 1 Jul 2015 07:47:41 +0000 (03:47 -0400)]
nouveau: rename var name for nouveau_vieux to avoid conflict with nouveau
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX to avoid the issue.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Martin Peres <martin.peres@free.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Tapani Pälli [Mon, 29 Jun 2015 12:23:45 +0000 (15:23 +0300)]
glsl: create program resource list after LinkShader
Resource list can be created properly only after LinkShader hook
has been called to make sure all dead variables have been removed.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925
Tapani Pälli [Mon, 29 Jun 2015 11:39:05 +0000 (14:39 +0300)]
glsl: expose build_program_resource_list function
This is required so that we can move resource list creation
to happen later.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Tapani Pälli [Mon, 29 Jun 2015 11:19:00 +0000 (14:19 +0300)]
glsl: build stageref mask using IR, not symbol table
Instead of using symbol table, build mask by inspecting IR. This
change is required by further patches to move resource list creation
to happen later when symbol table does not exist anymore.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Chia-I Wu [Mon, 29 Jun 2015 08:58:17 +0000 (16:58 +0800)]
ilo: remove ilo_image_params
It suffices to use ilo_image_layout directly.
Chia-I Wu [Mon, 29 Jun 2015 08:51:46 +0000 (16:51 +0800)]
ilo: add image_init_gen6_transfer_layout()
It replaces img_init_for_transfer().
Chia-I Wu [Mon, 29 Jun 2015 08:46:34 +0000 (16:46 +0800)]
ilo: add image_set_gen6_bo_size()
It replaces img_calculate_bo_size().
Chia-I Wu [Mon, 29 Jun 2015 08:42:04 +0000 (16:42 +0800)]
ilo: add image_set_gen6_{hiz,mcs}
They replace img_calculate_{hiz,mcs}_size().
Chia-I Wu [Mon, 29 Jun 2015 08:38:49 +0000 (16:38 +0800)]
ilo: add image_get_gen6_monolithic_size()
It replaces img_align().
Chia-I Wu [Mon, 29 Jun 2015 08:25:32 +0000 (16:25 +0800)]
ilo: add image_get_gen6_lods()
It replaces img_init_lods() and img_init_layer_height().
Chia-I Wu [Mon, 29 Jun 2015 08:16:11 +0000 (16:16 +0800)]
ilo: add image_get_gen{6,7}_alignment()
They replace img_init_alignments().
Chia-I Wu [Mon, 29 Jun 2015 08:14:36 +0000 (16:14 +0800)]
ilo: add image_get_gen6_{hiz,mcs}_enable()
They replace img_init_aux().
Chia-I Wu [Mon, 29 Jun 2015 08:11:09 +0000 (16:11 +0800)]
ilo: add image_get_gen6_tiling()
It replaces img_init_tiling().
Chia-I Wu [Mon, 29 Jun 2015 08:02:52 +0000 (16:02 +0800)]
ilo: add image_get_gen6_layout()
It replaces only img_init_walk() right now. It will replace all img_init_*().
Ilia Mirkin [Wed, 1 Jul 2015 06:11:39 +0000 (02:11 -0400)]
nv50/ir: copy joinAt when splitting both before and after
The current implementation only moves the joinAt when splitting after
the given instruction, not before it. So if you have a BB with
foo
instr
bar
joinat
and thus with joinAt set, we end up first splitting before instr, at
which point the instr's bb is updated to the new bb. Since that bb
doesn't have a joinAt set (despite containing one), when splitting after
the instr, there is nothing to copy over. Since the joinat will be in
the "split" bb irrespective of whether we're splitting before or after
the instruction, move it over in either case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91124
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 29 Jun 2015 07:11:59 +0000 (17:11 +1000)]
docs: update for llvmpipe fp64 support
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sat, 27 Jun 2015 04:21:54 +0000 (14:21 +1000)]
gallivm: add fp64 support. (v2.1)
This adds support for ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit to
llvmpipe.
Two things that don't mix well are SoA and doubles, see
emit_fetch_double, and emit_store_double_chan in this.
I've also had to split emit_data.chan, to add src_chan,
which can be different for doubles.
It handles indirect double fetches from temps, inputs, constants
and immediates. It doesn't handle double stores to indirects,
however it appears the mesa/st doesn't currently emit these,
it always does UARL/MOV combos, which will work fine.
tested with piglit, no regressions, all the fp64 tests seem to pass.
v2:
switch to using shuffles for fetch/store (Roland)
assert on indirect double stores - mesa/st never emits these (it uses MOV)
fix indirect temp/input/constant/immediates (Roland)
typos/formatting fixes (Roland)
v2.1:
cleanup some long lines, emit_store_double_chan cleanups.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sat, 27 Jun 2015 04:21:27 +0000 (14:21 +1000)]
tgsi: add infer support for double opcodes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Mon, 22 Jun 2015 21:53:24 +0000 (07:53 +1000)]
freedreno: use consistent version string format
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Timothy Arceri [Mon, 22 Jun 2015 21:47:58 +0000 (07:47 +1000)]
glsl: use consistent version string format
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Jason Ekstrand [Wed, 1 Jul 2015 00:47:53 +0000 (17:47 -0700)]
i965/fs: Fix PIXEL_X/Y in regs_read()
PIXEL_X/Y takes a vec2 in the first argument
Jason Ekstrand [Thu, 18 Jun 2015 19:44:35 +0000 (12:44 -0700)]
i965/fs: Remove the width field from fs_reg
As of now, the width field is no longer used for anything. The width field
"seemed like a good idea at the time" but is actually entirely redundant
with the instruction's execution size. Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
widths. With the builder, we can easiliy set the sizes explicitly and the
width field doesn't have as much purpose. At this point, it's just
redundant information that can get out of sync so it really needs to go.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 20:57:37 +0000 (13:57 -0700)]
i965/fs_generator: Use inst->exec_size for determining hardware reg widths
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 20:49:22 +0000 (13:49 -0700)]
i965/fs: Use exec_size instead of dst.width for computing component size
There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel. Instead, we should be using exec_size.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 25 Jun 2015 18:00:01 +0000 (11:00 -0700)]
i965/fs: Use the builder dispatch_width for computing register offsets
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 20:41:38 +0000 (13:41 -0700)]
i965/fs: Use the builder dispatch width instead of dst.width for pull constants
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:34:52 +0000 (12:34 -0700)]
i965/fs: Remove exec_size guessing from fs_inst::init()
Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:51:51 +0000 (12:51 -0700)]
i965/fs_builder: Use the dispatch width for setting exec sizes
Previously we used dst.width but the two *should* be the same.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:50:09 +0000 (12:50 -0700)]
i965/fs: Use exec_size for determining regs read/written and partial writes
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:30:43 +0000 (12:30 -0700)]
i965/fs: Remove fs_inst constructors that don't take an explicit exec_size
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:24:27 +0000 (12:24 -0700)]
i965/fs: Make better use of the builder in shader_time
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
builder.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 18 Jun 2015 19:07:27 +0000 (12:07 -0700)]
i965/fs: Add a builder argument to offset()
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>