Eric Anholt [Tue, 15 Nov 2016 22:35:12 +0000 (14:35 -0800)]
vc4: Restructure VPM write optimization into two passes.
For texturing, there won't be a fixed limit on how many writes there are,
so we need to compute uses up front.
Eric Anholt [Wed, 23 Nov 2016 20:23:55 +0000 (12:23 -0800)]
vc4: Make qir_for_each_inst_inorder() safe against removal.
The dead code elimination wants it to be safe, and I actually got
segfaults due to it being unsafe with the new coalescing pass.
Eric Anholt [Tue, 15 Nov 2016 22:24:25 +0000 (14:24 -0800)]
vc4: Split optimizing VPM writes from VPM reads.
The VPM write logic will be basically the same as the texture coordinate
write logic we need, and it's not really related to the VPM read logic
other than the reuse of the use_count array.
Eric Anholt [Tue, 15 Nov 2016 20:54:26 +0000 (12:54 -0800)]
vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.
For now we're still just generating MOVs, but this will let us fold into
other ops in the future. No difference on shader-db.
Eric Anholt [Tue, 15 Nov 2016 20:40:36 +0000 (12:40 -0800)]
vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).
Every caller was dereffing the qinst, and this will let us make the number
of sources vary depending on the destination of the qinst so that we can
have general ALU ops that store to tex_[strb] and get an implicit uniform.
Eric Anholt [Tue, 15 Nov 2016 20:36:20 +0000 (12:36 -0800)]
vc4: Replace the qinst src[] with a fixed-size array.
This may have made a tiny bit of sense when we had one 4-arg inst per
shader, but if we only ever put 2 things in, having a pointer to 2 things
almost every instruction is pointless indirection.
Eric Anholt [Tue, 15 Nov 2016 20:34:35 +0000 (12:34 -0800)]
vc4: Remove qir_inst4().
This was used originally for unorm4x8 packs, but we now represent those as
a series of packed movs.
Ilia Mirkin [Mon, 28 Nov 2016 02:05:36 +0000 (21:05 -0500)]
anv: bump the texture gather offset limits
This matches what NVIDIA and AMD hardware expose, as well as what Intel
hardware supports.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 02:05:35 +0000 (21:05 -0500)]
i965/gen7: expose larger gather offsets
This matches the capabilities of the hardware.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Mon, 28 Nov 2016 02:05:34 +0000 (21:05 -0500)]
i965: support constant gather offsets larger than 4 bits
Offsets that don't fit into 4 bits need to force gather_po to be
selected. Adjust the logic so that this happens.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Tue, 29 Nov 2016 02:13:02 +0000 (18:13 -0800)]
i965/fs: Refactor handling of constant tg4 offsets
Previously, we had an OFFSET_VALUE source for logical texture instructions
that was intended to mean exactly what it says, "offset". In reality, we
only fully used it for tg4 offsets. We used offset_value.file == IMM to
mean, "you have a constant offset, go look in instr->offset" and didn't
actually use the contents of the register at all in that case except for
in nir_emit_texture where we used it as a temporary before we copy it into
instr->offset.
This commit renames OFFSET_VALUE to TG4_OFFSET and restricts its usage to
indirect tg4 offsets only. The nir_emit_texture code is refactored so that
we explicitly build a header_bits value which is placed in instr->offset
and the constant offset values (both for tg4 and regular texture
operations) are used to construct header_bits and don't go through the
offset source at all. Finally, we stop passing offset_value in to
lower_sampler_logical_send_gen5 because we can't do indirect offsets until
gen7 anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Mon, 28 Nov 2016 23:18:43 +0000 (00:18 +0100)]
radv: Use different intrinsic for ubo loads.
Not sure about the deprecation path, but this intrinsic
can be lowered to SMEM loads. This results in a significant
Talos performance improvement.
v2: Fix for LLVM attribute changes.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Sat, 26 Nov 2016 23:31:01 +0000 (10:31 +1100)]
mesa: fix active subroutine uniforms properly
07fe2d565b introduced a big hack in order to return
NumSubroutineUniforms when querying ACTIVE_RESOURCES for
<shader>_SUBROUTINE_UNIFORM interfaces. However this is the
wrong fix we are meant to be returning the number of active
resources i.e. the count of subroutine uniforms in the
resource list which is what the code was previously doing,
anything else will cause trouble when trying to retrieve
the resource properties based on the ACTIVE_RESOURCES count.
The real problem is that NumSubroutineUniforms was counting
array elements as separate uniforms but the innermost array
is always considered a single uniform so we fix that count
instead which was counted incorrectly in
7fa0250f9.
Idealy we could probably completely remove
NumSubroutineUniforms and just compute its value when needed
from the resource list but this works for now.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 26 Nov 2016 06:09:30 +0000 (22:09 -0800)]
anv/cmd_buffer: Remove the 1-D case from the HiZ QPitch calculation
The 1-D special case doesn't actually apply to depth or HiZ. I discovered
this while converting BLORP over to genxml and ISL. The reason is that the
1-D special case only applies to the new Sky Lake 1-D layout which is only
used for LINEAR 1-D images. For tiled 1-D images, such as depth buffers,
the old gen4 2-D layout is used and the QPitch should be in rows.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 28 Nov 2016 23:44:13 +0000 (15:44 -0800)]
anv/cmd_buffer: Set the correct surface type for depth/stencil
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Ilia Mirkin [Wed, 23 Nov 2016 04:20:11 +0000 (23:20 -0500)]
anv: enable drawIndirectFirstInstance
This was already piped through in the CmdDraw(Indexed)Indirect handling.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Wed, 23 Nov 2016 04:03:12 +0000 (23:03 -0500)]
anv: expose depthBiasClamp, it is already set
The gen7/8_cmd_buffer logic already sets the clamp, and it's piped
through via the dynamic state.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Tue, 29 Nov 2016 00:49:51 +0000 (19:49 -0500)]
anv: bump maxFramebufferLayers to 2048
This matches maxImageArrayLayers, as well as the same setting in the GL
frontend.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Sun, 27 Nov 2016 21:37:17 +0000 (16:37 -0500)]
anv: enable storage image extended formats
These are all regularly available in desktop GL, so the backend fully
supports them.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sun, 27 Nov 2016 19:41:42 +0000 (14:41 -0500)]
anv: expose imageCubeArray functionality
This appears to be fully supported already.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 29 Nov 2016 01:16:56 +0000 (11:16 +1000)]
radv: set maxFragmentDualSrcAttachments to 1
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 29 Nov 2016 01:16:56 +0000 (11:16 +1000)]
anv: set maxFragmentDualSrcAttachments to 1
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Fri, 18 Nov 2016 20:36:40 +0000 (15:36 -0500)]
swr: [rasterizer memory] only clear up to the LOD size
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 15:15:30 +0000 (10:15 -0500)]
swr: [rasterizer memory] hook up stencil clears for ClearTile
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Ilia Mirkin [Fri, 18 Nov 2016 14:52:41 +0000 (09:52 -0500)]
swr: [rasterizer memory] add support for clearing Z32F_X32 and Z16
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 04:24:00 +0000 (20:24 -0800)]
intel/aubinator: Pull useful information from the AUB header
This commit does two things. One is to pull useful and/or interesting
information from the AUB file header and display it as a header above your
decoded batches. Second, it is now capable of pulling the PCI ID from the
AUB file comment left by intel_aubdump. This removes the need to use the
--gen flag all the time.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:14:27 +0000 (19:14 -0800)]
intel/aubinator: Wait to setup decoders until we parse the aub header
This requires that a few more state bits become global.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:38:00 +0000 (19:38 -0800)]
intel/aubinator: Rework handling of the --gen flag
This makes it just store the pci_id instead of a struct pointer
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Nov 2016 03:26:13 +0000 (19:26 -0800)]
intel/aubinator: Trust the packet size in the header for SUBOPCODE_HEADER
We were reading from the "comment size" dword and incrementing by that
amount. This never caused a problem because that field was always zero.
However, experimenting with actual aub file comments indicates, the
simulator seems to include the comment size in the packet size provided in
the header. We should do the same.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:30:50 +0000 (11:30 -0800)]
intel/aubinator: Add a get_offset helper
The helper automatically handles masking for us so we don't have to worry
about whether or not something is in the bottom bits.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:33:20 +0000 (11:33 -0800)]
intel/aubinator: Fix the kernel start pointer for 3DSTATE_HS
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 18 Nov 2016 19:14:59 +0000 (11:14 -0800)]
intel/aubinator: Add a get_address helper
This new helper is automatically handles 32 vs. 48-bit GTT issues. It also
handles 48-bit canonical addresses on Broadwell and above.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 9 Sep 2016 04:12:11 +0000 (21:12 -0700)]
intel/aubinator: Properly handle batch buffer chaining
The original aubinator that Kristian wrote had a bug in the handling of
MI_BATCH_BUFFER_START that propagated into the version in upstream mesa.
In particular, it ignored the "2nd level" bit which tells you whether this
MI_BATCH_BUFFER_START is a subroutine call (2nd level) or a goto. Since
the Vulkan driver uses batch chaining, this can lead to a very confusing
interpretation of the batches. In some cases, depending on how things are
laid out in the virtual GTT, you can even end up with infinite loops in
batch processing.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Ilia Mirkin [Sat, 26 Nov 2016 02:08:16 +0000 (21:08 -0500)]
swr: don't clear all dirty bits when changing so targets
Among other things, blits would clear existing SO targets which would
cause a bunch of updates from u_blitter to be missed.
Fixes fbo-scissor-blit fbo, probably among many others.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Ilia Mirkin [Sat, 26 Nov 2016 01:29:30 +0000 (20:29 -0500)]
swr: [rasterizer core] fix typo in scissor tile-alignment logic
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Kenneth Graunke [Mon, 28 Nov 2016 21:37:44 +0000 (13:37 -0800)]
anv: Fix cache UUID generation.
I asked Emil to switch from 0 (success) vs. -1 (fail) to use a boolean
in my review comments. The "not" went missing. Easy mistake, but the
result is that nothing runs at all :)
Fix whitespace while we're here too.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Gwan-gyeong Mun [Fri, 25 Nov 2016 14:39:04 +0000 (23:39 +0900)]
vulkan/wsi: Fix resource leak in success path of wsi_queue_init()
It fixes leakage of pthread_condattr resource on wsi_queue_init()
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Gwan-gyeong Mun [Fri, 25 Nov 2016 14:34:46 +0000 (23:34 +0900)]
anv: Update the teardown in reverse order of the anv_CreateDevice
This updates releasing of resource in reverse order of the anv_CreateDevice
to anv_DestroyDevice.
And it fixes resource leak in pthread_mutex, pthread_cond, anv_gem_context.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gwan-gyeong Mun [Fri, 25 Nov 2016 14:34:43 +0000 (23:34 +0900)]
anv: drop the return type for anv_queue_init()
anv_queue_init() always returns VK_SUCCESS, so caller does not need
to check return value of anv_queue_init().
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gwan-gyeong Mun [Fri, 25 Nov 2016 14:34:42 +0000 (23:34 +0900)]
anv: Add missing error-checking to anv_block_pool_init (v2)
When the memfd_create() and u_vector_init() fail on anv_block_pool_init(),
this patch makes to return VK_ERROR_INITIALIZATION_FAILED.
All of initialization success on anv_block_pool_init(), it makes to return
VK_SUCCESS.
CID
1394319
v2: Fixes from Emil's review:
a) Add the return type for propagating the return value to caller.
b) Changed anv_block_pool_init() to return VK_ERROR_INITIALIZATION_FAILED
on failure of initialization.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chandu Babu Namburu [Wed, 23 Nov 2016 14:54:34 +0000 (20:24 +0530)]
st/omx/dec/h264: consider POC as signed instead of unsigned
picture order count can be a negative value
Reviewed-by: Christian König <christian.koenig@amd.com>
Emil Velikov [Thu, 24 Nov 2016 20:30:45 +0000 (20:30 +0000)]
radv: don't return VK_SUCCESS if radv_device_get_cache_uuid() fails
If radv_device_get_cache_uuid() fails result will be VK_SUCCESS as set
by the radv_init_wsi() call above.
Fixes: d943839 (radv: Use library mtime for cache UUID.)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Emil Velikov [Thu, 24 Nov 2016 20:30:44 +0000 (20:30 +0000)]
radv: don't leak the fd if radv_physical_device_init() succeeds
radv_amdgpu_winsys_create() does not take ownership of the fd, thus we
end up leaking it as we return with VK_SUCCESS.
Cc: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Emil Velikov [Thu, 24 Nov 2016 20:30:43 +0000 (20:30 +0000)]
anv: don't leak memory if anv_init_wsi() fails
brw_compiler_create() rzalloc-ates memory which we forgot to free.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Thu, 24 Nov 2016 20:30:42 +0000 (20:30 +0000)]
anv: don't double-close the same fd
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 24 Nov 2016 20:30:41 +0000 (20:30 +0000)]
configure.ac: remove no longer used TIMESTAMP_CMD
Good bye, you shall not be missed.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 24 Nov 2016 20:30:40 +0000 (20:30 +0000)]
anv: automake: don't generate anv_timestamp.h
No longer used as of last commit.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 24 Nov 2016 20:30:39 +0000 (20:30 +0000)]
anv: Use library mtime for cache UUID.
Inspired by a similar commit for radv.
Rather than recomputing the timestamp on each make invocation, just
fetch it at runtime.
Thus we no longer get the constant rebuild of anv_device.c and the
follow-up libvulkan_intel.so link, when nothing has changed.
I.e. using make && make install is a little bit faster.
v2: Use bool return type (Ken).
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Thu, 24 Nov 2016 20:30:38 +0000 (20:30 +0000)]
anv: Store UUID in physical device.
Port of an equivalent commit for radv.
v2: Move the call just after MMAP_VERSION (Ken).
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Thu, 24 Nov 2016 18:18:15 +0000 (18:18 +0000)]
isl: Make isl_finishme only warn once per call-site
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 24 Nov 2016 18:18:14 +0000 (18:18 +0000)]
radv: Make radv_finishme only warn once per call-site
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Emil Velikov [Thu, 24 Nov 2016 18:18:13 +0000 (18:18 +0000)]
anv: use do { } while (0) in the anv_finishme macro
Use the generic construct instead of the currect GCC specific one.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Mon, 28 Nov 2016 17:40:04 +0000 (17:40 +0000)]
docs: add git tips how to do commit fixups and squash them
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
George Kyriazis [Mon, 28 Nov 2016 17:35:26 +0000 (17:35 +0000)]
docs: add note about r-b/other tags when resending
[Emil Velikov: split from the typos fixes]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Andres Gomez [Mon, 28 Nov 2016 16:47:42 +0000 (18:47 +0200)]
docs: fix small typos in the submit patches page
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 28 Nov 2016 17:22:15 +0000 (17:22 +0000)]
docs/releasing: use correct page title
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 28 Nov 2016 17:18:06 +0000 (17:18 +0000)]
docs/releasing: correctly document touch-testing
I've used an ancient version of the script which did not cover:
- version expansion (cd mesa-* does not work)
- --enable-glx-tls
- EGL and es2* testing
- Vulkan and DOTA2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 28 Nov 2016 15:35:43 +0000 (15:35 +0000)]
docs/release: drop references to patchwork
The changes to release.sh have landed, so all we need is a recent
checkout of xorg-utils.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 28 Nov 2016 15:30:13 +0000 (15:30 +0000)]
docs: add news item and link release notes for 13.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 28 Nov 2016 15:28:01 +0000 (15:28 +0000)]
docs: add sha256 checksums for 13.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
2722144beddac0aa7065b478502c7c3a1f2a5451)
Emil Velikov [Mon, 28 Nov 2016 15:06:08 +0000 (15:06 +0000)]
docs: add release notes for 13.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
c9e993ba1301ac0380b86a3934f5c97ff0827594)
Dave Airlie [Mon, 28 Nov 2016 07:03:11 +0000 (07:03 +0000)]
radv: fix 3D clears with baseMiplevel
This fixes:
dEQP-VK.api.image_clearing.clear_color_image.3d*
These were hitting an assert as the code wasn't taking the
baseMipLevel into account when minify the image depth.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 28 Nov 2016 06:22:05 +0000 (16:22 +1000)]
radv: brown-paper bag for a forgotten else.
This fixes the fix:
radv/ac/llvm: fix regression with shadow samplers fix
Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 28 Nov 2016 05:42:36 +0000 (15:42 +1000)]
radv/ac/llvm: fix regression with shadow samplers fix
This fixes
b56b54cbf1d8e70c87a434da5350d11533e5fed8:
radv/ac/llvm: shadow samplers only return one value
It makes sure we only do that for shadow sampling, as
opposed to sizing requests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 24 Oct 2016 21:47:13 +0000 (07:47 +1000)]
radv/ac/llvm: shadow samplers only return one value.
The intrinsic engine asserts in llvm due to this.
Reported-by: Christoph Haag <haagch+mesadev@frickel.club>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 24 Nov 2016 00:04:35 +0000 (10:04 +1000)]
radv/si: fix optimal micro tile selection
The same fix was posted for radeonsi, so port it here.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Emil Velikov [Thu, 24 Nov 2016 18:14:58 +0000 (18:14 +0000)]
radv: honour the number of properties available
Cap up-to the number of properties available while copying the data.
Otherwise we might crash and/or leak data.
Cc: Dave Airlie <airlied@redhat.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Mun Gwan-gyeong [Fri, 25 Nov 2016 14:34:44 +0000 (23:34 +0900)]
radv: drop the return type for radv_queue_init()
radv_queue_init() always returns VK_SUCCESS, so caller does not need
to check return value of radv_queue_init().
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Mon, 21 Nov 2016 15:23:04 +0000 (10:23 -0500)]
freedreno: fix slice size for imported buffers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 9 Nov 2016 18:17:08 +0000 (13:17 -0500)]
freedreno/a3xx: make _emit_const() static
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 9 Nov 2016 18:16:36 +0000 (13:16 -0500)]
freedreno/a4xx: make _emit_const() static
Signed-off-by: Rob Clark <robdclark@gmail.com>
Jason Ekstrand [Sat, 26 Nov 2016 06:27:36 +0000 (22:27 -0800)]
anv/pipeline: Make is_dual_src_blend_factor inline
It's not used on gen8+ so it causes unused function warnings.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jason Ekstrand [Sat, 26 Nov 2016 06:26:50 +0000 (22:26 -0800)]
anv/pipeline: Make the temp blend attachment state pointer const
This fixes a "discards const" warning since blend is const.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 25 Nov 2016 11:25:58 +0000 (12:25 +0100)]
gm107/ir: optimize 32-bit CONST load to mov
This is not allowed for indirect accesses because the source
GPR might be erased by a subsequent instruction (WaR hazard)
if we don't emit a read dep bar.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 25 Nov 2016 11:17:56 +0000 (12:17 +0100)]
gm107/ir: do not combine CONST loads
This will allow to use MOV instead of LD. The main advantage is
that MOV doesn't require a read dependency barrier while LD does,
and so this will both reduce barriers pressure and the number of
stall counts needed to read data from constant memory.
This is currently only for user uniform accesses. I should do
something similar when loading from the driver constant buffer
but it seems like a bit tricky to handle for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jason Ekstrand [Sat, 26 Nov 2016 05:45:02 +0000 (21:45 -0800)]
anv/device: Remove a bogus finishme comment
We've been properly detecting bit6 swizzling for a long time now.
Ben Widawsky [Wed, 20 Apr 2016 14:23:06 +0000 (07:23 -0700)]
i965: Enable fast clears for multi-lod
On SKL (also fast clear is used for level 0, layer 0):
Manhattan 3.0: 3.88434% +/- 0.814659%
Manhattan 3.0 off: 3.25542% +/- 0.101149%
Trex: 3.43501% +/- 0.31223%
Trex off: 4.13781% +/- 0.
0993569%
ON BDW:
Manhattan 3.0: 1.37079% +/- 0.571208%
Manhattan 3.0 off: 1.74029% +/- 0.267499%
v2 (Ben, Matt): Fix rebase error by removing the perf warning
v3 (Topi): Rebased on top of revised eligibility logic
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Tue, 22 Nov 2016 19:53:38 +0000 (21:53 +0200)]
i965: Allow single-sampled miptree to be resolved and shared
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Fri, 10 Jun 2016 06:12:23 +0000 (09:12 +0300)]
i965/gen8: Relax asserts prohibiting arrayed/mipmapped fast clears
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Tue, 8 Nov 2016 12:19:15 +0000 (14:19 +0200)]
i965: Use ISL for CCS layouts
One can now also delete intel_get_non_msrt_mcs_alignment().
v2 (Jason): Do not leak aux buf but allocate only after getting
ISL surfaces.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Mon, 13 Jun 2016 07:51:10 +0000 (10:51 +0300)]
i965: Resolve non-compressed fast clears prior layered rendering
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Tue, 14 Jun 2016 06:10:16 +0000 (09:10 +0300)]
i965: Restrict fast color clear on first slice only
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Fri, 10 Jun 2016 08:09:53 +0000 (11:09 +0300)]
i965: Track fast color clear state in level/layer granularity
Note that RESOLVED is not tracked in the map explicitly. Absence
of item implicitly means RESOLVED state.
v2: Added intel_resolve_map_clear() into intel_miptree_release()
v3 (Jason): Properly handle the assumption of resolve map not
containing any items with state RESOLVED. Removed
unnecessary intel_miptree_set_fast_clear_state() call
in brw_blorp_resolve_color() preventing
intel_miptree_set_fast_clear_state() from asserting
against RESOLVED.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Wed, 8 Jun 2016 17:51:32 +0000 (20:51 +0300)]
i965: Move fast clear state enumeration into resolve map
Status is still tracked per miptree. Next patch will switch to
resolve map per slice/level.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Fri, 10 Jun 2016 06:01:54 +0000 (09:01 +0300)]
i965: Refactor check if color resolve is needed
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Thu, 9 Jun 2016 07:59:06 +0000 (10:59 +0300)]
i965: Add plumbing for fast clear layer/level details
Until now fast clear has been supported only for non-layered and
non-mipmapped buffers. However, from gen8 onwards there is hardware
support also for layered/mipmapped. Once this is enabled, fast clear
operations target specific layer/level and call for the state to be
tracked in the same granularity. This is the first step providing
the details from callers to the state tracking.
Patch introduces new interface for reading and writing the state
hiding the upcoming bookkeeping changes in the call sites. There is
bunch of sanity checks added that will be relaxed per hardware
generation later on when the actual functionality is enabled.
v2: Rebased on top current master setting the state in
blorp_surf_for_miptree().
v3: Replace open-coded resolved check in surface state emission
with intel_miptree_has_color_unresolved().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Mon, 19 Sep 2016 09:03:58 +0000 (12:03 +0300)]
i965: Add interface for checking multiple slices if any is unresolved
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Thu, 15 Sep 2016 05:22:34 +0000 (08:22 +0300)]
i965: Provide slice details to renderbuffer fast clear state tracker
This patch also introduces getter and setter for fast clear state
preparing for tracking the state per slice.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Fri, 10 Jun 2016 07:09:34 +0000 (10:09 +0300)]
i965: Split per miptree and per slice/level fast clear bits
Currently the status bits for fast clear include the flag telling
if non-multisampled mcs buffer should be used at all. Once the
state tracking is changed to follow individual levels/layers one
still needs to have the mcs enabling information in the miptree.
Therefore simply split it out to its own boolean.
Possible follow-up work is to combine disable_aux_buffers and
no_ccs into single enum.
v2 (Jason): Changed no_msrt_mcs to no_ccs and updated comment
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Thu, 15 Sep 2016 06:05:55 +0000 (09:05 +0300)]
i965: Provide slice details to color resolver
v2: Make intel_miptree_resolve_color() take start layer and
layer count.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Fri, 10 Jun 2016 05:23:40 +0000 (08:23 +0300)]
i965: Add new interface for full color resolves
Upcoming patches will introduce fast clear in level/layer
granularity like the driver does already for depth/hiz. This patch
introduces equivalent full resolve option.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Topi Pohjolainen [Wed, 6 Jul 2016 09:29:41 +0000 (12:29 +0300)]
i965: Refactor lossless compression state tracking
Essentially this moves fast clear state update away from surface
state setup into brw_postdraw_set_buffers_need_resolve() that gets
called just after draw submission.
Calling intel_miptree_used_for_rendering() can be drop for gen6
and earlier as it is no-op.
v2: Rebased on top current master setting the state in
blorp_surf_for_miptree().
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Andres Gomez [Sat, 22 Oct 2016 14:22:13 +0000 (17:22 +0300)]
Revert "glsl: allow layout qualifier overrides with ARB_shading_language_420pack"
This reverts commit
aaa69c79cd584db4d9c6ea7794e93d29f3d54572.
The commit was erroneous because the ast_layout_expression class is
meant to hold a list used for an after check that all the declared
values for a layout-qualifier-name are consistent.
Therefore, the check for the possibility of duplicated values was
previously fixed to happen much sooner, in the GLSL parser and the
merge of layout qualifiers, and the process_qualifier_constant method
only needs to check that the values are consistent.
By now, those layout-qualifier-name represented as a
ast_layout_expression are "max_vertices", "invocations", "vertices",
"local_size_[x|y|z]" and "xfb_stride".
From page 40 (page 46 of the PDF) of the GLSL 1.50 spec:
" All geometry shader output layout declarations in a program must
declare the same layout and same value for max_vertices."
From page 44 (page 50 of the PDF) of the GLSL 4.00 spec:
" If an invocation count is declared, all such declarations must
specify the same count."
From page 47 (page 53 of the PDF) of the GLSL 4.00 spec:
" All tessellation control shader layout declarations in a program
must specify the same output patch vertex count."
From page 60 (page 66 of the PDF) of the GLSL 4.30 spec:
" Also, if such a layout qualifier is declared more than once in the
same shader, all those declarations must set the same set of local
work-group sizes and set them to the same values; otherwise a
compile-time error results. If multiple compute shaders attached
to a single program object declare local work-group size, the
declarations must be identical; otherwise a link-time error
results."
From page 73 (page 79 of the PDF) of the GLSL 4.40 spec:
" While xfb_stride can be declared multiple times for the same
buffer, it is a compile-time or link-time error to have different
values specified for the stride for the same buffer."
Fixes GL44-CTS.enhanced_layouts.xfb_duplicated_stride
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Sat, 22 Oct 2016 14:13:16 +0000 (17:13 +0300)]
Revert "glsl: geom shader max_vertices layout must match."
This reverts commit
4c863993780a11cea6f88fa0682796bee5794042.
The commit was erroneous because the ast_layout_expression class was
created to hold a list of values for a layout-qualifier-name which is
allowed to appear in more than one expression in the same
shader/program but not to hold different values.
In other words, the list is used for an after check that all the
declared values for a layout-qualifier-name are consistent.
Therefore, the values stored must match always, not just for
"max_vertices" or any other eventual layout-qualifier-name.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Thu, 6 Oct 2016 22:52:06 +0000 (01:52 +0300)]
glsl: push layout-qualifier-name values from variable declarations to global
After the previous modifications in the merging of the
layout-qualifier-name values, we no longer push the final value in a
declaration to the global values.
This regression happens because we don't call for merging on the
right-most layout qualifier of a declaration which is also the
overriding one in case of multiple appearances.
Now, we add a new method to push these values to the global ones and
we call for this just after all the layout-qualifier collapsing has
happened in a declaration.
This simplifies how this was working in two ways; we make a clear
differentiation of when we are pushing this to the global values since
before it was mixed in the merging call and we only run this once all
the processing for layout-qualifiers in a declaration has happened.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Sat, 22 Oct 2016 14:04:33 +0000 (17:04 +0300)]
glsl: simplified error checking for duplicated layout-qualifiers
The GLSL parser has been simplified to check for the needed
GL_ARB_shading_language_420pack extension just when merging the
qualifiers in the proper cases.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Thu, 6 Oct 2016 22:52:08 +0000 (01:52 +0300)]
glsl: simplified ast_type_qualifier::merge_into_[in|out]_qualifier API
Since we modified the way in which multiple repetitions of the same
layout-qualifier-name in a single declaration collapse into the
ast_type_qualifier class, we can simplify the
merge_into_[in|out]_qualifier APIs through removing the create_node
parameter.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Sat, 22 Oct 2016 14:01:11 +0000 (17:01 +0300)]
glsl: ignore all but the rightmost layout qualifier name from the rightmost layout qualifier
From page 46 (page 52 of the PDF) of the GLSL 4.20 spec:
" More than one layout qualifier may appear in a single
declaration. If the same layout-qualifier-name occurs in multiple
layout qualifiers for the same declaration, the last one overrides
the former ones."
Consider this example:
" #version 150
#extension GL_ARB_shading_language_420pack: enable
layout(max_vertices=2) layout(max_vertices=3) out;
layout(max_vertices=3) out;"
Although different values for "max_vertices" results in a compilation
error. The above code is valid because max_vertices=2 is ignored.
Hence, when merging qualifiers in an ast_type_qualifier, we now ignore
new appearances of a same layout-qualifier-name if the new
"is_multiple_layouts_merge" parameter is on, since the GLSL parser
works in this case from right to left.
In addition, any special treatment for the buffer, uniform, in or out
layout defaults has been moved in the GLSL parser to the rule
triggered just after any previous processing/merging on the
layout-qualifiers has happened in a single declaration since it was
run too soon previously.
Fixes GL44-CTS.shading_language_420pack.qualifier_override_layout
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Tue, 22 Nov 2016 14:09:54 +0000 (16:09 +0200)]
glsl: refactor duplicated validations between 2 layout-qualifiers
Several layout-qualifier validations are duplicated in the
merge_qualifier and validate_in_qualifier methods.
We would rather have them refactored into single calls.
Suggested by Timothy.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 11 Nov 2016 19:03:24 +0000 (21:03 +0200)]
glsl: assert on incoherent point mode layout-id-qualifier validation
The point mode value in an ast_type_qualifier can only be true if the
flag is already set since this layout-id-qualifier can only be or not
be present in a shader.
Hence, it is useless to check for its value if the flag is already
set. Just replaced with an assert.
V2: assert instead of checking for coherence and raising a compilation
error. Suggested by Timothy.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>