Luke Kenneth Casson Leighton [Wed, 7 Sep 2022 19:27:09 +0000 (20:27 +0100)]
add fcpsgn parallel reduction test
https://bugs.libre-soc.org/show_bug.cgi?id=864
Luke Kenneth Casson Leighton [Wed, 7 Sep 2022 19:26:24 +0000 (20:26 +0100)]
whoops forgot to strip "NN/NN=insn" in power_svp64.py
Luke Kenneth Casson Leighton [Wed, 7 Sep 2022 18:40:01 +0000 (19:40 +0100)]
add 2nd parallel prefix test, this time subtract (non-commutative)
Dmitry Selyutin [Wed, 7 Sep 2022 16:15:54 +0000 (19:15 +0300)]
power_insn: fix immediate operands
Dmitry Selyutin [Wed, 7 Sep 2022 12:30:32 +0000 (15:30 +0300)]
power_insn: refactor operands disassembly
Dmitry Selyutin [Wed, 7 Sep 2022 09:47:38 +0000 (12:47 +0300)]
power_fields: deprecate arrays
Dmitry Selyutin [Tue, 6 Sep 2022 19:09:59 +0000 (22:09 +0300)]
power_insn: support EXTRA2/EXTRA3 GPR/FPR
Dmitry Selyutin [Tue, 6 Sep 2022 18:26:53 +0000 (21:26 +0300)]
power_fields: allow getting individual field bits
Dmitry Selyutin [Tue, 6 Sep 2022 18:26:03 +0000 (21:26 +0300)]
power_insn: use tuple for bit ranges in fields
Dmitry Selyutin [Tue, 6 Sep 2022 13:25:23 +0000 (16:25 +0300)]
pysvp64asm: create database once
Dmitry Selyutin [Tue, 6 Sep 2022 12:26:42 +0000 (15:26 +0300)]
power_insn: fix naming conventions
Dmitry Selyutin [Tue, 6 Sep 2022 11:51:18 +0000 (14:51 +0300)]
power_insn: stricter reg type check
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 14:50:35 +0000 (15:50 +0100)]
add first functional confirmed unit test for parallel reduce REMAP
https://bugs.libre-soc.org/show_bug.cgi?id=864
using remap_preduce_yield directly, confirmed operational through ISACaller
added through decoder/isa/svshape.py which is responsible
in SVSHAPE.getiterator() for returning the appropriate yield-iterator
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 14:28:05 +0000 (15:28 +0100)]
REMAP parallel-reduce:
https://bugs.libre-soc.org/show_bug.cgi?id=864
* add 0b0111 csv entry for svshape
* stop sv/trans/svp64.py raising exception for SVrm=0b0111
* add beginnings of svshape SVrm=0b0111 to simplev.mdwn
* add first unit test
Jacob Lifshay [Tue, 6 Sep 2022 12:20:19 +0000 (05:20 -0700)]
add fixedsync.py to .gitignore
Jacob Lifshay [Tue, 6 Sep 2022 12:19:15 +0000 (05:19 -0700)]
fix incorrect comment
Jacob Lifshay [Tue, 6 Sep 2022 12:07:32 +0000 (05:07 -0700)]
add all fptrans ops to CSVs
Jacob Lifshay [Tue, 6 Sep 2022 11:50:57 +0000 (04:50 -0700)]
add unofficial and comment2 fields to minor_63.csv
Dmitry Selyutin [Tue, 6 Sep 2022 09:01:35 +0000 (12:01 +0300)]
power_insn: rename value argument to insn in operands
Dmitry Selyutin [Tue, 6 Sep 2022 09:01:10 +0000 (12:01 +0300)]
power_insn: support branch stub
Dmitry Selyutin [Mon, 5 Sep 2022 19:29:09 +0000 (22:29 +0300)]
power_insn: clean extra disassembly
Dmitry Selyutin [Mon, 5 Sep 2022 18:36:24 +0000 (21:36 +0300)]
power_enum: tune SVPtype representation
Dmitry Selyutin [Mon, 5 Sep 2022 18:35:33 +0000 (21:35 +0300)]
power_enum: tune SVEtype representation
Dmitry Selyutin [Mon, 5 Sep 2022 18:00:15 +0000 (21:00 +0300)]
power_insn: disassemble extra index
Dmitry Selyutin [Mon, 5 Sep 2022 17:58:13 +0000 (20:58 +0300)]
power_enum: tune SVExtra representation
Dmitry Selyutin [Mon, 5 Sep 2022 17:39:17 +0000 (20:39 +0300)]
power_insn: support extra_reg routine
Dmitry Selyutin [Mon, 5 Sep 2022 11:19:52 +0000 (14:19 +0300)]
power_insn: move extras to SVP64Record
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 11:42:30 +0000 (12:42 +0100)]
removing two unused fields (E) which somehow
made it into the 1.6.2 section
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 11:01:29 +0000 (12:01 +0100)]
add dummy fixedsync.mdwn pseudocode for lwarx/stbcx. LR/SC operations
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 01:22:02 +0000 (02:22 +0100)]
sort out demo of remap_preduce_yield.py
originally based on wiki preduce.py, split into two separate SVSHAPEs
one for left operand the other for right
Luke Kenneth Casson Leighton [Tue, 6 Sep 2022 00:39:00 +0000 (01:39 +0100)]
add first version of parallel reduction yield
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 23:12:10 +0000 (00:12 +0100)]
add a new log option to pysvp64dis and make it a command-line
console script using setup.py entry_points
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 23:09:06 +0000 (00:09 +0100)]
use log function for warnings about .mdwn files in pagereader.py
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 23:07:46 +0000 (00:07 +0100)]
move reading of os.environ out of a global which prohibits
setting of os.environ at runtime
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 16:23:12 +0000 (17:23 +0100)]
remove parallel-reduction mode from decoder and sv/trans/svp64.py
parallel reduction has to be done through REMAP due to two critical factors:
1) the amount of gates in joining REMAP with PREDUCE as a "Mode"
2) the differing Vector Length (similar to Matrix) from the number of
operations needed to be performed
the complexity arising is too great which means it has to be done as REMAP
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 11:40:04 +0000 (12:40 +0100)]
rename remap_debug to remap_set_steps
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 11:25:26 +0000 (12:25 +0100)]
please do not use format-specifiers
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 11:20:26 +0000 (12:20 +0100)]
remove yet more f"" specifiers
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 11:14:28 +0000 (12:14 +0100)]
removing use of format. please do not use format
Luke Kenneth Casson Leighton [Mon, 5 Sep 2022 09:21:20 +0000 (10:21 +0100)]
rename "PARALLEL" enums to "PTREDUCE" - parallel tree reduce
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 19:47:40 +0000 (20:47 +0100)]
add detection of Parallel-Reduction Mode into SVP64RMModeDecode
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 19:35:53 +0000 (20:35 +0100)]
add parallel-reduction (subvl=0) in sv/trans/svp64.py
Dmitry Selyutin [Sun, 4 Sep 2022 18:21:49 +0000 (21:21 +0300)]
power_insn: support mode description
Dmitry Selyutin [Sun, 4 Sep 2022 17:36:16 +0000 (20:36 +0300)]
power_insn: decouple mode function
Dmitry Selyutin [Sun, 4 Sep 2022 17:27:41 +0000 (20:27 +0300)]
power_insn: pass database instance everywhere
Dmitry Selyutin [Sun, 4 Sep 2022 16:17:48 +0000 (19:17 +0300)]
power_insn: refactor operation order
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 15:06:50 +0000 (16:06 +0100)]
whoops forgot to write maxvl in PowerDecoder2
Dmitry Selyutin [Sun, 4 Sep 2022 13:28:29 +0000 (16:28 +0300)]
power_insn: drop argument in PPCDatabase
Dmitry Selyutin [Sun, 4 Sep 2022 12:33:23 +0000 (15:33 +0300)]
power_table: replace prints with logging
Dmitry Selyutin [Sun, 4 Sep 2022 12:31:35 +0000 (15:31 +0300)]
power_table: simplify the code
Dmitry Selyutin [Sun, 4 Sep 2022 12:12:01 +0000 (15:12 +0300)]
power_insn: inherit PPCMultiRecord from frozenset
Dmitry Selyutin [Sun, 4 Sep 2022 12:10:56 +0000 (15:10 +0300)]
power_insn: try exact name matching first
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 11:35:34 +0000 (12:35 +0100)]
brainmelt moment, added a comma into a comment in a csv file
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 11:05:33 +0000 (12:05 +0100)]
use maxvl not vl in impicit-RS
Dmitry Selyutin [Sun, 4 Sep 2022 11:23:45 +0000 (14:23 +0300)]
power_insn: remove the whitespaces properly
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:45:32 +0000 (11:45 +0100)]
comments for 3-in 2-out ops
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:32:08 +0000 (11:32 +0100)]
whitespace cleanup
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:29:05 +0000 (11:29 +0100)]
comments on ffmadds fft 3-in 2-out
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:14:49 +0000 (11:14 +0100)]
assert prints out XO
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:10:48 +0000 (11:10 +0100)]
more comments
Dmitry Selyutin [Sun, 4 Sep 2022 10:06:24 +0000 (13:06 +0300)]
power_insn: refactor immediate operands
Dmitry Selyutin [Sun, 4 Sep 2022 09:49:42 +0000 (12:49 +0300)]
power_insn: inherit Operands from tuple
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 10:08:19 +0000 (11:08 +0100)]
code-cleanup (comments) and rename "i" to "XO"
Dmitry Selyutin [Sun, 4 Sep 2022 09:26:48 +0000 (12:26 +0300)]
power_insn: support immediate operands
Dmitry Selyutin [Sun, 4 Sep 2022 09:04:29 +0000 (12:04 +0300)]
power_insn: make operand classes public
Dmitry Selyutin [Sun, 4 Sep 2022 08:58:08 +0000 (11:58 +0300)]
Revert "target_addr in b and bc pseudo-code has no corresponding"
This reverts commit
7656b425de39cb28e6c52b9ee32c0f12517bae69.
Dmitry Selyutin [Sun, 4 Sep 2022 08:57:57 +0000 (11:57 +0300)]
Revert "svbranch.mdwn: replace target_addr with BD"
This reverts commit
617e5af215856d2b80f3c0d7c92d97e4a4e0b2fc.
Dmitry Selyutin [Sun, 4 Sep 2022 09:02:41 +0000 (12:02 +0300)]
power_insn: switch back to target_addr
Jacob Lifshay [Sun, 4 Sep 2022 07:53:30 +0000 (00:53 -0700)]
reallocate opcodes for ffadds (converted to X-FORM) and fdmadds to make space for fptrans
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 01:18:32 +0000 (02:18 +0100)]
clear up assert, clean up table columns
Luke Kenneth Casson Leighton [Sun, 4 Sep 2022 01:14:38 +0000 (02:14 +0100)]
fix power_table.py to use multi-entries
Dmitry Selyutin [Sat, 3 Sep 2022 21:15:22 +0000 (00:15 +0300)]
power_insn: support SVP64 verbose mode
Dmitry Selyutin [Sat, 3 Sep 2022 21:06:46 +0000 (00:06 +0300)]
power_insn: refactor verbose output
Dmitry Selyutin [Sat, 3 Sep 2022 20:50:18 +0000 (23:50 +0300)]
power_insn: support verbose binary
Dmitry Selyutin [Sat, 3 Sep 2022 20:15:54 +0000 (23:15 +0300)]
power_insn: support PPC multi-records
Dmitry Selyutin [Sat, 3 Sep 2022 17:44:33 +0000 (20:44 +0300)]
power_insn: update disassembly target_addr
Dmitry Selyutin [Sat, 3 Sep 2022 17:07:46 +0000 (20:07 +0300)]
pysvp64dis: support verbose mode
Dmitry Selyutin [Sat, 3 Sep 2022 14:18:39 +0000 (17:18 +0300)]
power_insn: support verbose disassembly mode
Dmitry Selyutin [Sat, 3 Sep 2022 10:52:05 +0000 (13:52 +0300)]
power_insn: implement mode decoding
Dmitry Selyutin [Sat, 3 Sep 2022 14:51:48 +0000 (17:51 +0300)]
power_insn: support Rc detection
Dmitry Selyutin [Sat, 3 Sep 2022 13:16:05 +0000 (16:16 +0300)]
power_insn: drop pack/unpack bit
Dmitry Selyutin [Sat, 3 Sep 2022 11:16:30 +0000 (14:16 +0300)]
power_insn: rename normal field to simple
Dmitry Selyutin [Sat, 3 Sep 2022 11:08:47 +0000 (14:08 +0300)]
power_insn: decouple IMM/IDX LD/ST modes
Dmitry Selyutin [Sat, 3 Sep 2022 10:09:30 +0000 (13:09 +0300)]
power_insn: support operands check
Dmitry Selyutin [Sat, 3 Sep 2022 10:06:05 +0000 (13:06 +0300)]
power_insn: canonicalize Rc field name
Dmitry Selyutin [Fri, 2 Sep 2022 22:11:32 +0000 (01:11 +0300)]
power_insn: support mode selector
Dmitry Selyutin [Fri, 2 Sep 2022 22:04:48 +0000 (01:04 +0300)]
power_insn: support normal mode
Dmitry Selyutin [Fri, 2 Sep 2022 21:20:16 +0000 (00:20 +0300)]
power_insn: support LD/ST indexed mode
Dmitry Selyutin [Fri, 2 Sep 2022 21:17:39 +0000 (00:17 +0300)]
power_insn: simplify fields
Dmitry Selyutin [Fri, 2 Sep 2022 21:01:47 +0000 (00:01 +0300)]
power_insn: decrease LDSTMode class nesting
Dmitry Selyutin [Fri, 2 Sep 2022 20:46:10 +0000 (23:46 +0300)]
power_insn: support LD/ST immediate mode
Dmitry Selyutin [Fri, 2 Sep 2022 16:56:39 +0000 (19:56 +0300)]
power_insn: make RM class public
Dmitry Selyutin [Fri, 2 Sep 2022 16:34:21 +0000 (19:34 +0300)]
power_insn: remap RM immediately
Dmitry Selyutin [Fri, 2 Sep 2022 21:34:29 +0000 (00:34 +0300)]
power_fields: allow slicing mappings
Dmitry Selyutin [Fri, 2 Sep 2022 16:34:11 +0000 (19:34 +0300)]
power_fields: allow slicing fields
Dmitry Selyutin [Fri, 2 Sep 2022 15:04:32 +0000 (18:04 +0300)]
power_fields: create arrays from Array class
Dmitry Selyutin [Fri, 2 Sep 2022 21:48:01 +0000 (00:48 +0300)]
sv_binutils: shorten and simplify the output
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:38:53 +0000 (19:38 +0100)]
create list of opcodes by dict entry
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:32:34 +0000 (19:32 +0100)]
correct table header
Luke Kenneth Casson Leighton [Sat, 3 Sep 2022 18:30:08 +0000 (19:30 +0100)]
use opcode directly