add detection of Parallel-Reduction Mode into SVP64RMModeDecode

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 29faffb15031eb1d88294f6dabed9c0bbc7c3696..bd8dfd1880adb20efe79ba396ed6709a899426e5 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -297,6 +297,7 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
     BRANCH = 5
+    PARALLEL = 6 # Parallel Reduction
 
 
 @unique

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 702bd8274f833367dbbb3561ed8fdcd45e9c80be..9f804a17da76a76ca36aa847065f5ccaf0421668 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -66,16 +66,20 @@ LD/ST indexed:
 11     inv     zz RC1  Rc=0: pred-result z/nonz
 
 Arithmetic:
-00     0   dz sz       normal mode
-00     1   0 RG        scalar reduce mode (mapreduce), SUBVL=1
-00     1   1 /         parallel reduce mode (mapreduce), SUBVL=1
-00     1   SVM 0       subvector reduce mode, SUBVL>1
-00     1   SVM 1       Pack/Unpack mode, SUBVL>1
-01     inv CR-bit      Rc=1: ffirst CR sel
-01     inv VLi RC1     Rc=0: ffirst z/nonz
-10     N   dz sz       sat mode: N=0/1 u/s
-11     inv CR-bit      Rc=1: pred-result CR sel
-11     inv zz RC1      Rc=0: pred-result z/nonz 
+| 0-1 |  2  |  3   4  |  description              |
+| --- | --- |---------|-------------------------- |
+| 00  |   0 |  dz  sz | simple mode                      |
+| 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
+| 00  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
+| 00  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
+| 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
+| 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
+| 10  |   N | dz   sz |  sat mode: N=0/1 u/s, SUBVL=1 |
+| 10  |   N | zz   0  |  sat mode: N=0/1 u/s, SUBVL>1 |
+| 10  |   N | zz   1  |  Pack/Unpack sat mode: N=0/1 u/s, SUBVL>1 |
+| 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
+| 11  | inv | zz  RC1 |  Rc=0: pred-result z/nonz |
 
 Branch Conditional:
 note that additional BC modes are in *other bits*, specifically
@@ -176,10 +180,13 @@ class SVP64RMModeDecode(Elaboratable):
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
                         comb += do_pu.eq(mode[SVP64MODE.LDST_PACK]) # Pack mode
                     with m.Elif(mode[SVP64MODE.REDUCE]):
-                        comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
-                        # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
-                        with m.If(self.rm_in.subvl != Const(0, 2)): # active
-                            comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK])
+                        with m.If(mode[SVP64MODE.PARALLEL]):
+                            comb += self.mode.eq(SVP64RMMode.PARALLEL)
+                        with m.Else():
+                            comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
+                            # Pack only active if SVM=1 & SUBVL>1 & Mode[4]=1
+                            with m.If(self.rm_in.subvl != Const(0, 2)): # active
+                                comb += do_pu.eq(mode[SVP64MODE.ARITH_PACK])
                     with m.Else():
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
                 with m.Case(1):