mesa.git
5 years agoradv: Change memory type order for GPUs without dedicated VRAM
Alex Smith [Sun, 2 Jun 2019 10:32:06 +0000 (11:32 +0100)]
radv: Change memory type order for GPUs without dedicated VRAM

Put the uncached GTT type at a higher index than the visible VRAM type,
rather than having GTT first.

When we don't have dedicated VRAM, we don't have a non-visible VRAM
type, and the property flags for GTT and visible VRAM are identical.
According to the spec, for types with identical flags, we should give
the one with better performance a lower index.

Previously, apps which follow the spec guidance for choosing a memory
type would have picked the GTT type in preference to visible VRAM (all
Feral games will do this), and end up with lower performance.

On a Ryzen 5 2500U laptop (Raven Ridge), this improves average FPS in
the Rise of the Tomb Raider benchmark by up to ~30%. Tested a couple of
other (Feral) games and saw similar improvement on those as well.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
(Bas: CCing this to 19.2-rc due to high impact and limited complexity)

5 years agolima/ppir: print register index and components number for spilled register
Vasily Khoruzhick [Tue, 20 Aug 2019 14:30:46 +0000 (07:30 -0700)]
lima/ppir: print register index and components number for spilled register

It can be useful for debugging purposes

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add control flow support
Vasily Khoruzhick [Mon, 19 Aug 2019 06:37:23 +0000 (23:37 -0700)]
lima/ppir: add control flow support

This commit adds support for nir_jump_instr, if and loop
nir_cf_nodes.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add better liveness analysis
Vasily Khoruzhick [Mon, 19 Aug 2019 06:34:22 +0000 (23:34 -0700)]
lima/ppir: add better liveness analysis

Add better liveness analysis that was modelled after one in vc4.
It uses live ranges and is aware of multiple blocks which is prerequisite
for adding CF support

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: validate shader outputs
Vasily Khoruzhick [Fri, 23 Aug 2019 04:17:23 +0000 (21:17 -0700)]
lima/ppir: validate shader outputs

Mali4x0 supports only gl_FragColor. gl_FragDepth is not supported.
Check that we don't get anything but gl_FragColor in shader outputs.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: turn store_color into ALU node
Vasily Khoruzhick [Thu, 22 Aug 2019 14:42:56 +0000 (07:42 -0700)]
lima/ppir: turn store_color into ALU node

We don't have a special OP to store color in PP, all we need to do is to
store gl_FragColor into reg0, thus it's just a mov and therefore ALU node.

Yet we still need to indicate that it's store_color op so regalloc ignores
its destination.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: create ppir block for each corresponding NIR block
Vasily Khoruzhick [Mon, 19 Aug 2019 06:30:32 +0000 (23:30 -0700)]
lima/ppir: create ppir block for each corresponding NIR block

Create ppir block for each corresponding NIR block and populate
its successors. It will be used later in liveness analysis and
in CF support

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add dummy op
Vasily Khoruzhick [Mon, 19 Aug 2019 06:03:57 +0000 (23:03 -0700)]
lima/ppir: add dummy op

We can get following from NIR:

(1) r1 = r2
(2) r2 = ssa1

Note that r2 is read before it's assigned, so there's no node for
it in comp->var_nodes. We need to create a dummy node in this case
which sole purpose is to hold ppir_dest with reg in it.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add write after read deps for registers
Vasily Khoruzhick [Mon, 19 Aug 2019 05:57:54 +0000 (22:57 -0700)]
lima/ppir: add write after read deps for registers

For cases like:

(1) r1 = r2
(2) r2 = ssa1

We need to add (1) as dependency of (2), otherwise scheduler may
reorder them.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: fix ordering deps
Vasily Khoruzhick [Mon, 19 Aug 2019 05:51:34 +0000 (22:51 -0700)]
lima/ppir: fix ordering deps

There can be several root nodes, i.e.:

(1) r0 = r1
(2) r2 = r3
(3) branch if (ssa1)

We need to make (3) depend on (1) and (2), old code added
dependency only for (2), and (1) was kept as root node since there
is no branch/discard or store color between two movs.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: set write mask for texture loads if dest is reg
Vasily Khoruzhick [Mon, 19 Aug 2019 05:48:22 +0000 (22:48 -0700)]
lima/ppir: set write mask for texture loads if dest is reg

Destination for texture load can be a reg, so we need to
set write mask in this case

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add support for unconditional branches and condition negation
Vasily Khoruzhick [Tue, 28 May 2019 03:02:55 +0000 (20:02 -0700)]
lima/ppir: add support for unconditional branches and condition negation

We need 'negate' modifier for branch condition to minimize branching. Idea
is to generate following:

current_block: { ...; if (!statement) branch else_block; }
then_block: { ...; branch after_block; }
else_block: { ... }
after_block: { ... }

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: clone ld_{uni,tex,var} into each block
Vasily Khoruzhick [Tue, 20 Aug 2019 03:20:12 +0000 (20:20 -0700)]
lima/ppir: clone ld_{uni,tex,var} into each block

ppir_lower_load() and ppir_lower_load_texture() assume that node
is in the same block as its successors, fix it by cloning each
ld_uni and ld_tex to every block.

It also reduces register pressure since values never cross block
boundaries and thus never appear in live_in or live_out of any block,
so do it for varyings as well.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: refactor const lowering
Vasily Khoruzhick [Wed, 24 Jul 2019 22:33:47 +0000 (15:33 -0700)]
lima/ppir: refactor const lowering

Const nodes are now cloned for each user, i.e. const is guaranteed to have
exactly one successor, so we can use ppir_do_one_node_to_instr() and
drop insert_to_each_succ_instr()

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agoanv: Only re-emit non-dynamic state that has changed.
Rafael Antognolli [Tue, 20 Aug 2019 00:01:10 +0000 (17:01 -0700)]
anv: Only re-emit non-dynamic state that has changed.

On commit f6e7de41d7b, we started emitting 3DSTATE_LINE_STIPPLE as part
of the non-dynamic state. That gets re-emitted every time we bind a new
VkPipeline. But that instruction is non-pipelined, and it caused a perf
regression of about 9-10% on Dota2.

This commit makes anv_dynamic_state_copy() return a mask with only the
state that has changed when copying it. 3DSTATE_LINE_STIPPLE won't be
emitted anymore unless it has changed, fixing the problem above.

v2: Improve commit message and add documentation about skipped checks
(Jason)

Fixes: f6e7de41d7b ("anv: Implement VK_EXT_line_rasterization")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agopan/decode: Validate and quiet helper invocation flag
Alyssa Rosenzweig [Thu, 22 Aug 2019 23:36:10 +0000 (16:36 -0700)]
pan/decode: Validate and quiet helper invocation flag

We can statically determine from the disassembly if helper invocations
will be needed, so we can validate the corresponding bit in the
cmdstream and thus avoid printing the bit itself in the decode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Analyze helper invocations
Alyssa Rosenzweig [Thu, 22 Aug 2019 23:31:03 +0000 (16:31 -0700)]
pan/midgard: Analyze helper invocations

We check for texture ops which calculate derivatives (either explicitly
via dFd* or implicitly) and mark the shader as requiring helper
invocations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoutil: fix compilation on macos
Lionel Landwerlin [Fri, 23 Aug 2019 08:35:13 +0000 (10:35 +0200)]
util: fix compilation on macos

timespec_get() is not available on macos, we need to pull in the
include/c11/threads_posix.h helper.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103674
Fixes: e2d761de03 ("util: drop final reference to p_compiler.h")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoi965: Silence brw_blorp uninitialized warning
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 16:12:02 +0000 (09:12 -0700)]
i965: Silence brw_blorp uninitialized warning

The variables level and start_layer are not initialized, then
initialized if we have a BUFFER_BIT_DEPTH set.  We assert on them
later using the same check.  This should be enough but GCC 9.1.1 is
not convinced, so let's initialize the variables.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agotgsi: Remove unused local
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 15:22:02 +0000 (08:22 -0700)]
tgsi: Remove unused local

Code that used it was removed in 4ebe6b2e72e ("tgsi: Drop the SSE2
constants setup that's been dead code since 2011.")

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoiris: Guard GEN9-only function in Iris state to avoid warning
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 15:12:37 +0000 (08:12 -0700)]
iris: Guard GEN9-only function in Iris state to avoid warning

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agointel/decoders: Avoid uninitialized variable warnings
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:59:21 +0000 (07:59 -0700)]
intel/decoders: Avoid uninitialized variable warnings

Initialize `next_batch_addr` and `second_level`.  If the batch is well
formed, those values will be overriden, if not, they are as good as
uninitialized garbage.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agocompiler/glsl: Fix warning about unused function
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:57:13 +0000 (07:57 -0700)]
compiler/glsl: Fix warning about unused function

The helper check_node_type() is only used when DEBUG is set (in the
function below), but ASSERTED macro uses NDEBUG.  So just guard the
helper with #ifdef.  If we see more such cases we might consider a
ASSERTED-like macro for the DEBUG case.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: Drop unused local variable
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 14:59:47 +0000 (07:59 -0700)]
anv: Drop unused local variable

Leftover from 021fa28163a ("xintel/nir: Add a helper for getting
BRW_AOP from an intrinsic").

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agointel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:41:18 +0000 (07:41 -0700)]
intel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1

Compiler can't see that d is initialized.

    ../src/intel/compiler/brw_vec4_nir.cpp: In function ‘int brw::try_immediate_source(const nir_alu_instr*, brw::src_reg*, bool, const gen_device_info*)’:
    ../src/intel/compiler/brw_vec4_nir.cpp:984:12: warning: ‘d’ may be used uninitialized in this function [-Wmaybe-uninitialized]
      984 |          d = MAX2(-d, d);

Assert that we expect at least one component -- hence d going to be
set.  That by itself is not enough, so also zero initialize the
variable.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: additional query fixes
Andres Rodriguez [Wed, 14 Aug 2019 03:52:23 +0000 (23:52 -0400)]
radv: additional query fixes

Make sure we read the updated data from the gpu in cases where WAIT_BIT
is not set.

Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoiris: Fix large timeout handling in rel2abs()
Kenneth Graunke [Thu, 22 Aug 2019 23:08:16 +0000 (16:08 -0700)]
iris: Fix large timeout handling in rel2abs()

...by copying the implementation of anv_get_absolute_timeout().

Appears to fix a CTS test with 32-bit builds:
GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush

Fixes: f459c56be6b ("iris: Add fence support using drm_syncobj")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoiris: Set MOCS in all STATE_BASE_ADDRESS commands
Kenneth Graunke [Thu, 22 Aug 2019 23:52:52 +0000 (16:52 -0700)]
iris: Set MOCS in all STATE_BASE_ADDRESS commands

Rafael Antognolli tracked down a performance gap between i965 and iris
in Synmark2's OglCSDof microbenchmark, noting that iris was performing
substantially more memory reads and writes, with substantially fewer
L3 hits.  He suggested that something might be wrong with MOCS, or L3
configs, at which point I came up with a theory...

It would appear that the STATE_BASE_ADDRESS command updates the MOCS
settings for various base addresses even if you don't specify the
"Modify Enable" bit for that address.  Until now, we had been setting
only the MOCS for bases we intended to change, leaving the others
"blank" which is MOCS table entry 0, which is uncached.

Most data access has a more specific MOCS (e.g. in SURFACE_STATE),
but scratch access uses the Stateless Data Port Access MOCS from
STATE_BASE_ADDRESS.  So this meant all scratch access was uncached.

Improves performance in Synmark2's OglCSDof by 2x, bringing iris
on par with the existing i965 driver.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoglx: Fix up glXQueryGLXPbufferSGIX on macOS.
Vinson Lee [Fri, 23 Aug 2019 05:26:26 +0000 (22:26 -0700)]
glx: Fix up glXQueryGLXPbufferSGIX on macOS.

Fix this build error on macOS.

../src/glx/apple/glx_empty.c:158:4: error: void function 'glXQueryGLXPbufferSGIX' should not return a value [-Wreturn-type]
   return 0;
   ^      ~

Fixes: 3dd299c3d5b8 ("glx: Sync <GL/glxext.h> with Khronos")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Adam Jackson <ajax@redhat.com>
5 years agodocs: update calendar, add news item and link release notes for 19.1.5
Juan A. Suarez Romero [Fri, 23 Aug 2019 10:40:40 +0000 (12:40 +0200)]
docs: update calendar, add news item and link release notes for 19.1.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
5 years agodocs: add sha256 checksums for 19.1.5
Juan A. Suarez Romero [Fri, 23 Aug 2019 10:38:02 +0000 (12:38 +0200)]
docs: add sha256 checksums for 19.1.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit ae2a676cd1748c850f579863003c92f2b137f44a)

5 years agodocs: add release notes for 19.1.5
Juan A. Suarez Romero [Fri, 23 Aug 2019 10:24:21 +0000 (12:24 +0200)]
docs: add release notes for 19.1.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit a384fe0cebf1fcd6671c51c749fcc981e01b5505)

5 years agoradeonsi/nir: Rewrite output scanning
Connor Abbott [Wed, 21 Aug 2019 15:08:03 +0000 (17:08 +0200)]
radeonsi/nir: Rewrite output scanning

Similarly to before, this didn't properly handle varying structs with
doubles in them.

This doesn't fix any tests, but was noticed while looking at the code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: Rewrite store intrinsic gathering
Connor Abbott [Wed, 21 Aug 2019 11:28:21 +0000 (13:28 +0200)]
radeonsi/nir: Rewrite store intrinsic gathering

The old version wasn't as accurate as it could be, and didn't handle
double variables inside structs correctly. Walk the path to compute the
actual components affected.

In combination with the previous commit fixes
KHR-GL45.enhanced_layouts.varying_structure_locations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: Add const_index when loading GS inputs
Connor Abbott [Tue, 20 Aug 2019 10:47:39 +0000 (12:47 +0200)]
radeonsi/nir: Add const_index when loading GS inputs

This fixes loading GS inputs in structures or arrays.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: Don't add const offset to indirect
Connor Abbott [Tue, 20 Aug 2019 10:45:32 +0000 (12:45 +0200)]
radeonsi/nir: Don't add const offset to indirect

This is already done in get_deref_offset() in the common code. We were
adding it twice accidentally.

Fixes KHR-GL45.enhanced_layouts.varying_array_locations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac/nir: Assert GS input index is constant
Connor Abbott [Tue, 20 Aug 2019 10:43:33 +0000 (12:43 +0200)]
ac/nir: Assert GS input index is constant

If it's not we silently ignore indir_index which is definitely a bug.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac/nir: Handle const array offsets in get_deref_offset()
Connor Abbott [Tue, 20 Aug 2019 10:31:55 +0000 (12:31 +0200)]
ac/nir: Handle const array offsets in get_deref_offset()

Some users of this function (e.g. GS inputs) currently only work with
constant offsets. We got lucky since all the tests used an array index
of 0, so the non-constant part was always 0. But we still need to handle
this.

This doesn't fix any CTS test, but was noticed while debugging one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi/nir: Don't recompute num_inputs and num_outputs
Connor Abbott [Thu, 22 Aug 2019 11:21:17 +0000 (13:21 +0200)]
radeonsi/nir: Don't recompute num_inputs and num_outputs

Don't repeat what mesa/st already does.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agost/nir: Fix num_inputs for VS inputs
Connor Abbott [Thu, 22 Aug 2019 11:19:07 +0000 (13:19 +0200)]
st/nir: Fix num_inputs for VS inputs

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradv/gfx10: do not use NGG with NAVI14
Samuel Pitoiset [Wed, 21 Aug 2019 08:53:57 +0000 (10:53 +0200)]
radv/gfx10: do not use NGG with NAVI14

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
Samuel Pitoiset [Wed, 21 Aug 2019 08:50:48 +0000 (10:50 +0200)]
radv/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0

Only gfx9 and older use it to get InstanceID in VGPR1.
Ported from RadeonSI.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agogitlab-ci: bump LLVM to 8 for meson-vulkan and meson-clover
Samuel Pitoiset [Wed, 21 Aug 2019 09:45:25 +0000 (11:45 +0200)]
gitlab-ci: bump LLVM to 8 for meson-vulkan and meson-clover

To fix pipeline builds.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoac,radv,radeonsi: remove LLVM 7 support
Samuel Pitoiset [Thu, 1 Aug 2019 09:18:43 +0000 (11:18 +0200)]
ac,radv,radeonsi: remove LLVM 7 support

Now that LLVM 9 will be released soon, we will only support
LLVM 8, 9 and master (10).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoegl: reset blob cache set/get functions on terminate
Tapani Pälli [Thu, 22 Aug 2019 07:49:36 +0000 (10:49 +0300)]
egl: reset blob cache set/get functions on terminate

Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when
running dEQP that terminates and reinitializes a display.

Fixes: 6f5b57093b3 "egl: add support for EGL_ANDROID_blob_cache"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoiris: Avoid unnecessary resolves on transfer maps
Kenneth Graunke [Fri, 26 Apr 2019 17:44:18 +0000 (10:44 -0700)]
iris: Avoid unnecessary resolves on transfer maps

We were always resolving the buffer as if we were accessing it via
CPU maps, which don't understand any auxiliary surfaces.  But we often
copy to a temporary using BLORP, which understands compression just
fine.  So we can avoid the resolve, and accelerate the copy as well.

Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agoiris: Drop copy format hacks from copy region based transfer path.
Kenneth Graunke [Wed, 24 Apr 2019 03:19:37 +0000 (20:19 -0700)]
iris: Drop copy format hacks from copy region based transfer path.

This doesn't work for compressed formats, as the source texture and
temporary texture would have different block sizes.  (Forcing the driver
to always take the GPU path would expose the bug.)  Instead, just use
the source format for the temporary, and let blorp_copy deal with
overrides.

The one case where we can't do this is ASTC, because isl won't let us
create a linear ASTC surface.  Fall back to the CPU paths there for now.

Fixes: 9d1334d2a0f ("iris: Use copy_region and staging resources to avoid transfer stalls")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agoiris: Update fast clear colors on Gen9 with direct immediate writes.
Kenneth Graunke [Mon, 19 Aug 2019 20:57:46 +0000 (13:57 -0700)]
iris: Update fast clear colors on Gen9 with direct immediate writes.

Gen11 stores the fast clear color in an "indirect clear buffer", as
a packed pixel value.  Gen9 hardware stores it as a float or integer
value, which is interpreted via the format.  We were trying to store
that in a buffer, for similarity with Icelake, and MI_COPY_MEM_MEM
it from there to the actual SURFACE_STATE bytes where it's stored.

This unfortunately doesn't work for blorp_copy(), which does bit-for-bit
copies, and overrides the format to a CCS-compatible UINT format.  This
causes the clear color to be interpreted in the overridden format.

Normally, we provide the clear color on the CPU, and blorp_blit.c:2611
converts it to a packed pixel value in the original format, then unpacks
it in the overridden format, so the clear color we use expands to the
bits we originally desired.

However, BLORP doesn't support this pack/unpack with an indirect clear
buffer, as it would need to do the math on the GPU.  On Gen11+, it isn't
necessary, as the hardware does the right thing.

This patch changes Gen9 to stop using an indirect clear buffer and
simply do PIPE_CONTROLs with post-sync write immediate operations
to store the new color over the surface states for regular drawing.
BLORP continues streaming out surface states, and handles fast clear
colors on the CPU.

Fixes: 53c484ba8ac ("iris: blorp using resolve hooks")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agoiris: Fix broken aux.possible/sampler_usages bitmask handling
Kenneth Graunke [Tue, 20 Aug 2019 05:36:36 +0000 (22:36 -0700)]
iris: Fix broken aux.possible/sampler_usages bitmask handling

For renderable surfaces, we allocate SURFACE_STATEs for each bit in
res->aux.possible_usages.  Sampler views use res->aux.sampler_usages.

When pinning buffers, we call surf_state_offset_for_aux() to calculate
the offset to the desired surface state.  surf_state_offset_for_aux()
took an aux_modes parameter, which should be one of those two fields.
However...it was not using that parameter.  It always used the broader
res->aux.possible_usages field directly.

One of the callers, update_clear_value(), was passing incorrect masks
for this parameter.  It iterated through the bits in order, using
u_bit_scan(), which destructively modifies the mask.  So each time we
called it, the count of bits before our selected mode was 0, which would
cause us to always update the SURFACE_STATE for ISL_AUX_USAGE_NONE,
rather than updating each in turn.  This was hidden by the earlier bug
where surf_state_offset_for_aux() ignored the parameter.

Fixes: 7339660e803 ("iris: Add aux.sampler_usages.")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agoiris: Replace devinfo->gen with GEN_GEN
Kenneth Graunke [Mon, 19 Aug 2019 20:52:37 +0000 (13:52 -0700)]
iris: Replace devinfo->gen with GEN_GEN

This is genxml, we can compile out this code.

Fixes: 26606672847 ("iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agopan/midgard: Fix writeout combining
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:59:54 +0000 (13:59 -0700)]
pan/midgard: Fix writeout combining

shader-db regression in the scheduler.

Fixes: dff4986b1aa ("pan/midgard: Emit store_output branch just-in-time")
total bundles in shared programs: 2055 -> 2019 (-1.75%)
bundles in affected programs: 1055 -> 1019 (-3.41%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.35% max: 20.00% x̄: 6.71% x̃: 5.16%
95% mean confidence interval for bundles value: -1.00 -1.00
95% mean confidence interval for bundles %-change: -8.45% -4.97%
Bundles are helped.

total quadwords in shared programs: 3444 -> 3408 (-1.05%)
quadwords in affected programs: 1897 -> 1861 (-1.90%)
helped: 36
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.19% max: 14.29% x̄: 3.97% x̃: 2.99%
95% mean confidence interval for quadwords value: -1.00 -1.00
95% mean confidence interval for quadwords %-change: -5.08% -2.86%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Implement gl_FragCoord correctly
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:29:23 +0000 (11:29 -0700)]
panfrost: Implement gl_FragCoord correctly

Rather than passing through the transformed gl_Position, we can use the
hardware-level varying for this, which will correctly handle
gl_FragCoord.w

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Remove vertex buffer offset from its size
Alyssa Rosenzweig [Thu, 22 Aug 2019 15:02:52 +0000 (08:02 -0700)]
panfrost: Remove vertex buffer offset from its size

The offset is added to the base address, so we need to subtract it from
the size to maintain the same end address and thus prevent a buffer
overflow:

   end_address = start_address + size

   start_address' = start_address + offset
   size' = size - offset

   end_address' = start_address' + size'
                = (start_address + offset) + (size - offset)
                = (start_address + size) + (offset - offset)
                = start_address + size
                = end_address

   QED.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Handle special varyings
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:27:38 +0000 (13:27 -0700)]
pan/decode: Handle special varyings

We need a special path for special varyings so we parse them correctly
instead of throwing an error when they inevitably point to bad memory.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Remove size/stride divisibility check
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:09:00 +0000 (13:09 -0700)]
pan/decode: Remove size/stride divisibility check

The hardware doesn't care, and a lot of Panfrost code relies on an
oversized buffer. The important part is that (stride *
padded_num_vertices) is no greater than size, which we'll need to check
once we validate instancing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Decouple attribute/meta printing
Alyssa Rosenzweig [Thu, 22 Aug 2019 20:07:01 +0000 (13:07 -0700)]
pan/decode: Decouple attribute/meta printing

They are independent fields, so the parser should reflect that.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Print stub for uniforms
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:30:13 +0000 (11:30 -0700)]
pan/decode: Print stub for uniforms

We don't need to dump the contents necessary, but having the stub with
the address is useful.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Decode actual varying_meta address
Alyssa Rosenzweig [Thu, 22 Aug 2019 18:21:35 +0000 (11:21 -0700)]
pan/decode: Decode actual varying_meta address

I don't know who thought this mask was a good idea but unfortunately it
must have been me.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Downgrade shader property mismatch to warning
Alyssa Rosenzweig [Thu, 22 Aug 2019 16:02:48 +0000 (09:02 -0700)]
pan/decode: Downgrade shader property mismatch to warning

If we permit more $whatever through than the shader needs, that's a bit
of a waste, but it isn't an error.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Validate, but do not print, index buffer
Alyssa Rosenzweig [Wed, 21 Aug 2019 23:06:23 +0000 (16:06 -0700)]
pan/decode: Validate, but do not print, index buffer

We don't actually care about the *contents* of the index buffer, but we
would rather like to ensure it is present and of the correct size.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Validate mali_shader_meta stats
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:57:23 +0000 (14:57 -0700)]
pan/decode: Validate mali_shader_meta stats

We can infer these stats in many cases from the disassembly, so we
should try to sanity check where we can. We may need to be fuzzy about
analysis, since analysis gives us a bound but we don't mind if it's not
used fully by the shader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Disassemble before printing shader descriptor
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:28:36 +0000 (14:28 -0700)]
pan/decode: Disassemble before printing shader descriptor

This allows the shader descriptor to access the disassembled stats.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Promote <no shader> to an error
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:16:32 +0000 (14:16 -0700)]
pan/decode: Promote <no shader> to an error

There is no reason this should happen to an in-spec program, as far as I
know.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Fix uniform printing
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:15:05 +0000 (14:15 -0700)]
pan/decode: Fix uniform printing

Lazypasting from UBOs.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Validate blend shaders don't access I/O
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:04:05 +0000 (14:04 -0700)]
pan/decode: Validate blend shaders don't access I/O

We could do better by forcing the checks to *equal* zero (right now, an
indeterminate answer will pass the checks), but this is a start to guard
against some egregious cases.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Validate and simplify FRAGMENT payloads
Alyssa Rosenzweig [Wed, 21 Aug 2019 19:29:47 +0000 (12:29 -0700)]
pan/decode: Validate and simplify FRAGMENT payloads

There are a number of conditions we need to test for to statically check
for TILE_RANGE_FAULTs, but once these checks are in order, we can print
as-is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Validate MFBD tags
Alyssa Rosenzweig [Wed, 21 Aug 2019 19:06:50 +0000 (12:06 -0700)]
pan/decode: Validate MFBD tags

These tags need to match up with what's actually described by the MFBD,
so check this. Once this is checked, since the type and contents of the
FBD are obvious from printing above, there's no need to explicitly mark
off the framebuffer line.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Eliminate non-FBD dumped case
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:52:51 +0000 (11:52 -0700)]
pan/decode: Eliminate non-FBD dumped case

We don't need *more* cases to deal with.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Removing uniform buffer framing
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:46:06 +0000 (11:46 -0700)]
pan/decode: Removing uniform buffer framing

We can do single line prints:

   ubuf_0[192] = memory_161f5000 + 896;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Remove mali_attr(_meta) framing
Alyssa Rosenzweig [Wed, 21 Aug 2019 18:43:13 +0000 (11:43 -0700)]
pan/decode: Remove mali_attr(_meta) framing

It doesn't give any real added value.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Disassemble integer constants in hex
Alyssa Rosenzweig [Wed, 21 Aug 2019 20:46:00 +0000 (13:46 -0700)]
pan/midgard: Disassemble integer constants in hex

It's usually easier to parse mentally.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Explain ffma
Alyssa Rosenzweig [Wed, 21 Aug 2019 20:45:47 +0000 (13:45 -0700)]
pan/midgard: Explain ffma

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Analyze simple loads/store
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:07:36 +0000 (15:07 -0700)]
pan/midgard: Analyze simple loads/store

For shaders using exclusively direct attribute/varyings, we can work
this out statically. For shaders with indirect access, we just set an
upper bound of 16 (the max attributes/varyings we support) and the
actual count will be reported regardless.

We proceed similarly for textures/samplers, as well as for UBOs. While
UBOs can be *indexed* indirectly, the *UBO itself* -- which is what we
count in the shader descriptor (rather than the UBO descriptors) -- is
statically determinable.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Compute work_count via writes
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:02:41 +0000 (15:02 -0700)]
pan/midgard: Compute work_count via writes

This is exact.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Sketch static analysis to uniform count
Alyssa Rosenzweig [Wed, 21 Aug 2019 22:18:40 +0000 (15:18 -0700)]
pan/midgard: Sketch static analysis to uniform count

This one is a little tricky, but the idea is that:

   r16-r23 are always uniforms

   r8-r15 are sometimes work, sometimes uniforms...
      ...but as work, they are always written before use
      ...and as uniforms, they are never written before use

So we use that heuristic to determine the count to feed the machine.
We'll record work register use in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/decode: Hoist shader-db stats to shared decode
Alyssa Rosenzweig [Wed, 21 Aug 2019 21:00:46 +0000 (14:00 -0700)]
pan/decode: Hoist shader-db stats to shared decode

We'll want all this information to validate the shader descriptor.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agonir: Remove nir_const_load_to_arr
Alyssa Rosenzweig [Wed, 21 Aug 2019 17:51:35 +0000 (10:51 -0700)]
nir: Remove nir_const_load_to_arr

There are no remaining users in-tree.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agopan/midgard,bifrost: Expand nir_const_load_to_arr
Alyssa Rosenzweig [Wed, 21 Aug 2019 17:50:31 +0000 (10:50 -0700)]
pan/midgard,bifrost: Expand nir_const_load_to_arr

Panfrost is the only user of the macro; we are better off expanding than
having random stuff in nir.h.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoglx: Make __glXGetDrawableAttribute return true sometimes
Adam Jackson [Tue, 20 Aug 2019 19:47:22 +0000 (15:47 -0400)]
glx: Make __glXGetDrawableAttribute return true sometimes

Right now it always returns zero, but as of:

    commit a48a6b8a400e6e92961cf7b7b4c287e8e9875f39
    Author: Adam Jackson <ajax@redhat.com>
    Date:   Tue Nov 14 15:13:05 2017 -0500

        glx: Prepare driFetchDrawable for no-config contexts

We were hoping it would return true if the drawable could actually be
looked up. It wasn't, so that didn't go very well. With the most recent
update to <GL/glxext.h> glXQueryGLXPbufferSGIX (correctly) returns void,
so there's no longer anything else besides driFetchDrawable that depends
on the return value from __glXGetDrawableAttribute.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglx: Sync <GL/glxext.h> with Khronos
Adam Jackson [Tue, 20 Aug 2019 19:43:06 +0000 (15:43 -0400)]
glx: Sync <GL/glxext.h> with Khronos

Minor fixups required to keep the prototypes matching and to remove
mention of retired enums.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoglx: Whitespace cleanups
Adam Jackson [Tue, 20 Aug 2019 19:06:08 +0000 (15:06 -0400)]
glx: Whitespace cleanups

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoswr: use LLVM version string instead of re-computing it
Eric Engestrom [Sat, 3 Aug 2019 00:38:26 +0000 (01:38 +0100)]
swr: use LLVM version string instead of re-computing it

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agollvmpipe: use LLVM version string instead of re-computing it
Eric Engestrom [Sat, 3 Aug 2019 00:38:20 +0000 (01:38 +0100)]
llvmpipe: use LLVM version string instead of re-computing it

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoscons: define MESA_LLVM_VERSION_STRING like the other build systems do
Eric Engestrom [Sat, 3 Aug 2019 00:49:11 +0000 (01:49 +0100)]
scons: define MESA_LLVM_VERSION_STRING like the other build systems do

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: Disable NGG for geometry shaders.
Bas Nieuwenhuizen [Sun, 18 Aug 2019 23:36:06 +0000 (01:36 +0200)]
radv: Disable NGG for geometry shaders.

A bunch of remaining issues including some that affect users.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111248
Fixes: ee21bd7440c "radv/gfx10: implement NGG support (VS only)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoutil/timespec: use unsigned 64 bit integers for nsec values
Lionel Landwerlin [Wed, 21 Aug 2019 09:21:05 +0000 (11:21 +0200)]
util/timespec: use unsigned 64 bit integers for nsec values

We added this utility for vulkan where all timeouts are given as
uint64_t values. We can switch from signed to unsigned as this is the
only user and if we ever deal with signed integers somewhere else
we'll have to be careful to use the corresponding
timespec_(add|sub)_msec and always pass absolute values.

v2: Forgot to drop the test calling add_nsec() with a negative number

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Fixes: d2d70c3bb5 ("util: add a timespec helper")
Acked-by: Daniel Stone <daniels@collabora.com>
5 years agoiris/android: fix build and link with libmesa_intel_perf
Tapani Pälli [Tue, 13 Aug 2019 07:34:06 +0000 (10:34 +0300)]
iris/android: fix build and link with libmesa_intel_perf

Fixes: 0fd4359733e "iris/perf: implement routines to return counter info"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoac: fix exclusive scans on GFX8-GFX9
Samuel Pitoiset [Wed, 21 Aug 2019 14:29:46 +0000 (16:29 +0200)]
ac: fix exclusive scans on GFX8-GFX9

This fixes a regression introduced with scan&reduce operations
on GFX10. Note that some subgroups CTS still fail on GFX10 but
I assume it's a different issue.

This fixes dEQP-VK.subgroups.arithmetic.*.subgroupexclusive*.

Fixes: 227c29a80de "amd/common/gfx10: implement scan & reduce operations"
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoutil: fix os_create_anonymous_file on android
Tapani Pälli [Tue, 20 Aug 2019 05:59:23 +0000 (08:59 +0300)]
util: fix os_create_anonymous_file on android

Commit fixes current crashes with Vulkan applications on Android.

Fixes: c0376a123418 "util: add anon_file.h for all memfd/temp file usage"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoi965: honor scanout requirement from DRI
Lionel Landwerlin [Thu, 8 Aug 2019 08:40:30 +0000 (11:40 +0300)]
i965: honor scanout requirement from DRI

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
5 years agogallium/noop: Implement resource_get_param
Kenneth Graunke [Tue, 13 Aug 2019 21:33:35 +0000 (14:33 -0700)]
gallium/noop: Implement resource_get_param

v2: Pass through to oscreen rather than faking it (review from Marek).

Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/rbug: Wrap resource_get_param if available
Kenneth Graunke [Tue, 13 Aug 2019 21:32:57 +0000 (14:32 -0700)]
gallium/rbug: Wrap resource_get_param if available

Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/trace: Wrap resource_get_param if available
Kenneth Graunke [Tue, 13 Aug 2019 21:32:26 +0000 (14:32 -0700)]
gallium/trace: Wrap resource_get_param if available

Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/ddebug: Wrap resource_get_param if available
Kenneth Graunke [Tue, 13 Aug 2019 21:28:56 +0000 (14:28 -0700)]
gallium/ddebug: Wrap resource_get_param if available

Fixes: 0346b700833 ("gallium/screen: Add pipe_screen::resource_get_param")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agomesa: recover target_check before get_current_tex_objects
Jose Maria Casanova Crespo [Wed, 21 Aug 2019 12:16:16 +0000 (13:16 +0100)]
mesa: recover target_check before get_current_tex_objects

At compressed_tex_sub_image we only can obtain the tex_object after
compressed_subtexture_target_check is validated for TEX_MODE_CURRENT.
So if the target is wrong the error is raised to the user.

This completes the fix for the regression introduced on "mesa: refactor
compressed_tex_sub_image function" of the pending failing tests:

dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage3d
dEQP-GLES31.functional.debug.negative_coverage.get_error.texture.compressedtexsubimage3d

v2: Fix warning that texObj might be used uninitialized (Gert Wollny)

Fixes: 7df233d68dc ("mesa: refactor compressed_tex_sub_image function")
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
5 years agogallium: Add buffer and configs handling or fp16 formats
Kevin Strasser [Fri, 25 Jan 2019 01:29:31 +0000 (17:29 -0800)]
gallium: Add buffer and configs handling or fp16 formats

Expose configs when allow_fp16_configs has been enabled and
DRI_LOADER_CAP_FP16 is set in the loader.

Also, make kms_swrast_dri respect format bpp, to allow for allocating
buffers wider than 32 bpp.

Make fp16 opt-in for gallium.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
5 years agoi965: Add handling for fp16 configs
Kevin Strasser [Fri, 25 Jan 2019 01:26:31 +0000 (17:26 -0800)]
i965: Add handling for fp16 configs

Expose configs when allow_fp16_configs has been enabled and
DRI_LOADER_CAP_FP16 is set in the loader.

Also, define a new dri configuration option so users can disable exposure of
fp16 formats. Make fp16 opt-in for i965.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
5 years agogbm: Add buffer handling and visuals for fp16 formats
Kevin Strasser [Fri, 25 Jan 2019 01:32:36 +0000 (17:32 -0800)]
gbm: Add buffer handling and visuals for fp16 formats

Define and set a new loader cap DRI_LOADER_CAP_FP16, indicating that gbm can
handle fp16 formats.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agodri: Add fp16 formats
Kevin Strasser [Fri, 25 Jan 2019 01:10:02 +0000 (17:10 -0800)]
dri: Add fp16 formats

Add dri formats for RGBA ordered 64 bpp IEEE 754 half precision floating
point. Leverage existing offscreen render support for
MESA_FORMAT_RGBA_FLOAT16 and MESA_FORMAT_RGBX_FLOAT16.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agoegl: Handle dri configs with floating point pixel data
Kevin Strasser [Fri, 25 Jan 2019 00:55:33 +0000 (16:55 -0800)]
egl: Handle dri configs with floating point pixel data

In the case that __DRI_ATTRIB_FLOAT_BIT is set in the dri config, set
EGL_COLOR_COMPONENT_TYPE_FLOAT_EXT in the egl config. Add a field to the
platform driver visual to indicate if it has components that are in floating
point form.

Signed-off-by: Kevin Strasser <kevin.strasser@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>