Luke Kenneth Casson Leighton [Fri, 6 Mar 2020 18:37:43 +0000 (18:37 +0000)]
add field decoder
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 23:08:22 +0000 (23:08 +0000)]
process fields to get positions associated with format
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 21:56:02 +0000 (21:56 +0000)]
decode power fields from Forms, section 1.6 of 2.07B ISA
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:42:14 +0000 (18:42 +0000)]
corrections on Form PowerDecoder
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:36:42 +0000 (18:36 +0000)]
whoops wrong numbering
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 18:35:55 +0000 (18:35 +0000)]
add "form" to power decode
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 12:30:05 +0000 (12:30 +0000)]
add more comments
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 12:14:35 +0000 (12:14 +0000)]
add comment docstring explaining power decoder
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:55:48 +0000 (03:55 +0000)]
whitespace
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:51:53 +0000 (03:51 +0000)]
add minor_19 patterns and extra/major
Luke Kenneth Casson Leighton [Thu, 5 Mar 2020 03:35:17 +0000 (03:35 +0000)]
3am coding. sigh. converted PowerDecoder to take list of namedtuples
can now pass in extra.csv and major.csv in setup
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 19:12:36 +0000 (19:12 +0000)]
add idea of Decoder namedtuple
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 17:32:00 +0000 (17:32 +0000)]
whoops realised that it is *PowerDecoder* args that need to become a list
Luke Kenneth Casson Leighton [Wed, 4 Mar 2020 16:49:01 +0000 (16:49 +0000)]
move default case out of switch, to make room for multiple switches
and a *list* of subdecoders
Michael Nolan [Wed, 4 Mar 2020 16:09:20 +0000 (11:09 -0500)]
Add suffix handling back in
Michael Nolan [Wed, 4 Mar 2020 16:09:06 +0000 (11:09 -0500)]
Generate ilang for whole decoder
Michael Nolan [Wed, 4 Mar 2020 15:42:47 +0000 (10:42 -0500)]
Add tests for minor_58 and minor_62
Michael Nolan [Wed, 4 Mar 2020 15:31:15 +0000 (10:31 -0500)]
Hierarchial decoder semi-working
Michael Nolan [Wed, 4 Mar 2020 14:40:23 +0000 (09:40 -0500)]
Add bit selectors for most of the tests
Michael Nolan [Wed, 4 Mar 2020 14:36:33 +0000 (09:36 -0500)]
Change decoder to take the bits to select of the opcode as parameter
Luke Kenneth Casson Leighton [Tue, 3 Mar 2020 19:26:11 +0000 (19:26 +0000)]
rename run_test so that nosetests3 doesnt complain
Luke Kenneth Casson Leighton [Tue, 3 Mar 2020 19:25:52 +0000 (19:25 +0000)]
move default values to power_enums.py
Luke Kenneth Casson Leighton [Tue, 3 Mar 2020 18:41:35 +0000 (18:41 +0000)]
experimenting getting power decoder into shape
Michael Nolan [Mon, 2 Mar 2020 15:40:28 +0000 (10:40 -0500)]
Add recursive decoding
Michael Nolan [Mon, 2 Mar 2020 15:24:16 +0000 (10:24 -0500)]
Add support for hierarchical decoding
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 20:21:54 +0000 (20:21 +0000)]
idea for sub-decoder
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 15:51:57 +0000 (15:51 +0000)]
sort out hacking of PowerDecoder to suit extra.csv
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 15:40:02 +0000 (15:40 +0000)]
correction on single bit flags
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 15:32:38 +0000 (15:32 +0000)]
fix up syntax errors in power_decoder
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 15:17:47 +0000 (15:17 +0000)]
missing commas
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 14:26:06 +0000 (14:26 +0000)]
add some basic comments to PowerOp and PowerDecoder classes
Luke Kenneth Casson Leighton [Sun, 1 Mar 2020 14:21:39 +0000 (14:21 +0000)]
separate out PowerOps from PowerDecoder, simplifies code and also makes
it possible to set (later) from explicit row specs (nop etc.)
Michael Nolan [Sat, 29 Feb 2020 22:45:02 +0000 (17:45 -0500)]
Add tests for minor_30 and minor_31 decoding tables
Michael Nolan [Sat, 29 Feb 2020 22:26:06 +0000 (17:26 -0500)]
Add default case to decoder
Michael Nolan [Sat, 29 Feb 2020 21:19:06 +0000 (16:19 -0500)]
Add fields from the ones in IBM's Microwatt
Michael Nolan [Sat, 29 Feb 2020 21:07:47 +0000 (16:07 -0500)]
Add decoder/test for minor_19 field
Michael Nolan [Sat, 29 Feb 2020 20:53:16 +0000 (15:53 -0500)]
Add code to download csv files from wiki if they don't exist
Michael Nolan [Sat, 29 Feb 2020 20:46:54 +0000 (15:46 -0500)]
Move enums to a separate file
Michael Nolan [Sat, 29 Feb 2020 20:37:35 +0000 (15:37 -0500)]
Correct cry in field from a single bit to an enum
Michael Nolan [Sat, 29 Feb 2020 20:27:05 +0000 (15:27 -0500)]
Cleanup testbench, add messages to assertions
Michael Nolan [Sat, 29 Feb 2020 20:16:30 +0000 (15:16 -0500)]
Add in remaining fields from major decoder
Michael Nolan [Sat, 29 Feb 2020 20:05:44 +0000 (15:05 -0500)]
Add signals for single bit flags in major.csv
Michael Nolan [Sat, 29 Feb 2020 19:46:57 +0000 (14:46 -0500)]
Add input and output register selector fields
Michael Nolan [Sat, 29 Feb 2020 19:35:02 +0000 (14:35 -0500)]
Minor cleanup
Michael Nolan [Sat, 29 Feb 2020 19:32:18 +0000 (14:32 -0500)]
Move decoder.py to power_major_decoder.py
Michael Nolan [Sat, 29 Feb 2020 19:27:03 +0000 (14:27 -0500)]
Add internal op field to major decoder
Michael Nolan [Sat, 29 Feb 2020 19:23:53 +0000 (14:23 -0500)]
Begin adding power ISA decoder
Tobias Platen [Sat, 25 Jan 2020 12:22:44 +0000 (13:22 +0100)]
convert ram tp modules
Tobias Platen [Fri, 24 Jan 2020 07:41:24 +0000 (08:41 +0100)]
translate slice_top and rab_slice from systemverilog to nmigen
Tobias Platen [Thu, 23 Jan 2020 10:51:52 +0000 (11:51 +0100)]
add more converted header files
Tobias Platen [Thu, 23 Jan 2020 09:44:44 +0000 (10:44 +0100)]
begin axi_rab to nmigen conversion
Luke Kenneth Casson Leighton [Fri, 17 Jan 2020 14:14:18 +0000 (14:14 +0000)]
update to new revision nmigen
Luke Kenneth Casson Leighton [Fri, 17 Jan 2020 13:57:54 +0000 (13:57 +0000)]
get familiar with tests again
Tobias Platen [Mon, 16 Sep 2019 16:42:15 +0000 (18:42 +0200)]
tlb_content now supports 512G pages
Tobias Platen [Wed, 11 Sep 2019 19:14:11 +0000 (21:14 +0200)]
terapage lookup
Tobias Platen [Tue, 10 Sep 2019 19:35:27 +0000 (21:35 +0200)]
tlb_content update test
Tobias Platen [Mon, 9 Sep 2019 18:31:06 +0000 (20:31 +0200)]
add unittest for tlb_content.py
Tobias Platen [Sun, 25 Aug 2019 17:31:34 +0000 (19:31 +0200)]
forgot to add one signal
Tobias Platen [Sat, 24 Aug 2019 14:15:19 +0000 (16:15 +0200)]
add is_512G to the data structure
Tobias Platen [Wed, 7 Aug 2019 18:31:43 +0000 (20:31 +0200)]
partial Unit Test for TLB
Tobias Platen [Sun, 4 Aug 2019 12:15:01 +0000 (14:15 +0200)]
tlb_test WIP
Luke Kenneth Casson Leighton [Thu, 1 Aug 2019 07:49:08 +0000 (08:49 +0100)]
move priority picker to nmutil
Tobias Platen [Thu, 25 Jul 2019 19:43:00 +0000 (21:43 +0200)]
Merge branch 'master' of https://git.libre-riscv.org/git/soc
Tobias Platen [Thu, 25 Jul 2019 19:41:37 +0000 (21:41 +0200)]
fix UnusedElaboratable warning in TLB code
Luke Kenneth Casson Leighton [Wed, 24 Jul 2019 21:47:32 +0000 (22:47 +0100)]
add TLB elaboratable
Tobias Platen [Sun, 21 Jul 2019 16:09:19 +0000 (18:09 +0200)]
TLB testbench WIP
isengaara [Sun, 21 Jul 2019 11:31:43 +0000 (13:31 +0200)]
implement page table lookup using 4 levels
Luke Kenneth Casson Leighton [Wed, 19 Jun 2019 06:02:15 +0000 (07:02 +0100)]
forgot to pull ld_o/st_o through from LDST CompUnits
Luke Kenneth Casson Leighton [Wed, 19 Jun 2019 05:47:01 +0000 (06:47 +0100)]
sort out address match global nomatch signal
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 16:09:35 +0000 (17:09 +0100)]
move mem into scoreboard (really should be outside, as should regfile)
add mempick GroupPicker
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 12:39:46 +0000 (13:39 +0100)]
add separate read/write port
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 09:28:15 +0000 (10:28 +0100)]
whoops syntax error
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 09:27:50 +0000 (10:27 +0100)]
write out data only on go_write
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 09:03:52 +0000 (10:03 +0100)]
clarify comment
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 09:01:26 +0000 (10:01 +0100)]
add address and output mode from LDSTCUs
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 08:26:25 +0000 (09:26 +0100)]
sort out go_ld_i and go_st_i
Luke Kenneth Casson Leighton [Tue, 18 Jun 2019 06:13:53 +0000 (07:13 +0100)]
add temporary immediate-activation of go_addr on adr_rel request
Luke Kenneth Casson Leighton [Mon, 17 Jun 2019 06:05:13 +0000 (07:05 +0100)]
add transitive accumulation of LD/STs into MDM
Luke Kenneth Casson Leighton [Mon, 17 Jun 2019 05:50:29 +0000 (06:50 +0100)]
remove TODO (done)
Luke Kenneth Casson Leighton [Sun, 16 Jun 2019 13:38:51 +0000 (14:38 +0100)]
fix several test imports, add Elaboratable
Luke Kenneth Casson Leighton [Sun, 16 Jun 2019 13:32:54 +0000 (14:32 +0100)]
fix test run errors
Luke Kenneth Casson Leighton [Sat, 15 Jun 2019 13:10:03 +0000 (14:10 +0100)]
rename match to nomatch, connect ld_i and st_i
Luke Kenneth Casson Leighton [Sat, 15 Jun 2019 07:41:48 +0000 (08:41 +0100)]
convert addr match into latched (SRLatch) version, activate on req_rel,
deactivate on busy
Luke Kenneth Casson Leighton [Sat, 15 Jun 2019 04:58:13 +0000 (05:58 +0100)]
use new ready/valid to ALU in CompLDST
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 12:07:05 +0000 (13:07 +0100)]
start connecting memory function unit
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 11:52:57 +0000 (12:52 +0100)]
only set adr_rel_o on LD or ADD/SUB, must wait for go_ad_i
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 10:34:14 +0000 (11:34 +0100)]
starting to run into things being broken in LD/ST Comp (yay)
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 10:16:19 +0000 (11:16 +0100)]
properly set the number of integer ALUs (2 at the moment)
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 10:12:09 +0000 (11:12 +0100)]
set number of ALUs to 2
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 09:18:00 +0000 (10:18 +0100)]
test LD/ST issue
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 08:03:38 +0000 (09:03 +0100)]
add in ld/st operand pseudo-opcode
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 07:41:36 +0000 (08:41 +0100)]
add in a TestMemory class
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 05:03:25 +0000 (06:03 +0100)]
added in the LD/ST Comp Unit (not connected up yet) and the code didnt fall over
amazing that the unit test still runs, first time.
particularly that the number of INT ALUs was reduced from 4 to 2
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 04:30:41 +0000 (05:30 +0100)]
move MemFunctionUnits to separate module
Luke Kenneth Casson Leighton [Mon, 10 Jun 2019 04:24:55 +0000 (05:24 +0100)]
move FUMemMatchMatrix to mdm module
Luke Kenneth Casson Leighton [Sun, 9 Jun 2019 11:25:51 +0000 (12:25 +0100)]
link address matching inputs to outside MemMatrix, preliminary test works
Luke Kenneth Casson Leighton [Sun, 9 Jun 2019 10:53:41 +0000 (11:53 +0100)]
bring in cancel array into FURegDepMatrix
use in class which merges Partial Addr Match with FURegDepMatrix to
create a MDM (Memory Dependency Matrix)
Luke Kenneth Casson Leighton [Sun, 9 Jun 2019 08:48:43 +0000 (09:48 +0100)]
make partialaddrmatch a matrix
Luke Kenneth Casson Leighton [Sat, 8 Jun 2019 23:41:24 +0000 (00:41 +0100)]
rename variables
Luke Kenneth Casson Leighton [Sat, 8 Jun 2019 13:50:59 +0000 (14:50 +0100)]
add 2nd test for mem dependency, use FU-Regs and FU-FU matrices