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Wesley W. Terpstra [Mon, 5 Mar 2018 23:45:01 +0000 (15:45 -0800)]
platforms: fixup to new package names
Wesley W. Terpstra [Mon, 5 Mar 2018 23:14:23 +0000 (15:14 -0800)]
submodules: bump again for the latest refactor
Wesley W. Terpstra [Sun, 25 Feb 2018 23:08:30 +0000 (15:08 -0800)]
fpga-shells: bump to fix timing closure
Wesley W. Terpstra [Sun, 25 Feb 2018 18:33:25 +0000 (10:33 -0800)]
build: update all submodules to their current master
Megan Wachs [Wed, 22 Nov 2017 21:42:22 +0000 (13:42 -0800)]
Merge pull request #44 from sifive/bump-sifive-blocks
bump sifive-blocks for GPIO IOF fix
Megan Wachs [Wed, 22 Nov 2017 20:26:49 +0000 (12:26 -0800)]
bump sifive-blocks for GPIO IOF fix
Megan Wachs [Fri, 3 Nov 2017 23:59:30 +0000 (16:59 -0700)]
Add links to some documents for E300 Arty Dev Kit (#41)
Wesley W. Terpstra [Fri, 3 Nov 2017 23:59:17 +0000 (16:59 -0700)]
Merge pull request #40 from sifive/bump
Bump all hardware to the newest versions
Wesley W. Terpstra [Fri, 3 Nov 2017 19:53:00 +0000 (12:53 -0700)]
README: note the vivado version requirements
Wesley W. Terpstra [Thu, 2 Nov 2017 22:32:31 +0000 (15:32 -0700)]
unleashed: build quad-core instead
Because there are boot loaders out there that disable core 0, let's
make sure the open source design has >1 core to prevent these images
from hanging. We should also change freedom-u-sdk to check using DTS
to determine which cores to disable to properly fix this problem.
Wesley W. Terpstra [Fri, 3 Nov 2017 18:42:52 +0000 (11:42 -0700)]
sdboot: support SMP boot
Wesley W. Terpstra [Thu, 2 Nov 2017 22:21:39 +0000 (15:21 -0700)]
u500: enable FPU; needed by linux
Wesley W. Terpstra [Fri, 3 Nov 2017 18:20:08 +0000 (11:20 -0700)]
README: update location of built files
Wesley W. Terpstra [Thu, 2 Nov 2017 21:43:04 +0000 (14:43 -0700)]
freedom: bump submodules to their respective masters
Shreesha Srinath [Sun, 20 Aug 2017 08:39:45 +0000 (01:39 -0700)]
README: Updates to build bootloaders
Shreesha Srinath [Sat, 19 Aug 2017 01:21:04 +0000 (18:21 -0700)]
Updates to Freedom SoCs
Richard Xia [Thu, 8 Dec 2016 20:14:17 +0000 (12:14 -0800)]
Add variable to control what program gets flashed to FPGA.
Wesley W. Terpstra [Thu, 1 Dec 2016 22:06:37 +0000 (14:06 -0800)]
README: our systems are untethered
Richard Xia [Thu, 1 Dec 2016 19:05:18 +0000 (11:05 -0800)]
Merge pull request #6 from sifive/remove-consts-vh
Remove verilog header files built from Chisel .prm file.
Richard Xia [Wed, 30 Nov 2016 23:00:50 +0000 (15:00 -0800)]
Also remove unused .prm file from Makefile.
Richard Xia [Wed, 30 Nov 2016 22:30:05 +0000 (14:30 -0800)]
Remove verilog header files built from Chisel .prm file.
Henry Styles [Wed, 30 Nov 2016 04:38:00 +0000 (20:38 -0800)]
Merge pull request #4 from sifive/fix_u500vc707devkit_dot_img
Update U500 VC707 Dev Kit BootROM image for SDBoot
Henry Styles [Wed, 30 Nov 2016 04:32:16 +0000 (20:32 -0800)]
fix U500 BootROM image for SDBoot
Olof Kindgren [Tue, 29 Nov 2016 22:22:26 +0000 (23:22 +0100)]
Use public accessible URL for submodules
SiFive [Tue, 29 Nov 2016 13:23:27 +0000 (05:23 -0800)]
Add submodules.
SiFive [Tue, 29 Nov 2016 13:23:11 +0000 (05:23 -0800)]
Initial commit.
projects / freedom-sifive.git / log