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(parent: da744a1) | patch
dcache 2nd stage (r1) should only indicate not-busy
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 12 Jan 2022 12:11:12 +0000 (12:11 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 12 Jan 2022 12:11:12 +0000 (12:11 +0000)
commita03aefb1e8ae7d6110a328b57f1336890ebee469
tree074e6d8d4834246a26091202b7a869a67cc66018tree
parentda744a15dc07e13ecac5ca539912111572a0da7bcommit | diff
dcache 2nd stage (r1) should only indicate not-busy
(r1.full) when all the ACKs of a cache-line fill have been processed
doing this too early results in r0 being pushed into r1 whilst
ACKs are still outstanding, and their completion corrupts the
operation that should not have been put into r1 in the first place
src/soc/experiment/dcache.py diff | blob | history